A Low-Power Comparator-Based Automatic Power and Modulation Control Circuit for VCSEL Drivers
Round 1
Reviewer 1 Report
Comments and Suggestions for AuthorsThis paper presents an integrated circuit including control loops for power and modulation of a VCSEL diode. by sensing the VCSEL voltage during both modulation on and off states, the bias current is adjusted to prevent degradation of the transfer characteristic, avoiding the need of additional monitoring photodiodes. The proposed system comprises a peak detector, sample&hold, comparator and counter blocks, generating digital signal used for power and modulation control. The authors are invited to address the following comments in view of possible publication of their manuscript.
- Specifications adopted in the design process of the proposed circuits are not entirely clear. What performance requirement determines the reported power consumption? Can power be scaled down without degrading performance? How frequently should the control loops act?
- Compared to some of the other works in table 1, the proposed work has a relatively low width of the digital control words (4 bits). How did the authors determine that 4 bits are enough for the intended application?
- 5(a): the method employed to generate the bias current (series connection of R1 and diode-connected M8) is highly dependent on process-voltage-temperature (PVT) variations. For enhanced robustness, an actual reference current block should be used, generating bias current compensated against PVT variations. To address this point, the authors might point out that current references might be employed to improve robustness in this respect, mentioning references such as doi: 10.1109/PRIME58259.2023.10161864.
- 5(b) is not straightforward to understand, the authors might improve its clarity.
- Simulation results should be reported also under varying temperature conditions, since, in the introduction, the authors mentioned that temperature variations are among the causes of degradation of the VCSEL transfer characteristic (Fig. 1).
- Details on the employed electrical simulation tools should be added, including details on the mixed-signal simulation environment that has maybe been used.
- Were any of the digital blocks designed through a standard-cell design flow based on a VHDL or Verilog description? Or were all digital blocks designed with a custom flow? Please provide details.
- Transistor-level schematic view of the comparator might also be added.
Author Response
This paper presents an integrated circuit including control loops for power and modulation of a VCSEL diode. By sensing the VCSEL voltage during both modulation on and off states, the bias current is adjusted to prevent degradation of the transfer characteristic, avoiding the need of additional monitoring photodiodes. The proposed system comprises a peak detector, sample&hold, comparator and counter blocks, generating digital signal used for power and modulation control. The authors are invited to address the following comments in view of possible publication of their manuscript.
1. Specifications adopted in the design process of the proposed circuits are not entirely clear. What performance requirement determines the reported power consumption? Can power be scaled down without degrading performance? How frequently should the control loops act?
(ans.) In this paper, we have focused on describing the method by which the APMC loop operates, rather than detailing the specific circuit specifications. Each stage of the proposed circuit is set with the minimum bias current required to drive the next stage effectively. Therefore, it would be difficult to reduce the power consumption further without degrading the performance. Also, the control loop is activated whenever the degradation of the VCSEL diode's performance is detected.
2. Compared to some of the other works in table 1, the proposed work has a relatively low width of the digital control words (4 bits). How did the authors determine that 4 bits are enough for the intended application?
(ans.) The 4-bit digital control appears relatively short when compared to the prior works shown in Table 1. In previous works, however, the digital code typically represented a value converted through ADCs. Therefore, longer bit-lengths indicated finer detection resolution. In contrast, this paper focuses on counting the number of compensation actions based on a given reference voltage. Hence, longer bit-lengths would simply allow for more compensation cycles. So, we reckon that 4-bits are sufficient for the intended application based on the findings in Ref. [5,6] where the threshold current of a VCSEL diode increased up to 1 mA because of the temperature rise. Since the threshold for compensation is set to a 0.5-mA increase in the threshold current, it is sufficient to perform the compensation twice. Nonetheless, the number of compensation cycles is set to four so as to provide margin.
3. 5(a): the method employed to generate the bias current (series connection of R1 and diode-connected M8) is highly dependent on process-voltage-temperature (PVT) variations. For enhanced robustness, an actual reference current block should be used, generating bias current compensated against PVT variations. To address this point, the authors might point out that current references might be employed to improve robustness in this respect, mentioning references such as doi: 10.1109/PRIME58259.2023.10161864.
(ans.) As commented, the reference current generated by R1 and a diode-connected M8 is highly sensitive to PVT variations. This issue is described in the main text. We have also mentioned that a circuit for generating a reference current, which is less sensitive to PVT variations, can be introduced.
4. 5(b) is not straightforward to understand, the authors might improve its clarity.
(ans.) We have revised the paragraph, as follows.
“Figure 5b illustrates the schematic diagram of the S/H circuit which uses a chain of MOSFET transmission gates (TG) to control the connection between IN and OUT nodes depending on the clock signal (CLK). Here, a TG chain structure including dummy switches is employed to suppress any voltage disturbance caused by the charge injection from the channel to adjacent nodes, and also to minimize inevitable mismatches. When CLK is low (‘0’), the IN and OUT nodes are disconnected. This allows the IN node to sample the voltage from the previous stage. As CLK transitions to high (‘1’), M5 and M6 are turned ON, thus forming a conductive channel that transfers the sampled voltage to the OUT node. When CLK returns to low (‘0’), M5 and M6 are turned OFF, disconnecting the IN and OUT and allowing the output node to hold the sampled voltage.”
5. Simulation results should be reported also under varying temperature conditions, since, in the introduction, the authors mentioned that temperature variations are among the causes of degradation of the VCSEL transfer characteristic (Fig. 1).
(ans.) The simulation results of the APMC under varying temperature conditions are provided in Figure 16.
6. Details on the employed electrical simulation tools should be added, including details on the mixed-signal simulation environment that has maybe been used.
(ans.) All simulations were performed in Cadence Virtuoso using the Spectre simulator within the ADEL environment. Digital blocks are also custom-designed at the transistor level and directly integrated on-chip. Therefore, we did not need mixed-signal simulation environments.
7. Were any of the digital blocks designed through a standard-cell design flow based on a VHDL or Verilog description? Or were all digital blocks designed with a custom flow? Please provide details.
(ans.) All digital blocks employed in the APMC were designed by using a full-custom flow. We have clarified this point in the revised manuscript.
8. Transistor-level schematic view of the comparator might also be added.
(ans.) The figure and description of the comparator circuit have been added to the main text.
Reviewer 2 Report
Comments and Suggestions for AuthorsThe paper presents an automatic power and modulation control (APMC) circuit for vertical cavity surface emitting laser (VCSEL) diodes, which aims to detect device degradation through a novel voltage sensing mechanism, eliminating the need for external photodiodes. We have identified several significant issues that, in our view, make the paper unsuitable for publication in the journal.
- Insufficient Explanation of Voltage Monitoring Logic and the Relationship Between Electrical and Optical Power
The paper proposes using voltage sensing as a means to monitor VCSEL degradation. However, it lacks a sufficient theoretical or experimental explanation of why voltage alone is a reliable indicator of optical power changes. It is well known that variations in electrical power do not always correspond directly to optical output, especially during device aging. To strengthen the technical foundation of the work, the authors are advised to:
a). Clarify the physical mechanism linking voltage drift to optical degradation.
b). Provide a model or analysis that establishes the correlation between junction voltage and optical efficiency under constant current operation.
c). Discuss any assumptions or operational constraints (e.g., fixed bias conditions) that are necessary for the method to remain valid.
d). This explanation should be added to the “Working Principle” or “Discussion” section of the manuscript.
- Lack of Experimental Validation of Functional Performance
Currently, the experimental results are limited to simulations that mainly demonstrate advantages in terms of area and power consumption. However, there is no experimental validation regarding the actual performance of the APMC circuit in detecting and compensating for VCSEL degradation. The authors should consider adding:
a). Experimental data showing how the voltage sensing responds to VCSEL degradation over time, preferably under accelerated aging conditions.
b). Demonstration of the closed-loop control functionality—i.e., how the system adjusts the driving current in response to detected voltage changes to maintain stable optical output.
c). Graphs or tables comparing voltage trends, optical power measurements, and control responses across different stages of device life.
d). If hardware implementation is not feasible, the limitations should be clearly stated, and supporting evidence from prior experimental studies should be referenced.
- Image Quality Issues
Some figures in the manuscript suffer from poor resolution or clarity. For example, Figure 7 appears blurry and difficult to interpret, while Figure 8 is clear and well-rendered. It is recommended that all figures be re-examined and improved to meet publication standards. Specifically:
a). Ensure all images have a minimum resolution of 300 dpi.
b). Use vector-based formats (e.g., PDF, SVG) where possible to avoid pixelation.
c). Maintain consistent formatting and labeling across all figures.
- Need for More Detailed Figure Captions
The captions accompanying some figures lack sufficient detail for readers to fully understand the content without referring back to the main text. To improve clarity and accessibility:
a). Each caption should describe what the figure shows, including the type of data or schematic, the meaning of symbols or colors, and the experimental or simulation conditions.
b). Technical components or key parameters should be briefly explained in the caption itself.
- Outdated Comparative Methods
The comparative methods cited in the paper are largely from over a decade ago, with some dating back as far as 2009. In order to better position the proposed APMC circuit in the context of current research and enhance the paper’s credibility, comparisons should also be made with recent advancements in similar areas. The authors are encouraged to:
a). Include recent literature (within the past 3–5 years) that explores integrated monitoring techniques or low-power control schemes for VCSELs.
b). Update comparison tables or discussion sections to reflect modern benchmarks.
c). Highlight how the proposed method improves upon or differs from these newer approaches in terms of complexity, cost, and performance.
Author Response
Dear Reviewer,
Please find the attached file that is our answer sheet for your valuable comments.
Best regards,
Sung Min Park
Author Response File: 
Author Response.pdf
Reviewer 3 Report
Comments and Suggestions for AuthorsAuthors propose a low Power comparator-based automatic power and modulation control circuit for vertical cavity surface emitting laser drivers.
Generally speaking the paper is well-written and should be slightly re-organized. Simulation results are reported to validate the proposed system.
My further comments are in the following.
1) Introduction is confusing because it reports the previous art but also the proposed topology. Reviewer would like to suggest to re-organized this first part. In particular, introduction should report previous art and methods, a brief description of the proposed solution and the description of the structure of the paper. The proposed solution scheme, i.e. Fig. 2c, should be shown when the proposal is in-depth described (Section 2).
2) Transistors in Fig. 5b, S/H circuit, should be named and it should be clearly stated which compose the switches and which the capacitors. Further, about the involved OTAs, Reviewer would suggest claiming that there are different solutions of OTAs (single- or multi-stage) that can be used, as an example the following
Ballo, A.; Grasso, A.D.; Pennisi, S. 0.4-V, 81.3-nA Bulk-Driven Single-Stage CMOS OTA with Enhanced Transconductance. Electronics 2022, 11, 2704. https://doi.org/10.3390/electronics11172704
3) There is a red-colored sentence in line 147. Probably, it is a typo.
4) The reported results are simulated and the Authors show the layout also. I can deduce that the simulation results come from post-layout? Or are referred to pre-layout. I suggest to specify it.
5) Being only simulation results reported, what about corner (PVT variations) and MC simulations? Authors should report these too.
6) The advantages of the proposed system should be clearly stated along the paper.
Author Response
Authors propose a low Power comparator-based automatic power and modulation control circuit for vertical cavity surface emitting laser drivers. Generally speaking the paper is well-written and should be slightly re-organized. Simulation results are reported to validate the proposed system. My further comments are in the following.
1. Introduction is confusing because it reports the previous art but also the proposed topology. Reviewer would like to suggest to re-organized this first part. In particular, introduction should report previous art and methods, a brief description of the proposed solution and the description of the structure of the paper. The proposed solution scheme, i.e. Fig. 2c, should be shown when the proposal is in-depth described (Section 2).
(ans.) We have revised the manuscript as commented. The introduction has been reorganized to include the prior arts and methods, and followed by a brief description of the proposed solution. The detailed description of Figure 2c has been moved to Section 2.
2. Transistors in Fig. 5b, S/H circuit, should be named and it should be clearly stated which compose the switches and which the capacitors. Further, about the involved OTAs, Reviewer would suggest claiming that there are different solutions of OTAs (single- or multi-stage) that can be used, as an example the following
Ballo, A.; Grasso, A.D.; Pennisi, S. 0.4-V, 81.3-nA Bulk-Driven Single-Stage CMOS OTA with Enhanced Transconductance. Electronics 2022, 11, 2704. https://doi.org/10.3390/electronics 11172704.
(ans.) We have updated Figure 5b to clearly name the transistors. Also, alternative structures such as single-stage or multi-stage OTAs can be used. We have stated this in the manuscript.
3. There is a red-colored sentence in line 147. Probably, it is a typo.
(ans.) The typo in line 147 has been corrected.
4. The reported results are simulated and the Authors show the layout also. I can deduce that the simulation results come from post-layout? Or are referred to pre-layout. I suggest to specify it.
(ans.) The reported results are obtained from the post-layout simulations. This has been clarified in the revised manuscript.
5. Being only simulation results reported, what about corner (PVT variations) and MC simulations? Authors should report these too.
(ans.) The simulation results of the APMC under varying temperature conditions are provided in Figure 16.
6. The advantages of the proposed system should be clearly stated along the paper.
(ans.) We have revised the manuscript.
Round 2
Reviewer 2 Report
Comments and Suggestions for AuthorsThe manuscript requires revisions to better clarify its novelty. Specific suggestions are as follows:
1 The method proposed in Reference 11 achieves AMC and APC through voltage detection. Please clearly distinguish between the content cited from Reference 11 and the original contributions of this work in the text, ensuring the innovation of the proposed approach is explicitly emphasized.
2 A quantitative comparison with Reference 11 should be added in the comparison section to substantiate the claimed advantages of your approach.
Author Response
1. The method proposed in Reference 11 achieves AMC and APC through voltage detection. Please clearly distinguish between the content cited from Reference 11 and the original contributions of this work in the text, ensuring the innovation of the proposed approach is explicitly emphasized.
--> (ans.) Thank you for this comment. The distinction between this work and Reference [11] has been explicitly addressed and added to the main text (line 61-70), as below.
“Nonetheless, this structure relies on the internal analog-to-digital converter (ADC) within the APC and AMC blocks, inevitably increasing the circuit complexity and resource usage. In addition, a prior APC-specific approach employing low-pass filters (LPFs) for voltage averaging mandates the use of capacitors, which are generally large in physical size. The inclusion of such components leads to the enlarged chip area, which is undesirable particularly for the applications targeting high integration and low power consumption characteristics. Therefore, this paper proposes a comparator-and-counter-based automatic power and modulation control (APMC) circuit that can eliminate the requirements of MPDs, ADCs, or large passive components, thereby achieving improved compactness and system efficiency.”
2. A quantitative comparison with Reference 11 should be added in the comparison section to substantiate the claimed advantages of your approach.
--> (ans.) A detailed comparison with Reference [11] has been incorporated into both the comparison table and the corresponding discussion in the revised manuscript (line -280), as below.
“Ref. [11] proposed an analog APC architecture that utilized a low-pass filter (LPF) to extract the average voltage. While the overall structure was relatively simple, the LPF required a physically large capacitor, thus resulting in an increased overall chip area. In addition, LPF-based approaches inherently produced ripples. In this case, a bias current ripple of approximately 0.5 mA was observed. The presence of such ripple indicates that the VCSEL cannot be maintained in a stable manner. Furthermore, Ref. [11] addressed only the APC functionality without incorporating AMC.”
Reviewer 3 Report
Comments and Suggestions for AuthorsAuthors have addressed my comments. However, the introduction lacks of the brief description of paper structure. Reviewer would like to sugget to add it and better explain the advantages and novelty of the proposal.
Author Response
Authors have addressed my comments. However, the introduction lacks of the brief description of paper structure. Reviewer would like to suggest to add it and better explain the advantages and novelty of the proposal.
--> (ans.) Thank you for the comment. A brief overview of the proposed method has been included in the introduction section (line 71-75), as below.
“VCSEL degradation is detected by monitoring the voltage drop at the anode of the utilized VCSEL diode. When the sensed voltage falls below a predefined reference level, a logic '1' is generated by the comparator. Then, the logic high outputs are counted by using a digital counter, therefore resulting in a 4-bit digital code that represents the degree of degradation. All digital circuits are implemented by using full-custom design methodology.”
