Design and Optimization of Optical NAND and NOR Gates Using Photonic Crystals and the ML-FOLD Algorithm

Abstract

The continuous demand for faster processing systems, driven by the rise of artificial intelligence, has exposed limitations in traditional transistor-based electronics, including quantum tunneling, heat dissipation, and switching delays due to challenges in further miniaturization. This study explores optical systems as a promising alternative, leveraging the speed of photons over electrons. Specifically, we design and simulate optical NAND and NOR logic gates using a two-dimensional photonic crystal structure with a square lattice. Symmetrical waveguides are used for the input paths to make the structure relatively more straightforward to fabricate. A key innovation is the ability to realize both gates within a single structure by adjusting the phases of the input sources. To optimize the phase parameters efficiently, we employ the ML-FOLD (Meta-Learning and Formula Optimization for Logic Design) optimization formula, which outperforms traditional methods and machine learning approaches in terms of computational efficiency and data requirements. Through finite-difference time-domain (FDTD) simulations, the proposed optical structure demonstrates successful implementation of NAND and NOR gate logic, achieving high contrast ratios of 4.2 dB and 4.8 dB, respectively. The results validate the effectiveness of the ML-FOLD method in identifying optimal configurations, offering a streamlined approach for the design of all-optical logic devices.

1. Introduction

Digital and computer systems have become an inseparable part of human life, with an ever-increasing demand for faster processors. This demand has surged even further following the advent and widespread adoption of artificial intelligence (AI) [1,2]. Modern digital systems rely on transistors for switching operations and information processing [3,4,5,6,7,8]. Over the years, the size of transistors has been progressively reduced; however, this continuous downsizing now faces significant challenges, making further reductions increasingly difficult and, in some cases, impractical. Consequently, this justifies the exploration of alternative methods and systems to replace transistors [9,10,11,12].

One promising alternative to electronic systems is the use of optical systems. In electronic devices, electrons are utilized for processing, whereas optical systems employ photons [13,14,15]. Photons travel significantly faster than electrons, resulting in a substantial increase in the speed of optical systems compared to their electronic counterparts. Among the suitable platforms for implementing optical devices, photonic crystals have garnered considerable attention from researchers in recent years [16,17,18,19]. The ability to control and guide light within compact structures is a key advantage of photonic crystals over other platforms for optical device implementation [20,21,22]. Photonic crystals have been utilized in developing optical sensors, photonic crystal lasers, and optical logic gates such as AND, OR, NAND, and NOR, in addition to logic circuits like half-adders, full-adders, multiplexers, and various other logical systems [23,24,25,26,27,28].

The design and optimization of all-optical logic gates present significant challenges, particularly in precisely tuning key parameters such as phase shift (φ), lattice constant, rod radius, and refractive index. Achieving optimal performance requires balancing multiple variables to maximize metrics like contrast ratio and minimize signal loss in photonic crystal-based structures [29,30]. Traditional optimization methods, such as finite-difference time-domain (FDTD) simulations, are computationally intensive and iterative, often demanding extensive numerical calculations to identify suitable configurations [31,32,33,34,35,36,37,38,39]. This complexity is compounded by the need to explore a multidimensional parameter space, making the process time-consuming and resource-heavy.

Optimizing all-optical logic gates requires precise tuning of parameters such as phase shift (φ), lattice constant, and rod radius to maximize performance metrics like contrast ratio. Traditional methods, such as FDTD simulations, are computationally intensive due to complex parameter spaces [29,30]. Advanced approaches using machine learning and evolutionary algorithms (e.g., genetic algorithms) offer improvements but face challenges, including large dataset requirements, hyperparameter tuning, and high computational costs [1,8,12].

In the base study [1,8], the ML-FOLD (Meta-Learning and Formula Optimization for Logic Design) algorithm was applied within a machine learning framework to optimize phase configurations for XOR, NOT, and OR gates, necessitating extensive training data. In contrast, our study employs ML-FOLD as a deterministic optimization formula, eliminating machine learning dependencies. We optimize NAND and NOR gates using simple arithmetic operations to compute the optimize_R metric, which evaluates phase configurations based on output powers.

Our contributions are (1) a single photonic crystal structure achieving both NAND and NOR functionalities via phase adjustments; (2) a deterministic ML-FOLD algorithm for efficient phase optimization without machine learning; (3) unlike [8], which focused on XOR, OR, and NOT gates, this study applies the ML-FOLD method to NAND and NOR gates using a unified photonic crystal design, demonstrating its broader applicability; and (4) we made the code and dataset publicly available for reproducibility.

This approach offers key advantages:

• Low Data Needs: Requires minimal data compared to machine learning’s large datasets [1,8,12].
• Simplified Process: Avoids hyperparameter tuning and iterative learning.
• Efficiency: Uses basic arithmetic, outperforming iterative genetic algorithms.

FDTD simulations validate our approach, demonstrating high-accuracy NAND and NOR operations with superior contrast ratios, advancing efficient all-optical logic gate design.

2. Proposed Configuration for Realizing Optical NAND and NOR Gates

To implement optical NAND and NOR logic gates, a two-dimensional photonic crystal structure with a square lattice configuration is utilized. This structure exhibits a photonic bandgap under the transverse magnetic (TM) polarization, as depicted in the bandgap diagram presented in Figure 1.

Figure 1 shows that a photonic band gap is created in the structure in the normalized range of 0.28 to 0.42. Given that these values are related to ${\displaystyle \raisebox{1ex}{$a$}\!\left/ \!\raisebox{-1ex}{$\lambda $}\right.}$, the wavelength equivalent to this range can be calculated. This range is equivalent to $1.43\mathsf{\mu }\mathrm{m}<\lambda <2.14\mathsf{\mu }\mathrm{m}$.

Wavelengths that lie within this bandgap are restricted from propagating through the medium. The input signals are configured at a wavelength of 1.55 µm, which is located within the bandgap region of the designed structure. A comprehensive list of the structure’s physical specifications is provided in

Table 1. Characteristics of the initial photonic crystal design.

Parameter	Index	Value
Lattice Constant	a	0.6 µm
Radius of Rods	R	0.12 µm
Refractive Index of Background	n1	1
Refractive Index of Rods	n2	3.46
Number of Rods	-	21 × 15

.

According to Table 1, it can be seen that the structure has a lattice constant of 0.6 µm, and the radius of the rods is R = 0.12 µm. The refractive index of air is shown as n₁, and the refractive index of the rods is shown as n₂, where n₂ = 3.46. The proposed structure has dimensions such that the number of rods in the horizontal direction is 21 and in the vertical direction is 15.

By selectively removing specific rods, three waveguide paths are created to guide light from the input sources and a bias source into the structure. Additionally, another waveguide path is formed by removing further rods to direct light toward the output. Two defect rods, denoted as R1 and R2, are strategically placed at the ends of two waveguides to optimize the output power. The structural design utilized for implementing the proposed optical logic gates is shown in Figure 2. The phases of the laser sources are determined using the ML-FOLD optimization algorithm, which analyzes a small dataset of FDTD-simulated output powers to identify optimal configurations. The process involves calculating the optimization metric optimize_R (Equations (1) and (2)) for each phase pair, ranking them, and selecting the highest-scoring configuration, as detailed in Section 3.3. Specifically, for the NOR gate, the phases are set as φA = φB = 90°, while for the NAND gate, they are set as φA = 55° and φB = −170°.

Table 2. Logical states of NOR and NAND gates.

A	B	NAND	NOR
0	0	1	1
0	1	1	0
1	0	1	0
1	1	0	0

presents the logical states of the NAND and NOR gates. The simulation outcomes for the optical NAND and NOR gates, obtained through the FDTD method, are presented. These results include both the normalized output power and the optical power distribution across the structure, as illustrated in the corresponding figures.

Figure 2 illustrates the designed architecture for implementing optical NAND and NOR gates using a balanced configuration. The input channels are symmetrically arranged relative to each other, ensuring a mirrored structure with respect to the output channel. The bias signal, positioned between inputs A and B, maintains a constant phase of 0° across all scenarios to serve as a stable reference.

As shown in Figure 2, the two main inputs, A and B, are located on the left. The auxiliary input bias is also located between these two inputs. The role of the bias input is to provide output power when the main inputs are off. These three input paths are created for light propagation, which then intersect the waveguides. At the intersection of the waveguides, two rods are considered defect rods. These rods have a radius of R1 = R2 = 0.5R, where R is the radius of the other rods. The role of these defective rods is to control the optical power when light waves intersect and transmit it to the output.

3. Methods

This section outlines the methodology for optimizing all-optical NAND and NOR logic gates using a photonic crystal platform, focusing on determining optimal phase configurations (φA and φB) to achieve reliable logical operations.

3.1. Introduction to ML-FOLD Optimization

In designing and optimizing all-optical logic gates—specifically the NAND and NOR gates explored in this study—accurately selecting the phase parameters (φA and φB) is crucial to ensure proper interference behavior and desired output power levels. Conventional optimization strategies, such as finite-difference time-domain simulations with repetitive parameter tuning or more sophisticated methods like machine learning and genetic algorithms, typically require substantial computational power and large volumes of data. To overcome these challenges, this work adopts the ML-FOLD optimization formula—an efficient and uncomplicated mathematical technique that avoids the need for iterative convergence or extensive training datasets. First introduced in [8], the ML-FOLD method is utilized here to determine the optimal phase settings.

The ML-FOLD algorithm is a deterministic optimization method that evaluates a predefined set of phase combinations to identify configurations maximizing the optimize_R metric, calculated from normalized output powers (Equations (1) and (2)). In this study, phase combinations (e.g., 0°, 45°, 90°, 180°, and 245° for NOR; 0°, ±45°, ±90°, ±180°, 55°, and −170° for NAND) were predefined based on symmetry, interference patterns, and prior FDTD simulation insights to cover a representative range of interference scenarios.

3.2. ML-FOLD Formula and Rationale

The ML-FOLD optimization algorithm employs a concise formula to assess the suitability of phase combinations based on the normalized output powers for the four logical states of a two-input logic gate. The optimization metric, termed $optimize\text{\_}R$, slightly differs depending on the target logic gate due to their distinct truth tables. For the NOR gate, the formula is

$$optimize\text{\_}R={\displaystyle \frac{{\mathrm{preds}}_{A=0,B=0}}{{\mathrm{preds}}_{A=1,B=0}\times {\mathrm{preds}}_{A=0,B=1}\times {\mathrm{preds}}_{A=1,B=1}}}$$

(1)

For the NAND gate, it is adjusted to:

$$optimize\text{\_}R={\displaystyle \frac{{\mathrm{preds}}_{A=0,B=0}\times {\mathrm{preds}}_{A=1,B=0}\times {\mathrm{preds}}_{A=0,B=1}}{{\mathrm{preds}}_{A=1,B=1}}}$$

(2)

where

• $\left({\mathrm{preds}}_{A=1,B=0}\right)$: Output power when input A is active and B is inactive.
• $\left({\mathrm{preds}}_{A=0,B=1}\right):$ Output power when input A is inactive and B is active.
• $\left({\mathrm{preds}}_{A=1,B=1}\right)$: Output power when both inputs A and B are active.
• $\left({\mathrm{preds}}_{A=0,B=0}\right)$: Output power when both inputs A and B are inactive.

The rationale for these formulations aligns with the expected behavior of each gate:

• NOR Gate: A high output (logical “1”) is required only when both inputs are off (A = 0, B = 0), with low outputs (logical “0”) for all other states. A high $optimize\text{\_}R$ value thus indicates a large preds_AB_0 relative to the product of the other outputs, favoring configurations where the (0,0) state is distinctly prominent.
• NAND Gate: A low output (logical “0”) is expected only when both inputs are active (A = 1, B = 1), with high outputs (logical “1”) elsewhere. Here, a high $\mathrm{o}\mathrm{p}\mathrm{t}\mathrm{i}\mathrm{m}\mathrm{i}\mathrm{z}\mathrm{e}\text{\_}R$ reflects a small preds_AB_1 relative to the product of the other outputs, highlighting configurations that effectively suppress the (1,1) state.

The use of multiplication and division amplifies differences in performance across the logical states, providing a robust indicator of optimality without necessitating complex computations.

3.3. Implementation of ML-FOLD

The ML-FOLD algorithm was implemented using Python (version 3.12), with Pandas (version 2.2) and NumPy (version 1.26) libraries to efficiently process the simulation data.

Two datasets were analyzed: one for the NOR gate with 16 phase combinations and another for the NAND gate with 17 phase combinations. Each dataset includes phase angles $\left(\mathsf{\phi }\mathrm{A}\mathrm{a}\mathrm{n}\mathrm{d}\mathsf{\phi }\mathrm{B}\right)$ and the corresponding normalized output powers for the four input states obtained from FDTD simulations of the photonic crystal structure.

The implementation process includes the following steps:

• Data Preprocessing: The dataset is loaded into a Pandas DataFrame.
• Metric Calculation: The $\left({\mathrm{optimize}}_R\right)$ value is computed for each configuration using the formula above.
• Threshold Determination: A threshold for classification is established as 80% of the maximum $optimize\text{\_}R$ value ($threshold\text{\_}fraction=0.8$). This dynamic approach adapts to the dataset’s range, though alternatives such as the median or a fixed value could be considered. (The thresholds of 73.17 (NOR) and 0.674 (NAND) were set at 80% of the maximum optimize_R values to visually distinguish near-optimal configurations in plots (e.g., Figure 3 and Figure 4). These thresholds are not essential, as ML-FOLD ranks configurations by optimize_R to identify the optimum without categorization.)
• For the NOR gate, the maximum $optimize\text{\_}R$ was 91.46, resulting in a threshold of 73.17. For the NAND gate, the maximum was 0.843, yielding a threshold of 0.674.
• Classification: Each configuration is assigned a classification based on its $\left({\mathrm{optimize}}_R\right)$ value relative to the threshold.
• Final Stage: With the ranked results, we now have the best candidate, which has a high chance of being optimal, ready for final validation or implementation.

To visualize the optimization process, 3D scatter plots were generated for NOR and NAND gate datasets using Python and matplotlib. These plots show $\mathsf{\phi }\mathrm{A}$(x-axis, degrees), $\mathsf{\phi }\mathrm{B}$ (y-axis, degrees), and $optimize\text{\_}R$ (z-axis), with points colored green (“Optimal”, above threshold) or red (“Suboptimal”, below threshold). A blue plane marks the threshold (80% of max $optimize\text{\_}R$). “Optimal” points are annotated near their positions with phase pairs and $optimize\text{\_}R$ values, enhanced by white backgrounds with gray borders for readability.

4. Results

This section presents the outcomes of the optimization and simulation studies for the optical NOR and NAND gates. The analysis focuses on phase pair configurations, their corresponding optimization metrics (optimize_R), and the resulting output powers for all logical input states. The results are visualized in Figure 3 and Figure 4, which integrate 3D optimization plots with normalized optical power distributions for each gate, arranged vertically as generated by the provided Python script.

4.1. NOR Gate Optimization

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The dataset comprised 16 phase pairs, with $optimize\text{\_}R$ ranging from 0.275 to 91.46.

○

Two configurations were classified as “Optimal”: (90°, 90°) with $optimize\text{\_}R=75.76\mathrm{a}\mathrm{n}\mathrm{d}(90°,180°)$ with $optimize\text{\_}R$ = 91.46. The former aligns with this study’s reported NOR gate phases $(\phi A=\phi B=90°)$, producing outputs (0.6, 0.22, 0.20, 0.18), which correspond to NOR logic (1, 0, 0, 0) using thresholds of 0.5 for “1” and 0.3 for “0”. Figure 3 visualizes this, with annotated optimal points above the threshold plane.

4.2. NAND Gate Optimization

○

The dataset included 17 phase pairs, with $optimize\text{\_}R$ ranging from 0.162 to 0.843.

○

One configuration was classified as “Optimal”: (55°, −170°) with $optimize\text{\_}R=0.843$, precisely matching this study’s NAND gate phases. The outputs (0.6, 0.53, 0.53, 0.2) align with NAND logic (1, 1, 1, 0) using the same thresholds.

○

The formula accurately identifies a suppressed preds_AB_1 relative to the other states, validating its suitability for NAND optimization. Figure 4 illustrates this, with the annotated optimal point above the threshold.

4.3. Simulation Results for the Optical NOR Gate

To enhance clarity and enable more effective comparison across input states, the simulation results corresponding to the four logical combinations of the NOR gate have been integrated into Figure 5.

• Scenario a (A = 0, B = 0): When both input sources are inactive, the output is solely driven by the bias source, resulting in a normalized output power of 0.6, interpreted as a logical “1”.
• Scenario b (A = 0, B = 1): Activation of input B leads to destructive interference with the bias wave, reducing the output to 0.22, corresponding to a logical “0”.
• Scenario c (A = 1, B = 0): Similarly, activation of input A yields an output of approximately 0.2, due to destructive interference.
• Scenario d (A = 1, B = 1): When both inputs are active, combined destructive interference occurs, producing a minimal output of 0.18, also representing a logical “0”.

4.4. Simulation Outcomes of the Optical NAND Gate

Likewise, the simulation results of the NAND gate under all four logical input states are presented in an integrated Figure 6, allowing for a unified and comparative analysis.

• Scenario a (A = 0, B = 0): The absence of both inputs results in output power driven by the bias source, reaching 0.6, interpreted as logical “1”.
• Scenario b (A = 0, B = 1): With input B active, interference with the bias wave produces an output of 0.53, which is considered logical “1”.
• Scenario c (A = 1, B = 0): Input A is active, leading to a similar output of 0.53 due to the same interference conditions.
• Scenario d (A = 1, B = 1): Activation of both inputs results in strong destructive interference with the bias wave, reducing the output to 0.2, corresponding to a logical “0”.

5. Discussion

The ML-FOLD algorithm, as implemented in this study, primarily functions as a classification and ranking tool, evaluating a predefined set of phase combinations to identify optimal configurations for the NOR and NAND gates.

The ML-FOLD optimization method is built upon the inherent nonlinearity and sensitivity of optical interference patterns within photonic crystal waveguide structures. Specifically, the output power in such systems is not a linear function of the inputs; rather, it results from constructive and destructive interference effects influenced by phase differences. Because of this nonlinearity, small variations in phase can produce disproportionately large variations in output power, especially in critical states such as (A = 1, B = 1) for NAND or (A = 0, B = 0) for NOR. The ML-FOLD formula leverages this by applying a multiplicative ratio: the outputs that are desirable (i.e., should be maximized) are placed in the numerator, while those that must be suppressed (i.e., minimized) are placed in the denominator.

This formulation amplifies configurations where the desired outputs are significantly stronger than the undesired ones. For example, in the case of a NAND gate, the desired output is high for three of the four input conditions. Placing these high-output states in the numerator and the one low-output state (A = 1, B = 1) in the denominator magnifies the contrast between optimal and suboptimal phase configurations. This mechanism directly correlates with the physical goal: achieving sharp contrast between logic 1 and logic 0 across all input states with minimal power leakage or overlap.

In comparison to traditional optimization methods,

• FDTD iterative sweeps are computationally expensive and scale poorly with the number of parameters, as they lack a closed-form assessment metric.
• Genetic algorithms and ML models require extensive data and hyperparameter tuning, often leading to high computational costs and potential overfitting to simulation noise.
• ML-FOLD, in contrast, relies on only a small set of simulation results and uses simple arithmetic operations, allowing for rapid, interpretable evaluation of phase configurations.

The ML-FOLD algorithm exhibits exceptional efficiency in pinpointing optimal phase parameters with minimal data—16 and 17 points for NOR and NAND gates, respectively—compared to the extensive datasets typically required by machine learning models. Its arithmetic simplicity (multiplication and division) bypasses the computational burden of iterative methods like genetic algorithms, enabling rapid analysis on standard hardware. The threshold-based classification enhances decision-making clarity, although the selection of 80% as the fraction could be further optimized based on specific performance criteria, such as contrast ratio. Moreover, this method proves particularly advantageous when evaluating numerous configurations—e.g., 50 to 100 potential designs for a logic gate—enabling researchers to efficiently pinpoint the most promising candidates amidst uncertainty, thereby streamlining the optimization process.

The disparity in $optimize\text{\_}R$ ranges between the NOR gate (0.275–91.46) and the NAND gate (0.162–0.843) may indicate differences in simulation conditions or formula sensitivity, meriting additional scrutiny. Nonetheless, the precise alignment between ML-FOLD’s “Optimal” classifications and this study’s reported phases—(90°, 90°) for NOR and (55°, −170°) for NAND—underscores its practical applicability.

The results obtained are summarized in

Table 3. Summary of results obtained in different input modes.

Input State	NOR Output (Binary Equivalent)	CR (NOR)	NAND Output (Binary Equivalent)	CR (NAND)
00	0.6 (1)	4.8	0.6 (1)
01	0.2 (0)		0.53 (1)	4.2
10	0.2 (0)		0.53 (1)
11	0.18 (0)		0.2 (0)

. This table shows the structure’s different input and output states in NOR and NAND gate modes. This table shows the output power (binary equivalent) in each state. The contrast ratio (CR) parameter is also calculated in this table. This parameter is expressed as the relationship $\mathrm{C}\mathrm{R}=10\times \mathrm{l}\mathrm{o}\mathrm{g}{\displaystyle \frac{P1,min}{P0,max}}$ representing the power difference between high and low logic states.

To show the advantage of the proposed structure over previous research,

Table 4. Comparison of the proposed structure parameters with previous gates.

Ref.	Type	Size (µm2)	P0,max	P1,min	CR (dB)	Stable Time (ps)
[35]	NAND	390	0.15	0.50	5.18	0.67
	NOR	390	0.20	0.51	4	0.67
[36]	NAND	396	0.28	0.75	4.25	6
[37]	NAND	98	0.17	0.43	4	0.32
	NOR	98	0.21	0.43	3.1	0.32
[38]	NAND	56	0.24	0.29	0.85	3.33
	NOR	56	0.24	0.29	0.85	3.33
[39]	NAND	280	0.03	0.11	5.6	2.5
	NOR	280	0.04	0.34	9.2	2.5
This work	NAND	100	0.20	0.53	4.2	0.32
	NOR	100	0.20	0.60	4.8	0.32

can be seen. This table lists the important parameters of photonic crystal-based NAND/NOR gates, and the results obtained from the structure are compared with previous papers.

Table 4 compares the important parameters of NAND and NOR gates. The structure proposed in [35] is large and unsuitable for optical integrated circuits. It also has a relatively long stability time. Another structure presented in [36] can only be used as a NAND gate. It is also large in size and has a long stability time. The all-optical logic gates in [37] have a low power in the logic 1 state and a low CR.

Although the all-optical logic gates reported in [38] are small, the power in logic 1 is very weak, and the CR of the structure is very low. Also, its stability time is very long. In the gates of [39], the structure size is large, and the power in logic 1 is also very low. Its stability time is also long. The structure proposed in this study, in which the ML-FOLD algorithm has been used in its design, has a relatively small size and suitable powers in logic 0 and 1. The advantage of this structure over other structures is its very low stability time, which can be used in high-speed optical integrated circuits.

6. Conclusions

In this study, optical NAND and NOR gates were effectively designed and simulated within a unified two-dimensional photonic crystal framework by carefully tuning the input phase parameters. The use of the ML-FOLD optimization formula has proven to be highly efficient, requiring only a small set of simulation data points to identify optimal phase configurations, thereby circumventing the computational burdens associated with traditional optimization techniques. Our results confirm that the proposed structure accurately performs the logical operations for both gates, as evidenced by the normalized output powers aligning with the expected logical states. The disparity in the optimization metric ranges between the NOR and NAND gates suggests potential areas for further investigation, such as refining the formula’s sensitivity or exploring additional structural parameters. Nonetheless, the precise alignment of the ML-FOLD-identified optimal phases with those reported in this study underscores the method’s practical applicability. This research contributes to the advancement of all-optical logic devices, paving the way for faster and more efficient computing systems. Future work may focus on experimental validation of the simulated designs and extending the approach to more complex logic circuits.