Novel Quasi-Z-Source Inverter with High-Frequency AC Link of High-Proportion Renewable-Energy Power System

Abstract

Z-source/quasi-z-source inverters can make up for some limitations of traditional voltage-/current-source inverters. In recent years, more and more research has been carried on z-source/quasi-z-source inverters, but most of them are unable to realize input/output galvanic isolation. The proposal of high-frequency isolated z-source/quasi-z-source inverters greatly enriches the topological family of this type of converter but places relatively high voltage stress on the capacitors. In this paper, a novel circuit topology of a quasi-z-source inverter with a high-frequency AC link of a new high-proportion power system is proposed. The operating principle and abnormal operating states, such as discontinuous-conduction mode (DCM) operation and abnormal states caused by component failures, are analyzed. The double closed-loop control strategy is analyzed and designed, and a grid-connected photovoltaic system based on the inverter is designed. The experimental results verify that the presented inverter has advantages such as high-frequency electrical isolation, bi-directional power flow, lower voltage stress on the capacitors, etc.

1. Introduction

Traditional voltage-/current-source inverters are widely used in many applications, such as motor speed control, DC transmission, new energy generation, power quality control, and microgrids [1,2,3,4]. Many control methods for the inverters, including generalized droop control, have been presented [5,6,7,8]. The above inverters have concise circuit topology, a single power stage, and high efficiency, but they have some limitations because of their circuit structures [9,10,11,12]. For example, the DC-DC converters are necessary in the front stage to extend the scope of the output, which increases loss and reduces efficiency [13,14,15,16,17]. On the other hand, the two power switches on the same bridge-arm of the inverter are easy to run straight through [18,19,20,21,22]. A kind of z-source inverter has been put forward, as shown in Figure 1a, which can well make up for the shortcomings of voltage-/current-source inverters [23]. The advantages, limitations, and disadvantages of z-source inverters have been analyzed [24].

Due to their many advantages, a large number of scholars have conducted in-depth research on z-source inverters. A derived structure of a z-source inverter has been proposed, i.e., a quasi-z-source inverter, whose voltage-source topology is shown in Figure 1b [25]. Compared with z-source inverters, this inverter has more advantages, such as the input and output sharing the same ground, lower voltage stress on passive devices, power switches, and a simpler control circuit, but it does not have electrical isolation.

More and more research has since been carried out on quasi-z-source inverters, and most research has focused on how to reduce straight-through duty cycles under the same boost factor [26,27]. By changing the position of the voltage source, the capacitor, and the inductor, the embedded z-source inverter has minimum voltage stress on the capacitor as well as the continuous input current [28]. A z-type impedance network was added, and the cascaded quasi-z-source inverter was proposed to reduce the voltage stress on the devices [29]. The switched inductor quasi-z-source inverter was improved by replacing one inductor with a switched inductor, which further reduces the straight-through duty cycle. The T-type quasi-z-source inverter, whose two inductors are replaced by a coupling transformer, achieves the minimum straight-through duty cycle [26]. In order to increase the capacity, the external cascaded quasi-z-source inverter based on the T-type inverter was proposed [30].

The above inverters have a single power stage but no electrical isolation. As shown in Figure 1c, a circuit topological family of high-frequency isolated z-source/quasi-z-source inverters was proposed, and a brief analysis and simulation was made [31], but they have uni-directional power flow.

In the second section of this paper, a novel circuit topology of a quasi-z-source inverter with a high-frequency ac link is proposed. In the third section, the operating principle and abnormal-operating-condition work situations are analyzed. In the fourth section, a control strategy is designed and analyzed. Finally, in the fifth section, the inverter system is designed and experimentally verified.

2. Circuit Topology

High-Frequency Isolated Quasi-Z-Source Inverter Design

As the above high-frequency transformer-isolated quasi-z-source inverter has high voltage stress on the capacitors, a novel circuit topology is proposed in this paper, as shown in Figure 2a. Considering the high-frequency transformer, a multi-winding output is adopted to achieve voltage equalization of the capacitor C_3s and C_4s easily, and the desired output voltage can be obtained through an output series. This circuit topology can reduce the voltage stress on the capacitor to about half of the previous stress levels, so the size and weight of the capacitor decreases greatly.

In order to avoid the non-normal operating state operation such as discontinuous conduction mode (DCM) operation and abnormal states caused by component failures of the inverter, the proposed circuit topology is improved by replacing the input freewheel diode D with a power switch S₅, whose control signal is opposite to that of S. The presented improved circuit topology is shown in Figure 2b. Compared with the existing inverters, the proposed one in this paper has not only high-frequency electrical isolation, bi-directional power flow, high power density, and little buck and weight, but also low voltage stress of the capacitors.

3. Modeling Analysis

3.1. Operation Principle

The operation modes of this inverter can be classified into continuous conduction mode (CCM) and discrete conduction mode (DCM). For this inverter, DCM operation must be avoided. There are two operating states in CCM, i.e., straight-through zero-vector and non-straight-through effective-vector, while DCM operation has a third discrete operating state. The equivalent models of operation mode are shown in Figure 3.

Figure 3a represents the equivalent circuit of the inverter operating in a straight-through zero-vector state. The primary-side power switch S is on, S₅ is off, and at least one bridge-arm on the secondary side is straight-through. During this operation, the primary-side capacitor discharges and the inductor charges, and the secondary side is inverse. The energy is stored in the primary-side inductor. Meanwhile, the load current is freewheeling. This state is unique to z-source/quasi-z-source inverters and is equivalent to the energy storage of the boost converter.

Figure 3b denotes the equivalent circuit operating in a non-straight-through effective-vector state. S is off, S₅ is on, and the output of the inverter is equivalent to a constant-current source. The primary-side capacitor charges and the inductor discharges, and the secondary side operates oppositely. The energy of the primary-side inductor is released to the load, and the load side is in the inversion state.

The equivalent circuit of the abnormal state is shown in Figure 3c. This state may occur in non-straight-through operation, which is caused because of a small input inductor or light load. S₅ is equivalent to off and the input current is zero.

To simplify the steady-state analysis, it is assumed that all capacitance and inductance are, respectively, C and L, and C is large enough. Then from the relationship of the voltages and the currents in Figure 3a,b, the following equations can be obtained:

$$<V_{L1P}{>}_{Ts}=(V_S+V_{C2P})D_O+(V_S-{V_{C1P}}^{\prime })(1-D_O)=0$$

(1)

$$<V_{L2P}{>}_{Ts}=V_{C1P}{D}_O+(-{V_{C2P}}^{\prime })(1-D_O)=0$$

(2)

$$<V_{L3S}+V_{L4S}{>}_{Ts}=(V_{C3S}+V_{C4S})D_O+({V_{C3S}}^{\prime }+{V_{C4S}}^{\prime }-{V_{DC}}^{\prime })(1-D_O)=0$$

(3)

where T_S is one operating cycle time, and D_O and 1 − D_O are, respectively, the through and non-through duty cycle. Equation (4) is also obtained.

$${V_{DC}}^{\prime }={V_{C3S}}^{\prime }+{V_{C4S}}^{\prime }-{V_{L3S}}^{\prime }+{V_{L4S}}^{\prime }={V_{C3S}}^{\prime }+{V_{C4S}}^{\prime }+2N{V_{C2P}}^{\prime }$$

(4)

Solving Equations (1)–(4) yields:

$$V_{C1P}={\displaystyle \frac{(1-D_O)V_S}{1-2D_O}}$$

(5)

$$V_{C2P}={\displaystyle \frac{D_O{V}_S}{1-2D_O}}$$

(6)

$$V_{C3S}+V_{C4S}={\displaystyle \frac{2N(1-D_O)V_S}{1-2D_O}}$$

(7)

$${V_{DC}}^{\prime }={\displaystyle \frac{2N{V}_S}{1-2D_O}}$$

(8)

The same turns ratio of the transformer ensures the equal voltage of the vice-side capacitors. The secondary-side capacitor voltage is clamped by the output voltage of the transformer, so low voltage stress of the capacitors is obtained, which is shown in Equation (9).

$$V_{C3S}=V_{C4S}={\displaystyle \frac{N(1-D_O)V_S}{1-2D_O}}$$

(9)

Based on the output voltage relationship of the single-phase inverter, the peak output AC voltage can be derived.

$${\widehat{v}}_O=M{V}_{DC}={\displaystyle \frac{2MN{V}_S}{1-2D_O}}=M\times N\times B\times V_S$$

(10)

where V_DC = V_DC′ is the peak voltage of DC bus, M is the modulation degree of the inverter, N is the turn ratio of the transformer, and B is the boost factor.

Then assuming that the inductance L is large enough, the following equations can be obtained from Figure 3a,b.

$$<I_{C1P}{>}_{Ts}=I_{LP}{D}_O-{I_S}^{\prime }(1-D_O)=0$$

(11)

$$<I_{C2P}{>}_{Ts}=I_S{D}_O-{I_{LP}}^{\prime }(1-D_O)=0$$

(12)

$$<I_{C3S}{>}_{Ts}=I_{LS}{D}_O-{I_{DC}}^{\prime }(1-D_O)=0$$

(13)

The current of the inductor can not change abruptly, so there is

$$I_S={I_S}^{\prime }$$

(14)

According to the flux balance of the transformer, Equation (15) is obtained.

$$I_{LP}-2N{I}_{LS}={I_{LP}}^{\prime }+2N{I_{DC}}^{\prime }$$

(15)

Based on the principle of power conservation, Equation (16) is achieved as

$${I_{DC}}^{\prime }={\displaystyle \frac{P_O}{{V_{DC}}^{\prime }}}={\displaystyle \frac{P_O(1-2D_O)}{2N{V}_S}}$$

(16)

In Equation (16), P_O is the average output power. From Equations (11)–(16), the following equation is described as

$$I_S={\displaystyle \frac{P_O(1-D_O)}{V_S}}$$

(17)

$$I_{LP}={\displaystyle \frac{P_O{(1-D_O)}^2}{D_O{V}_S}}$$

(18)

$${I_{LP}}^{\prime }={\displaystyle \frac{P_O{D}_O}{V_S}}$$

(19)

$$I_{LS}={\displaystyle \frac{P_O(1-D_O)(1-2D_O)}{2D_{O}N{V}_S}}$$

(20)

Other voltage and current parameters of the inverter can also be obtained as shown in Equations (21)–(24).

$$V_D=V_{C1P}+V_{C2P}={\displaystyle \frac{V_S}{1-2D_O}}$$

(21)

$$I_D={I_S}^{\prime }+{I_{LP}}^{\prime }={\displaystyle \frac{P_O}{V_S}}$$

(22)

$$V_P=V_{C1P}+V_{C2P}={\displaystyle \frac{V_S}{1-2D_O}}$$

(23)

$$I_P=I_S+I_{LP}={\displaystyle \frac{P_O(1-D_O)}{D_O{V}_S}}$$

(24)

In summary, from Equation (10), it can be seen that the input and output voltage transfer gain is G = M × N × B = M × N × 2/(1 − 2D_O). Generally, for given N, the boost or buck output can be realized by controlling M and D_O.

3.2. Abnormal Operation Conditions

As shown in Figure 3c, the operating state of discrete input current is abnormal, which needs to be avoided. In this paper, the improved novel circuit topology shown in Figure 2b is proposed to prevent the DCM operation. Setting the straight-through operating state time as T_O, the non-straight-through CCM operating state time as T_A, and the non-straight-through DCM operating state time as T_D, so T_S = T_O + T_A + T_D, the corresponding duty cycle can be expressed as 1 = D_O + D_A + D_D.

Considering T_D, from Equations (1)–(3), Equations (25)–(27) can be obtained as:

$$<V_{L1P}{>}_{Ts}=(V_S+V_{C2P})D_O+(V_S-{V_{C1P}}^{\prime })D_A+D_D\times 0=0$$

(25)

$$<V_{L2P}{>}_{Ts}=V_{C1P}{D}_O+(-{V_{C2P}}^{\prime })D_A+D_D\times 0=0$$

(26)

$$<V_{L3S}+V_{L4S}{>}_{Ts}=(V_{C3S}+V_{C4S})D_O+({V_{C3S}}^{\prime }+{V_{C4S}}^{\prime }-{V_{DC}}^{\prime })D_A+D_D\times 0=0$$

(27)

So the average value of DC bus voltage in DCM can be achieved.

$${\overline{V}}_{DC}=V_{C3S}+V_{C4S}={\displaystyle \frac{2N{D}_A{V}_S}{D_A-D_O}}$$

(28)

$$V_{C2P}={\displaystyle \frac{D_O{V}_S}{1-2D_O-D_D}}$$

(29)

According to the relationship of the inductor voltage and current, the average value of the input current can be calculated as

$${\overline{I}}_S=N{\overline{I}}_{DC}+{\displaystyle \frac{T_O+T_A}{T_S}}({\displaystyle \frac{T_O{V}_{L1P}}{2L_{1P}}})=N{\overline{I}}_{DC}+(D_O+D_A)[{\displaystyle \frac{D_O(V_S+V_{C2P})}{2L_{1P}f}}]$$

(30)

where ${\overline{I}}_{DC}$ is the equivalent average output current. Equation (31) can be obtained from Equations (28)–(30).

$${\overline{I}}_S=N{\overline{I}}_{DC}+{\displaystyle \frac{{\overline{V}}_{DC}{D_O}^2}{2L_{1P}Nf}}({\displaystyle \frac{2{\overline{V}}_{DC}-2N{V}_S}{{\overline{V}}_{DC}-2N{V}_S}})$$

(31)

Losses neglected, based on the principle of conservation energy, there is

$$V_S{\overline{I}}_S={\overline{V}}_{DC}{\overline{I}}_{DC}$$

(32)

From Equations (31) and (32), the average input–output voltage gain in DCM is given as:

$$G_{DCM}(\beta )={\displaystyle \frac{{\overline{V}}_{DC}}{V_S}}={\displaystyle \frac{2N\beta }{\beta -{D_O}^2}}$$

(33)

where $\beta ={\overline{I}}_{DC}N{L}_{1P}f/V_S$. In addition, the average input–output voltage gain of the inverter in CCM is:

$$G_{CCM}(\beta )={\displaystyle \frac{{\overline{V}}_{DC}}{V_S}}={\displaystyle \frac{2N(1-D_O)}{1-2D_O}}$$

(34)

Based on the average input–output voltage gains in both DCM and CCM, the operating parameter range of the inverter can be derived, as shown in Figure 4. The critical points are shown as the dash curve, which indicates the input–output voltage gains varying with the parameter β. CCM operation should be ensured, so β must be satisfied as:

$$\beta \ge 0.25$$

(35)

and the input inductor L_1P should be satisfied as:

$$L_{1P}\ge {\displaystyle \frac{V_S}{4N{\overline{I}}_{DC}f}}={\displaystyle \frac{{\overline{V}}_{DC}}{4N{\overline{I}}_{S}f}}={\displaystyle \frac{V_{DC}(1-D_O)}{4N{\overline{I}}_{S}f}}$$

(36)

where f is the operating frequency of the inverter.

4. Control Strategy

According to the input–output characteristics, the novel inverter is suitable for different types of input sources and a wide range of input voltages. In this paper, a grid-connected photovoltaic system is designed based on the inverter. The control block diagram of the system is given in Figure 5.

In this paper, an accurate control strategy of constant DC bus peak voltage is adopted, and the inner loop of grid-connected current is added to improve the dynamic response. The outer loop of DC bus voltage uses a PI controller for closed-loop compensation, which can effectively eliminate the DC static error. A PR controller is adopted in the inner loop as compensation to remove the AC static error.

In Figure 5, the voltage and the current signals are input to the digital signal processor (DSP) after A/D sampling and added double closed-loop algorithm is integrated in the DSP to realize digital control. The outer voltage loop ensures the stability of the peak voltage of the DC bus. The output of the outer loop is used as the amplitude reference of the inner current loop, and multiplied by the sinusoidal signal with the same frequency and phase as the grid voltage, so the sinusoidal reference is obtained for the inner loop. The inner current loop is adopted to realize unit power factor operation. The dual closed-loop output is a sinusoidal modulation signal, which is intersected with a triangular carrier to obtain the corresponding sinusoidal pulse width modulation (SPWM) control signal. Meanwhile, the straight-through pulse width modulation (PWM) signal is directly derived from the intersection of the given D_O and the same triangular carrier, then synthesized with the SPWM signal to achieve the final control signals.

5. System Design and Experimental Verification

The structure block diagram of the grid-connected photovoltaic system designed is shown in Figure 6, the including quasi-z-source network, high-frequency isolation transformer, inverter bridge, output filter, generating circuit of square-wave signal synchronized with the grid voltage, sampling circuit of DC voltage, sampling circuit of grid-connected current, driving circuit, and DSP and peripheral circuit.

Main parameters of the system are shown in

Table 1. Main parameters of the grid-connected photovoltaic system.

Variants	Parameters
Rated power	500 VA
Input DC voltage VS	120~180 V
Duty cycle Do	0.083~0.223
Grid voltage E	220 V
Grid current Iac	2.273 A
Capacitors C1P, C3S, C4S	1200 μF/250 V
Capacitors C2P	1200 μF/50 V
Parasitic resistor of capacitor R	0.1 Ω
Input energy storage inductor L1P	1.2 mH
Output filter inductor Lac	5 mH
Parasitic resistor of inductor r	0.1 Ω
Turn ratio of transformer N	1
Switching frequency f	20 kHz
Control chip	TMS320F2808
Phase-locked loop module	CD4046

. As shown in Figure 7, the experimental platform includes the solar panel, the experimental prototype, the control panel, and the grid. The solar panel is simulated by a DC voltage source in series with a resistor, and the grid is replaced by an AC power source with a resistive load connected to limit the current.

The selection of these parameters is based on the requirements of system design, the specifications of the inverter, and the purpose of experimental verification. The selection of parameters aims to ensure that the simulated input of the solar panel matches the input requirements of the inverter, while the output voltage and current can meet the grid connection requirements. For example, the setting of input voltage vs. at 176.6 V and through duty cycle D_O at 0.085 is to simulate the output of a solar panel under specific lighting conditions and ensure that the inverter can operate stably under these conditions. In addition, the output voltage is designed as an AC sine voltage synchronized with the grid voltage, with an effective value (RMS) of 220 V, to ensure that the output of the inverter can be smoothly integrated into the grid. The selection of these parameters comprehensively considers the performance, efficiency, and compatibility with the power grid of the inverter.

Measurement technology includes the use of high-precision digital signal processors (DSPs) to implement a dual closed-loop control strategy, where the outer loop controls the peak voltage of the DC bus and the inner loop controls the grid-connected current to improve the dynamic response. The voltage and current signals are sampled through analog-to-digital conversion (A/D) and input into the DSP, where specific algorithms are used for digital control. In addition, sine pulse width modulation (SPWM) technology was used to generate control signals in the experiment, and a phase- locked loop (PLL) module CD4046 was used to ensure that the inverter output is synchronized with the grid voltage. The selection of these measurement techniques is based on their accuracy, resolution, and ability to synchronize with the grid voltage, aiming to accurately capture the performance parameters of the inverter, thereby allowing other researchers to reproduce experimental results under the same conditions.

In the experimental platform, the configuration of the solar panel is simulated by connecting a DC voltage source in series with a resistor, where the average input voltage vs. is 176.6 V and the through duty cycle D_O is 0.085. This configuration aims to simulate the output characteristics of the solar panel under specific lighting conditions and match the input requirements of the inverter. The power grid is replaced by an AC power source with a current-limiting resistor load to simulate actual grid conditions.

The grid conditions are simulated through an AC power source and a current-limiting resistor load to ensure that the current does not exceed the safe operating range of the experimental equipment. This simulated power grid design is used to test the performance of the inverter when connected to the actual power grid, including the peak output AC voltage it can provide. This voltage is calculated based on the output voltage relationship of a single-phase inverter and is related to the modulation index M of the inverter, the turns ratio N of the transformer, the boost factor B, and the peak voltage VDC of the DC bus. The component parameters used in the experiment are given in Table 1 of the document, including the specifications of key components such as the quasi-Z-source network, high-frequency isolation transformer, inverter bridge, output filter, etc. These parameters are crucial for system design and experimental verification.

The effectiveness of circuit topology, working principle, control strategy, and system design verification results of the designed quasi-z-source inverters with a high-frequency ac link of high proportion renewable energy power system are shown from Figure 8, Figure 9, Figure 10, Figure 11 and Figure 12.

The waveforms of the input and output voltages are given in Figure 8. The average value of the input voltage vs. is 176.6 V, and the corresponding pass-through duty cycle D_O is 0.085. The output voltage of the inverter is clamped to the grid voltage as an AC sinusoidal voltage with an RMS value of 220 V. Compared with the existing inverters, the proposed inverter can not only convert voltage types (from DC to AC) but also adjust the voltage to a certain RMS value of 220 V to match the requirements of the power grid, which is crucial for ensuring the stable and efficient operation of the power system.

As shown in Figure 9a–c, the control signals of S₁, S and S₅ are SPWM waveforms. DC bus voltage is given in Figure 9d, whose peak value is approximately 430 V.

Compared with the existing inverters, the inverters proposed has higher peak DC bus voltage. A higher peak value of the DC bus voltage typically indicates several potential advantages and characteristics:

High power handling capability: A higher peak value of the DC bus voltage suggests that the inverter can handle higher power levels. This is because power is directly proportional to voltage and current and, with a constant current, a higher voltage can transmit more power.

Energy storage capability: In some designs, a higher peak value of the DC bus voltage may imply greater energy storage capacity. This is because capacitors or other energy storage components can store more energy at higher voltages.

System flexibility: A higher peak value of the DC bus voltage can offer greater design flexibility, allowing the inverter to operate more efficiently under different load and input voltage conditions. This is especially important for applications that require adaptation to varying input voltages or need to operate in different modes.

Output voltage Regulation Range: In inverters, a higher peak value of the DC bus voltage can provide a wider range of output voltage regulation. This is particularly useful for equipment or systems that need to operate at different voltage levels.

Improved efficiency: In some cases, a higher DC bus voltage peak can reduce energy losses during conversion, thereby increasing overall efficiency. This is because, for the same power output, a higher voltage can reduce current, thereby reducing losses due to current flow (for example, losses due to wire resistance).

Adaptability: For grid-tied inverters, a higher peak value of the DC bus voltage can better accommodate fluctuations in grid voltage, providing a more stable output.

As shown in Figure 10, the voltages of each capacitor are, respectively, V_C1P = 180.2 V, V_C2P = 18 V, V_C3S = 187 V, and V_C4S = 185.5 V, which are all approximately equal to their theoretical values and relatively less than that of the existing inverters. The voltage of capacitor C_2P fluctuates more but has no damage to the circuit because of its low voltage level.

Compared with the existing inverters, the inverters proposed have lower capacitor voltage level, which brings lower voltage stress of the capacitors, offering the following advantages:

Simplified design and reduced cost: If the voltage stress on capacitors is lower, engineers may not need to employ complex voltage balancing or equalization techniques, which can simplify circuit design. Capacitors with lower voltage stress are generally less expensive as they can be manufactured using more common materials and simpler designs.

Enhanced reliability: Capacitors are among the more failure-prone components in an inverter. Reducing the voltage stress on capacitors can extend their service life, thereby increasing the reliability of the entire system.

Decreased size and weight: With lower voltage stress, smaller and lower capacitance capacitors can be used, which helps to reduce the size and weight of the inverter, making it more suitable for portable or space-limited applications.

Improved efficiency: Lower voltage stress on capacitors can reduce power losses, thereby improving the efficiency of the inverter, especially noticeable in high-frequency applications.

Lower thermal management requirements: Capacitors with lower voltage stress generate less heat, which means that the cooling system of the inverter can be simpler, further reducing system complexity and cost.

Increased safety: Lower voltage stress on capacitors reduces the risk of capacitor rupture or explosion, thereby enhancing the safety of the inverter.

Reduced maintenance Needs: Capacitors, being a consumable part of the inverter, can cause the entire system to fail if they fail. By using capacitors with lower voltage stress, the frequency of maintenance and replacement can be reduced, lowering maintenance costs.

Figure 11 gives the drain-source voltages of the power switches and the output voltage of the inverter bridge. It shows that the voltages of each power switch are similar to the theoretical values and the primary voltages are stable without large spike. The output voltage of the inverter bridge shown in Figure 11d, which is across the output filter, is a unipolar SPWM voltage.

From Figure 11, it can be seen that the inverter proposed demonstrates capabilities in accurate voltage regulation, stable operation, efficient power switching, and effective filtering, all of which contribute to its high performance and reliability in power conversion applications.

The grid-voltage and grid-connected current as well as the phase-locked loop waveforms are given in Figure 12. The orange and blue waveforms shown in Figure 12a are respectively grid voltage and grid-connected current. It can be seen that they have the same frequency and phase. In Figure 12b, the orange and blue waveforms belong to the sampled grid-voltage and the output of the phase-locked loop module CD4046. The later has the same frequency and phase with the former, and is input to the DSP chip.

In summary, the synchronization capabilities demonstrated in Figure 12 indicate that the inverter has a high level of control precision, dynamic response, and reliability, which are essential for stable and efficient operation in grid-tied applications.

According the effectiveness of circuit topology, working principle, control strategy, and system design verification results of the proposed quasi-z-source inverters shown from Figure 8, Figure 9, Figure 10, Figure 11 and Figure 12, the comparison of performance between the existing inverters described in the literature and the inverter proposed are shown in the

Table 2. Comparison of performance between the existing inverters and the inverter proposed.

Performance Parameter	The Inverter in the Figure 1.1(a) [23]	The Inverter in the Figure 1.1(b) [25]	The Inverter in the Figure 1.1(c) [32]	The Inverter Proposed
The output voltage (V)	210.00	212.77	208.00	220.00
The peak value of the DC bus voltage (V)	375.00	382.00	415.00	430.00
The voltage of the capacitors	VC1P = 205.00 V, VC2P = 215.00 V	VC1P = 194.68 V, VC2P = 18.10 V	VC1P = 192.17 V, VC2P = 192.17 V, VC1S = 194.68 V, VC2S = 194.68 V	VC1P = 180.20 V, VC2P = 18.00 V, VC3S = 187.00 V, VC4S = 185.50 V
The voltage stress of the capacitors	High	Low	Medium	Low
Weight	Heavy	Light	Light	Light
Electrical isolation	No	Yes	High-frequency	High-frequency
Power flow	Uni-directional	Uni-directional	Uni-directional	Bi-directional
Power density	Low	Medium	High	High

. The performance parameter value of the existing inverters in the Table 2 are converted according to the formula in the literature and the input parameters with the input voltage 176.6 V, the corresponding pass-through duty cycle D_O of 0.085, and the value in Table 1.

From the Table 2, following conclusions can be obtained through the experiment, when the input DC voltage vs. and the two control variables D_O and M are given, the voltages of each branch of the inverter as well as the output voltage agree well with the theoretical analysis, which fully verifies the proposed circuit topology, operation principle, control strategy and system design.

6. Conclusions

Traditional voltage/current-source inverters are widely used in many fields, which have concise circuit topology, single power stage and high efficiency, but they have some limitations because of the circuit structures. Z-source/quasi-z-source inverters can make up for the limitations of the voltage/current-source inverters, but most of them are unable to realize the input/output galvanic isolation. The proposal of high-frequency isolated z-source/quasi-z-source inverters greatly enriches the topological family of this type of converter, but has relatively high voltage stress of the capacitors.

In this paper, a novel circuit topology of quasi-z-source inverter with a high-frequency ac link of high proportion new power system is proposed. The operation principle and non-normal operating state operation such as discontinuous conduction mode (DCM) operation and abnormal states caused by component failures are analyzed. The relatively complex double closed-loop control strategy is analyzed and designed, and the grid-connected photovoltaic system based on the inverter is developed and experimentally verified. Compared with the existing inverters, the experimental results verify that the presented inverter has not only high-frequency electrical isolation, bi-directional power flow, high power density and little buck and weight, but low voltage stress of the capacitors.

This paper serves as an in-depth study of the new topology of high-frequency isolated type z-source/quasi-z-source inverter.