Next Article in Journal
Numerical Simulation Approach for a Dynamically Operated Sorption-Enhanced Water-Gas Shift Reactor
Previous Article in Journal
Accurate Estimation of Tensile Strength of 3D Printed Parts Using Machine Learning Algorithms
Previous Article in Special Issue
The Design and Magnetic Field Analysis of a Double Rotor Permanent Magnet Braking Device
 
 
Font Type:
Arial Georgia Verdana
Font Size:
Aa Aa Aa
Line Spacing:
Column Width:
Background:
Article

Optimization of a Multilevel Inverter Design Used for Photovoltaic Systems under Variable Switching Controllers

Department of Electrical Engineering, College of Engineering, University of Ha’il, Ha’il 2240, Saudi Arabia
*
Author to whom correspondence should be addressed.
Processes 2022, 10(6), 1159; https://doi.org/10.3390/pr10061159
Submission received: 7 May 2022 / Revised: 6 June 2022 / Accepted: 7 June 2022 / Published: 9 June 2022

Abstract

:
Among multilevel inverters (MLIs), two-level inverters are the most common. However, this inverter type cannot maintain total harmonic distortion (THD) due to its limited number of levels. Reductions in THD are inversely proportional to the number of levels where increased output occurs in diverse ways, and the use of fewer components with low harmonic distortion is necessary for such reductions. This work proposes a seven-level (7L) MLI design with a small number of components and low harmonic distortion. The proposed MLI is combined with switched capacitor (SC) cells to promote output levels and at the same time to boost the input voltage. The connections between the capacitor and the source are based on the series to parallel topology, where the charging and discharging of the SC cells are caused by fluctuations in their connection. The output of the SC cell is combined with an H-bridge inverter controlled by a proposed PWM controller. The simulation result of the SC 7L inverter was completed using LTspice software. A comparison of the proposed topology with that of other current MLI led to better validation results. The proposed design shows a reduction in the THD with fewer components. The cost and size of the proposed inverter is minimal due to the smaller number of components. Ohmic load and inductive ohmic load were used as loads for the system.

1. Introduction

Researchers have been working to develop renewable energy systems as one of the solutions to global environmental problems. Nevertheless, renewable energy sources produce a low level of energy, which limits their usage and applications. A step up in the production of renewable energy encourages expanding their applications, especially in the smart grid field. Typically, step-up converters or inverters can increase the power produced. The energy conversion is either direct current (DC) to DC, as that in converters, or alternating current (AC) to DC, as that in inverters. This conversion task needs heavy magnetic elements such as transformers and inductors to achieve the high-voltage output. However, using magnetic elements negatively affects the overall efficiency [1,2,3,4]. To maintain the overall efficiency in diverse ways encourages the reduction of the size of the magnetic elements or their complete elimination. For instance, DC–DC switched-capacitor (SC) converters can built without magnetic elements, as in [1,2]. In addition to DC–DC SC converters, a non-isolated converter is recommended, which can achieve a higher output gain with higher power density [3,4,5,6]. Combining a DC–DC SC converter with a non-isolated converter also improves the output gain [7,8].
SC converters offer a higher voltage level in a very efficient manner. The SC cells work to pump the electric charge to a prominent level, and as a result, the input voltage is increased. This step-up technique is based on charging and discharging, where a parallel connection helps to charge the capacitors and a series connection leads to discharging it. Dependency between the voltage level and the number of capacitors causes some complexity issues. However, merging SC cells with an inverter produces a DC–AC converter design that can be designated as an SC multilevel inverter (MLI). Achieving a higher AC voltage waveform without any use of a power transformer may be considered the main advantage of the MLI. Additionally, the multilevel SC inverter requires fewer switches and gate drivers.
Several types of MLIs have been proposed, with the first being implemented in 1998 by O.C. Mak and A. Ioinovici. MLI research then focused mostly on managing total harmonic distortion (THD), improving inverter efficiency, and increasing power density. One way to improve MLIs is to use a soft switching technique, which helps to maintain the overall efficiency. Since most of the proposed MLI designs include multiple switching elements, the resonant technique helps to reduce switching loss, which enhances inverter efficiency [9,10,11,12].
Specifically, for high-power applications, MLIs have been used in academic and industrial research for the last two decades. MLIs are attractive for these fields because of their ability to supply high-output voltages and to maintain the harmonic distortion of output waveforms. There are hundreds of inverter designs that can be utilized for DC–AC conversions over medium and high voltages [13,14,15,16]. There are three main types of MLIs: diode-clamped or necked (neutral-point clamped), capacitor-clamped (flying capacitor), and cascaded multilevel. The diode-clamped inverter is the most popular type; the diodes in this design help to compress the DC voltage, which results in increases in output voltage. Furthermore, diodes are regarded as having the advantage of limiting voltage stress. This type of circuit is constructed with a voltage source, (n − 1) diodes, and (n − 1) or 2(n − 2) diodes. Inversely proportional to the number of levels, a reduction in THD helps to achieve sinusoidal waveform output voltage.
An alternative to using diodes is to use clamped capacitors in place of the diodes, and this topological arrangement is the second-best known MLI [17,18,19,20,21]. Adding capacitors to the MLI design allows for a charging and discharging process, which boosts the input voltage to a higher level. Series and parallel connections of capacitors alter the voltage into the flying capacitors. There are many topologies of SC cells, some of which boost the input voltage, such as the ladder topology. Known as cascading MLIs, the third type of MLI combines two or more H-bridge inverters in a series to produce sinusoidal voltage. The more cascaded inverters, the more output voltage is achieved with higher inverter levels [6,9,22,23]. Compared to the earlier two types, the cascaded MLI has the significant advantage of requiring fewer components. Some recent work has merged two or more of the earlier MLI types, using both clamped diodes and capacitors in combination to support the THD. Where this combination was used in several proposed models, it is known as the hybrid MLI because it is a cascaded operation with SC cells. In these articles, different topologies for SC cells were all focused on supporting the THD with smaller numbers of components.
Our goal in this article is to present an MLI topology to achieve high-output voltages with fewer components. The insertion of the SC cell into the H-bridge inverter helps to increase output voltage and inverter levels. Instead of using double input sources as in [24,25], the capacitor cell in this work behaves as an additional input source. Increasing the inverter level leads to a reduction in the THD, which is desirable for achieving a sinusoidal output. However, this achievement must be completed with a limited number of elements; thus, a new controlling state for the H-bridge switches was completed. Similar to other MLI topologies, the proposed inverter is useful for grid-connected photovoltaic (PV) systems [26,27,28,29,30,31]. Figure 1 presents a simple PV system in which the inverter is essential to transfer the DC voltage to AC voltage and make it more suitable for a grid utilities application [32]. LTspice software was used to validate the proposed work. Seven levels of the proposed inverter were compared with similar designs, which successfully proved the merit of this project.

2. Proposed Topology

Figure 2 shows how the proposed MLI module circuit is configured. The system consists of seven unidirectional switches which are either an insulated-gate bipolar transistor (IGBT) or a metal-oxide-semiconductor field-effect transistor (MOSFET), one DC source and one SC cell. The DC source and SC cell are connected serially and in parallel, whereas at the series connection, the SC cell acts as an additional DC source. With this configuration, a seven-level (7L) configuration can be generated, which includes three positive levels, three negative levels, and one zero. Table 1 depicts the switching states of all switches.
Compared to current MLIs, the proposed model needs fewer elements per level. For instance, the 7L of the proposed model requires seven switches where five of them are (ON) at a time for each level. Due to the conduction and switching losses supported by having lower (ON) switches, the proposed MLI successfully supplies improved efficiency.

3. The Series to Parallel SC Cell

To add an SC cell to the proposed model, one capacitor and three switches are required where the capacitor cell, C, acts as additional voltage source (Figure 3a). The duty cycle is 50% for each series, with parallel connection and series-mode S6 conducting. However, S5 and S7 are not. Series mode C is connected in series while it is in parallel mode. The total charge in series mode or the first mode ( Q T 1 ) equals the total charge of the parallel mode or the second mode ( Q T 1 ) [33,34,35,36,37,38,39,40] as in (1):
Q T 1 = Q T 2
In parallel mode (Figure 3b), the voltage across the capacitor (VC) equals the input voltage (Vin), as in (2):
  V C = V i n
To satisfy (1) it is necessary to apply (2):
Q T 1 = C V C
by sub (2) into (3) to obtain (4):
Q T 1 = V i n C  
In series mode (Figure 3c), the output voltage of the SC cell ( V c e l l _ o u t ) is the input voltage added to the voltage across the capacitor (5):
V C = V c e l l _ o u t V i n
The total charge of this mode is presented in (6):
Q T 2 = C ( V c e l l _ o u t V i n )
  Q T 2 = C V o u t C V i n
Returning to (1) and by equalizing 4 and 7, then we obtain:
V o u t = 2 V i n

4. Control System

This proposed MLI uses different modulation techniques, and the one producing less THD was chosen. This 7L MLI topology was modulated with an alternate phase opposition technique. An analogy comparator compared the sine wave with the multicarrier wave before it is driven by a NOT gate. By using the NOT gate, the multicarrier wave is reversed. Using a comparator and a NOT gate, gate pulses are generated to drive the IGBT in the proposed MLI. According to the proposed MLI, relative signals are made up of a sine wave and six triangular multicarrier with phases which are offset by the intervals between the two carrier signals as in Figure 4 [41].

5. Proposed MLI Configuration

The topology of the proposed inverter is shown in Figure 2. Seven unidirectional switches and one SC make up the topology. Seven voltage levels can be achieved with this inverter topology. When connected in parallel, SC cell C is balanced at a voltage level equal to Vin input voltage. Simultaneously, the input DC source Vin charges the SC cell C. After the SC is charged, it is connected in series to the input voltages and functions as an extra source of power. As presented in Figure 5, S5, S6, and S7 are responsible for carrying out the parallel and series connections between the Vin and the capacitor cell. If the S6 is (ON), Vin is in series to C, whereas if S5 and S7 are (ON), then a parallel connection develops between Vin and C. The series and the parallel connections either deliver the same input voltage to the output or double it. Table 1 illustrates the switch states required to create a 7L output voltage.

6. Modes of Operation

Section 5 presents the basic principle of generating different voltage levels across a load through different modes of operation. The SC-MLI′s proposed operation modes in positive and negative half-cycles are depicted in Figure 5, which presents seven modes of operation. The switching states of the proposed MLI can be viewed in Table 1. As shown in the previous table, ‘0’ refers to the (OFF) state of the switches, while ‘1’ corresponds to the (ON) state. The letter C in the table indicates that the SC C is being charged, and the letter D indicates that it is being discharged. The following paragraphs describe how the proposed SC-MLI generates different output levels.
±1Vin voltage level: As can be seen in Figure 5 (Mode 1 and Mode 5), switches S1, S2, S5, and S7 are all turned (ON) to produce 1V. Similarly, capacitor C is charged to Vin level by being paralleled with the DC input source. For a voltage level of −1Vin, the corresponding switches S3, S4, S5, and S7 are all (ON), as shown in Figure 5.
±1.75Vin voltage level: as can be seen in Figure 5 (Mode 2 and Mode 6), switches S1, S2, S5, and S7 are all turned (ON) to produce 1V. Similarly, capacitor C is charged to Vin level by being paralleled with the DC input source. For a voltage level of −1Vin, the corresponding switches S3, S4, S5, and S7 are all (ON), as shown in Figure 5.
According to Figure 5 (Mode 3), the S1, S2, and S6 are turned (ON) to produce voltage level 2Vin. On the other hand, voltage level −2Vin can be achieved by turning on S3, S4, and S6 (Figure 5, Mode 7). In these two levels, a series connection is needed between SC C and the input source, which makes C work as an additional voltage source.
The voltage level of +1.75Vin is like that of +2Vin, but an added switch S3 is turned (ON), which lowers the voltage level by a voltage drop. In comparison to the −2Vin level, switch S2 is activated to achieve −1.75Vin.
Remark 1.
  • Similar to the work suggested in [25], this work uses the series to parallel the configuration to achieve a 7L MLI with the least number of input sources and switches.
  • The work in [25] used three input sources to implement the 7L inverter; however, this work used only a single input source with an SC cell. 3.The single input source used in this work is connected to an H-bridge inverter through an SC cell operating in the series to parallel; thus, the SC cell behaves as an additional input source.
  • From a practical point of view, the switching states of the switches of the H-bridge can be obtained using the method suggested in [20].
  • Unlike to the conventional H-bridge switch controller, the method in [20] is based on allowing three switches in the H-bridge to be (ON) to increase the number of output levels, referring to Mode 2 and Mode 6 in Figure 5.

7. Results and Discussion

Simulations were carried out using LTspice software. A single-phase 7L inverter was developed for simulation purposes with different parameters. The proposed model was compared with other MLIs to validate this work [41,42,43,44]. The possibility of expanding the inverter levels was achieved by adding additional SC cells. The seven MOSFET switches were controlled by the pulse-width modulation (PWM) method, where the selected fundamental switching frequency is 50 Hz. For simulation purposes, we selected 48 V as the input voltage source, along with a resistive load of 150 Ω, an inductive resistive load of 150 Ω, and 100 mH for the proposed SC-MLI [45]. The obtained output verifies the seven-level output where using a resistive inductive load promotes the output current. Due to the SC cells in the proposed design, the input voltage to the full bridge inverter is presented in Figure 6. As can be seen in Figure 6, the input voltage fluctuated between 96 V and 48 V during the series to parallel. Voltage and current achieve maximum output peaks at 96 V and 1.9 A, respectively. The output voltage and current waveforms are presented in Figure 7a and Figure 7b, respectively. From the V input voltage value, the voltage is boosted twice (Figure 7). This shows the feasibility of the SC-MLI. Furthermore, the results with inductive load confirm that the SC-MLI can be operated bidirectionally. As a fundamental parameter used to validate the proposed design, studying the THD is desirable. The harmonic spectrum of the output voltage shows a THD of 4.65% in the absence of any filters, as seen in Figure 8. The Institute of Electrical and Electronics Engineers (IEEE) standards, namely IEEE519, confirm all obtained results. Through simulations, the seven levels with triple voltage gain and inductive load capability were confirmed. Based on a voltage ripple of less than 10%, the optimum value of capacitor C is approximately 1000 μF.
The shared contribution that has been added to MLI fields by our proposed design is increasing the design power density due to reducing the number of elements, referred to in Table 2 and Table 3. As compared to several MLIs, the proposed model needs fewer switches, which helps to reduce switching complexity and switch failures [39,40,41,42]. Using SC cells works to increase the number of inverter levels with fewer switches.

8. Conclusions

This paper successfully tested a novel MLI topology with fewer power components. Instead of adding more switches to build an MLI, SC cells were interleaved in the proposed design. The SC cells work in series to parallel configurations, where the cell is charged by the input voltage during parallel configuration and discharged during series configuration and where the fully charged capacitors behave as an added input source. The use of the SC in the proposed 7L inverter helps to increase the output voltage with reduction in the THD. Furthermore, the higher output level is produced by a smaller number of components, which lowers the cost of this MLI model. Based on this model, the output voltage and level of the proposed model could be increased by adding more SC cells. Low THD and lower cost are two important benefits of the proposed design for both ohmic load and inductive ohmic load.

Author Contributions

Conceptualization, A.A. (Ayoob Alateeq) and Y.A.; methodology, A.A. (Ayoob Alateeq); software, A.A. (Abdulaziz Alateeq); validation, Y.A. and A.A. (Abdulaziz Alateeq); formal analysis, A.A. (Abdulaziz Alateeq); investigation, A.A. (Abdulaziz Alateeq); resources, A.A. (Abdulaziz Alateeq); data curation, A.A. (Abdulaziz Alateeq); writing—original draft preparation, A.A. (Abdulaziz Alateeq); writing—review and editing, A.A. (Ayoob Alateeq); visualization, Y.A.; supervision, A.A. (Abdulaziz Alateeq); project administration, A.A. (Abdulaziz Alateeq); funding acquisition, A.A. (Abdulaziz Alateeq). All authors have read and agreed to the published version of the manuscript.

Funding

This research was funded by the Scientific Research Deanship at the University of Ha’il in Saudi Arabia through project number BA-2109.

Acknowledgments

We would like to thank this work sponsor the Scientific Research Deanship at the University of Ha’il in Saudi Arabia for funding this work through project number BA-2109.

Conflicts of Interest

The authors declare no conflict of interest.

References

  1. Alateeq, A.S.; Almalaq, Y.A.; Matin, M.A. Modeling and simulation of GaN step-up power switched capacitor converter. In Proceedings of the SPIE 10381, Wide Bandgap Power Devices and Applications II, San Diego, CA, USA, 6–10 August 2017. [Google Scholar]
  2. Alateeq, A.S.; Almalaq, Y.A.; Matin, M.A. A Performance of the Soft Charging Operation in Series of Step-Up Power Switched-Capacitor Converters. J. Low Power Electron. Appl. 2018, 8, 8. [Google Scholar] [CrossRef] [Green Version]
  3. Alateeq, A.S.; Almalaq, Y.A.; Matin, M.A. A switched-inductor model for a non-isolated multilevel boost converter. In Proceedings of the 2017 North American Power Symposium (NAPS), Morgantown, WV, USA, 17–19 September 2017; p. 15. [Google Scholar]
  4. Sagar, M.; Ranjana, B. A Novel Non-Isolated Switched Inductor Floating Output DC-DC Multilevel Boost Converter For Fuelcell Applications. In Proceedings of the 2014 IEEE Students’ Conference on Electrical, Electronics and Computer Science, Bhopal, India, 1–2 March 2014; p. 14254943. [Google Scholar]
  5. Du, Z.; Tolbert, L.M.; Chiasson, J.N.; Ozpineci, B. Reduced Switching-Frequency Active Harmonic Elimination for Multilevel Converters. IEEE Trans. Power Electron. 2008, 55, 1761–1770. [Google Scholar]
  6. Ebrahimi, J.; Babaei, E.; Gharehpetian, G.B. A new topology of cascaded multilevel converters with reduced number of components for high-voltage applications. IEEE Trans. Power Electron. 2011, 26, 3109–3118. [Google Scholar] [CrossRef]
  7. Alateeq, A.; Matin, M. A Novel Design of a High Gain Step-up Converter Using Switched-Capacitors/Switched-Inductors Cells. In Proceedings of the 2018 IEEE International Conference on Electro Information Technology (EIT), Rochester, MI, USA, 3–5 May 2018. (In the Press). [Google Scholar]
  8. Lai, J.S.; Peng, F.Z. Multilevel converters—A new breed of power converters. IEEE Trans. Ind. Applicat. 1996, 32, 509–517. [Google Scholar]
  9. Babaei, E.; Laali, S.; Bayat, Z. A single-phase cascaded multilevel inverter based on a new basic unit with reduced number of power switches. IEEE Trans. Ind. Electron. 2014, 62, 922–929. [Google Scholar] [CrossRef]
  10. Arbune, P.A.; Gaikwad, A. Comparative Study of Three level and five level Inverter. Int. J. Adv. Res. Electr. Electron. Instrum. Eng. 2016, 5, 681–686. [Google Scholar]
  11. Rodriguez, J.; Lai, J.S.; Peng, F.Z. Multilevel inverters: A survey of topologies controls and applications. IEEE Trans. Ind. Electron. 2002, 49, 724–738. [Google Scholar] [CrossRef] [Green Version]
  12. Manjrekar, M.D.; Lipo, T.A. A hybrid multilevel inverter topology for drive applications. In Proceedings of the IEEE APEC’98 Thirteenth Annual Applied Power Electronics Conference and Exposition, Anaheim, CA, USA, 15–19 February 1998; pp. 523–529. [Google Scholar]
  13. Hammond, P. A new approach to enhance power quality for medium voltage ac drives. IEEE Trans. Ind. Applicat. 1997, 33, 202–208. [Google Scholar] [CrossRef]
  14. Meynard, T.A.; Foch, H. Multi-level choppers for high voltage applications. Eur. Power Electron. Drives J. 1992, 2, 41. [Google Scholar] [CrossRef]
  15. Hochgraf, C.; Lasseter, R.; Divan, D.; Lipo, T.A. Comparison of multilevel inverters for static var compensation. In Proceedings of the 1994 IEEE Industry Applications Society Annual Meeting, Denver, CO, USA, 2–6 October 1994; pp. 921–928. [Google Scholar]
  16. Tolbert, L.; Peng, F.Z.; Habetler, T. Multilevel converter for large electrical drives. IEEE Trans. Ind. Applicat. 1999, 35, 36–44. [Google Scholar] [CrossRef] [Green Version]
  17. Cao, W.; Xu, Y.; Han, Y.; Ren, B. Comparison of cascaded multilevel and modular multilevel converters with energy storage system. In Proceedings of the 2016 IEEE 11th Conference on Industrial Electronics and Applications (ICIEA), Hefei, China, 5–7 June 2016; pp. 290–294. [Google Scholar]
  18. Uddin, M.J.; Islam, M.S. Implementation of Cascaded Multilevel Inverter with Reduced Number of Components. In Proceedings of the 2021 2nd International Conference on Robotics, Electrical and Signal Processing Techniques (ICREST), Dhaka, Bangladesh, 5–7 January 2021; pp. 669–672. [Google Scholar] [CrossRef]
  19. Nabae, A.; Takahashi, I.; Akagi, H. A new neutral-point clamped PWM inverter. IEEE Trans. Ind. Applicat. 1981, IA-17, 518–523. [Google Scholar] [CrossRef]
  20. Pharne, I.D.; Bhosale, Y.N. A review on multilevel inverter topology. In Proceedings of the IEEE International Conference on Power Energy and Control (ICPEC), Dindigul, India, 6–8 February 2013; pp. 700–703. [Google Scholar]
  21. Najafi, E.; Yatim, A.H. Design and implementation of a new multilevel inverter topology. IEEE Trans. Ind. Electron. 2011, 59, 4148–4154. [Google Scholar] [CrossRef]
  22. Nedumgatt, J.J.; Kumar, D.V.; Kirubakaran, A.; Umashankar, A.S. Multilevel inverter with reduced number of switches. In Proceedings of the 2012 IEEE Students’ Conference on Electrical Electronics and Computer Science, Kollam, India, 20–21 April 2017; pp. 1–4. [Google Scholar]
  23. Manjrekar, M.; Venkataramanan, G. Advanced topologies and modulation strategies for multilevel inverters. In Proceedings of the PESC Record. 27th Annual IEEE Power Electronics Specialists Conference, Baveno, Italy, 23–27 June 1996; pp. 1013–1018. [Google Scholar]
  24. Ramani, K.; Sathik, M.A.; Sivakumar, S. A New Symmetric Multilevel Inverter Topology Using Single and Double Source Sub-Multilevel Inverters. J. Power Electron. 2015, 15, 96–105. [Google Scholar] [CrossRef] [Green Version]
  25. Motaparthiand, N.; Malligunta, K. Seven-Level Symmetrical Series/Parallel Multilevel Inverter with PWM Technique Using Digital Logic. Int. J. Electr. Comput. Eng. Syst. 2021, 12, 123–130. [Google Scholar]
  26. Buticchi, G.; Lorenzani, E.; Franceschini, G. A five level single-phase grid-connected converter for renewable distributed systems. IEEE Trans. Ind. Electron. 2013, 60, 906–918. [Google Scholar] [CrossRef]
  27. Myrzik, J.M.A. Novel inverter topologies for single-phase stand-alone or grid-connected photovoltaic systems. In Proceedings of the 4th IEEE International Conference on Power Electronics and Drive Systems, Denpasar, Indonesia, 25–25 October 2001; pp. 103–108. [Google Scholar]
  28. Wang, Y.; Li, Y.; Cao, Y.; Tan, Y.; He, L.; Han, J. Hybrid AC/DC microgrid architecture with comprehensive control strategy for energy management of smart building. Int. J. Electr. Power Energy Syst. 2018, 101, 151–161. [Google Scholar] [CrossRef]
  29. Panagis, P.; Stergiopoulos, F.; Marabeas, P.; Manias, S. Comparison of State of the Art Multilevel Inverters. In Proceedings of the IEEE Power Electronics Specialists Conference, Rhodes, Greece, 15–19 June 2008; pp. 4296–4301. [Google Scholar]
  30. Górecki, K.; Dąbrowski, J.; Krac, E. SPICE-Aided Modeling of Daily and Seasonal Changes in Properties of the Actual Photovoltaic Installation. Energies 2021, 14, 6247. [Google Scholar] [CrossRef]
  31. Piccini, A.R.; Guimarães, G.C.; de Souza, A.C.; Denardi, A.M. Implementation of a Photovoltaic Inverter with Modified Automatic Voltage Regulator Control Designed to Mitigate Momentary Voltage Dip. Energies 2021, 14, 6244. [Google Scholar] [CrossRef]
  32. Masters, G.M. Renewable and Efficient Electric Power Systems. John Wiley & Sons Inc.: Hoboken, NJ, USA, 2004. [Google Scholar]
  33. Seeman, M.D.; Sanders, S.R. Analysis and Optimization of Switched-Capacitor DC-DC Converters. IEEE Trans. Power Electron. 2008, 23, 841–851. [Google Scholar] [CrossRef]
  34. Alateeq, A.; Almalaq, Y.; Matin, M. Using SiC MOSFET in switched-capacitor converter for high voltage applications. In Proceedings of the 2016 North American Power Symposium (NAPS), Denver, CO, USA, 18–20 September 2016; pp. 1–5. [Google Scholar]
  35. Xiong, S.; Wong, S.C.; Tan, S.C.; Tse, C.K. A Family of Exponential Step-Down Switched-Capacitor Converters and Their Applications in Two-Stage Converters. IEEE Trans. Power Electron. 2014, 29, 1870–1880. [Google Scholar] [CrossRef] [Green Version]
  36. Baddipadiga, B.P.; Ferdowsi, M. A High-Voltage-Gain DC-DC Converter Based on Modified Dickson Charge Pump Voltage Multiplier. IEEE Trans. Power Electron. 2017, 32, 7707–7715. [Google Scholar] [CrossRef]
  37. Ayudhya, R.S.N. A switched-capacitor Dickson charge pumps for high-voltage high power applications. In Proceedings of the 2014 International Conference on Information Science, Electronics and Electrical Engineering, Sapporo, Japan, 26–28 April 2014; pp. 1147–1150. [Google Scholar]
  38. Abraham, C.; Jose, B.R.; Mathew, J.; Evzelman, M. Modelling, simulation and experimental investigation of a new two input, series-parallel switched capacitor converter. IET Power Electron. 2017, 10, 368–376. [Google Scholar] [CrossRef]
  39. Pérez-Nicoli, P.; Lisboa, P.C.; Veirano, F.; Silveira, F. A series–parallel switched capacitor step-up DC–DC converter and its gate-control circuits for over the supply rail switches. Analog Integr. Circuits Signal Process. 2015, 85, 37–45. [Google Scholar] [CrossRef]
  40. Dias, J.C.; Lazzarin, T.B. Steady State Analysis of Voltage Multiplier Ladder switched-capacitor cell. In Proceedings of the 2016 12th IEEE International Conference on Industry Applications (INDUSCON), Curitiba, PR, Brazil, 20–23 November 2016. [Google Scholar]
  41. Babaei, E.; Hosseini, S.H.; Gharehpetian, G.B.; Haque, M.T.; Sabahi, M. Reduction of dc voltage sources and switches in asymmetrical multilevel converters using a novel topology. Electr. Power Syst. Res. 2007, 77, 1073–1085. [Google Scholar] [CrossRef]
  42. Jayabalan, M.; Jeevarathinam, B.; Sandirasegarane, T. Reduced switch count pulse width modulated multilevel inverter. IET Power Electron. 2017, 10, 10–17. [Google Scholar] [CrossRef]
  43. Thiyagarajan, V.; Somasundaram, P. A New Seven Level Symmetrical Inverter with Reduced Switch Count. Int. J. Power Electron. Drive Syst. 2018, 9, 921–925. [Google Scholar]
  44. Barah, S.S.; Behera, S. An Optimize Configuration of H-Bridge Multilevel Inverter. In Proceedings of the 2021 1st International Conference on Power Electronics and Energy (ICPEE), Bhubaneswar, India, 2–3 January 2021; pp. 1–4. [Google Scholar]
  45. Inverter, Solar Inverter, Home Power Inverter. Available online: https://www.inverter.com/ (accessed on 24 May 2022).
Figure 1. The PV system shows the importance of using DC–AC inverter in the utility grid [32].
Figure 1. The PV system shows the importance of using DC–AC inverter in the utility grid [32].
Processes 10 01159 g001
Figure 2. The proposed 7L MLI supplied by an SC cell.
Figure 2. The proposed 7L MLI supplied by an SC cell.
Processes 10 01159 g002
Figure 3. (a) The proposed SC cell merged into a full-bridge converter to complete the proposed seven MLI. (b) Discharging mode connection of SC cell. (c) Charging mode of SC cell.
Figure 3. (a) The proposed SC cell merged into a full-bridge converter to complete the proposed seven MLI. (b) Discharging mode connection of SC cell. (c) Charging mode of SC cell.
Processes 10 01159 g003
Figure 4. Pulse width modulation techniques for the proposed 7L MLI.
Figure 4. Pulse width modulation techniques for the proposed 7L MLI.
Processes 10 01159 g004
Figure 5. Seven modes of operation for the proposed MLI supplied by an SC cell where each mode of operation presents an output voltage level.
Figure 5. Seven modes of operation for the proposed MLI supplied by an SC cell where each mode of operation presents an output voltage level.
Processes 10 01159 g005aProcesses 10 01159 g005b
Figure 6. The V c e l l _ o u t in two different modes when the input voltage and capacitor have a parallel and series connection.
Figure 6. The V c e l l _ o u t in two different modes when the input voltage and capacitor have a parallel and series connection.
Processes 10 01159 g006
Figure 7. (a) The output voltage of the proposed 7L MLI at resistive load, and (b) the output current of the proposed model with a resistive inductive load.
Figure 7. (a) The output voltage of the proposed 7L MLI at resistive load, and (b) the output current of the proposed model with a resistive inductive load.
Processes 10 01159 g007
Figure 8. The harmonic spectrum of the load voltage used to present the THD.
Figure 8. The harmonic spectrum of the load voltage used to present the THD.
Processes 10 01159 g008
Table 1. Status of all switches and capacitors for each output voltage level for the proposed MLI.
Table 1. Status of all switches and capacitors for each output voltage level for the proposed MLI.
Output Voltage LevelS1S2S3S4S5S6S7C1
+2Vin.1100010D
+1.75Vin.1110010D
+1Vin.1100101C
01100000-
−1Vin.0011101C
−1.75Vin.0111010D
−2Vin.0011010D
Table 2. A comparison of total number of components.
Table 2. A comparison of total number of components.
ParametersProposedRef. [18]Ref. [42]Ref. [43]Ref. [44]
Number of levels77775
Number of DC source13332
Number of clamped diodes00000
Number of switches712966
Number of capacitors10000
Total components9151198
Table 3. Comparison of THD and the number of elements required per level.
Table 3. Comparison of THD and the number of elements required per level.
TopologyTHD%Total Components Per Level
Proposed4.65%1.285
Ref. [18]10.7%2.142
Ref. [41]10.02%1.57
Ref. [42]17.77%1.285
Ref. [43]17.66%1.6
Publisher’s Note: MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Share and Cite

MDPI and ACS Style

Alateeq, A.; Almalaq, Y.; Alateeq, A. Optimization of a Multilevel Inverter Design Used for Photovoltaic Systems under Variable Switching Controllers. Processes 2022, 10, 1159. https://doi.org/10.3390/pr10061159

AMA Style

Alateeq A, Almalaq Y, Alateeq A. Optimization of a Multilevel Inverter Design Used for Photovoltaic Systems under Variable Switching Controllers. Processes. 2022; 10(6):1159. https://doi.org/10.3390/pr10061159

Chicago/Turabian Style

Alateeq, Ayoob, Yasser Almalaq, and Abdulaziz Alateeq. 2022. "Optimization of a Multilevel Inverter Design Used for Photovoltaic Systems under Variable Switching Controllers" Processes 10, no. 6: 1159. https://doi.org/10.3390/pr10061159

Note that from the first issue of 2016, this journal uses article numbers instead of page numbers. See further details here.

Article Metrics

Back to TopTop