New High-Speed Arithmetic Circuits Based on Spiking Neural P Systems with Communication on Request Implemented in a Low-Area FPGA

Abstract

During the last years, the demand for internet-of-things (IoT) resource-constrained devices has grown exponentially. To address this need, several digital methods have been proposed to improve these devices in terms of area and power consumption. Despite achieving significant results, improvement in these factors is still a challenging task. Recently, an emerging computational area has been seen as a potential solution to improving the performance of conventional binary circuits. In particular, this area uses a method based on spiking neural P systems (SN P) to create arithmetic circuits, such as adders, subtractors, multipliers, and divisors, since these components are vital in many IoT applications. To date, several efforts have been dedicated to decreasing the number of neurons and synapses to create compact circuits. However, processing speed is a persistent issue. In this work, we propose four compact arithmetic circuits with high processing speeds. To evaluate their performance, we designed a neuromorphic processor that is capable of performing four operations using dynamic connectivity. As a consequence, the proposed neuromorphic processor achieves higher processing speeds by maintaining low area consumption in comparison with the existing approaches.

1. Introduction

During the last 10 years, a large number of arithmetic circuits based on spiking neural P systems [1] have been proposed to improve their performance compared to conventional binary circuits [2,3]. The aim of this approach is to create circuits that achieve better area consumption and processing time when compared with conventional binary circuits. Until now, several circuits have been improved using new variants of the SN P systems [4,5], such as request rules [6], colored spikes [7], learning functions [8], structural plasticity [9], production functions on synapses [10], propagation delay [11], myelin [12], dendritic delay [13], lateral inhibition [14], enzymes [15], energy request rules [16], weights and delays on synapses [17], stochastic rules [18], microglia [19], the local synchronization of a rule [20], without duplication [21], polarizations and anti-spikes [22], inhibitory rules and time schedules [23], cooperative synapses [24], multiple channels and autapses [25], long-term potentiation and depression [26], neuron permeability [27], weights and multiple channels [28], structural plasticity and mute rules [29], autapses with partial synchronization [30], membrane potentials, inhibitory rules, and anti-spikes [31], evolution rules [32], and autapses [33]. The use of these SN P systems variants has allowed for improvements in terms of the area consumption and computational complexity of a soma. As a consequence, we reduce the number of synapses and spiking rules, respectively. From an engineering perspective, the improvement of these factors potentially allows for their implementation in resource-constrained embedded devices. Until now, several neural arithmetic circuits have been proposed to perform addition, subtraction, multiplication, and division.

In [34], Liu et al. proposed an adder circuit composed of two neurons. Frias et al. [35] presented a compact neural adder consisting of a single neuron. To improve the processing speed, Vazquez et al. [36] presented a parallel adder, in which the number of neurons and synapses were significantly decreased by ensuring a high processing speed.

Liu et al. [34] proposed a two-neuron subtractor circuit using a spike train of seven spikes. In [35], the authors presented an ultra-compact subtractor composed of one neuron. To achieve this, the authors employed a recent variant of SN P systems. Specifically, the circuit used astrocyte-like control to perform the subtraction operation. In this way, the soma includes simple spiking rules to perform processing spike by spike. As a consequence, this circuit exhibits an extremely low processing speed.

A multiplier using runtime-free SN P systems with eleven neurons was presented in [34]. On the other hand, Frias et al. [35] presented a single neuron-based multiplier to process spikes sequentially. This circuit is based on dendritic feedback connections and dendritic delays. Recently, Pichardo et al. [37] presented a high-processing-speed multiplier, which was designed to process floating-point numbers. The authors intended to improve the processing speed of the circuit by keeping the area consumption low.

The divisor circuit, proposed by Liu et al., [34], consists of ten neurons. In [38], the authors presented a sequential divisor that uses eight neurons and two types of spiking rules per neuron. Frias et al. [35] proposed a divisor using a single neuron. This circuit performs its operation sequentially. Recently, Vazquez et al. [36] presented a parallel divisor based on cutting-edge variants of SN P systems, such as dendritic delays and colored spikes.

As can be seen in a previous study of the state of the art, several authors intend to minimize the number of neurons/synapses in their arithmetic circuits. As a consequence, these circuits present low processing speeds due to their sequential processing nature. On the other hand, parallel arithmetic circuits can be seen as a potential solution. However, most of the recent proposals must still be improved in terms of their area consumption. This aspect becomes critical, especially when these circuits need to be implemented in resource-constrained devices. Hence, two great challenges remain in the development of efficient arithmetic SN P circuits:

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The first challenge is to develop a compact arithmetic SN P circuit. One crucial aspect is linked to the reduction in synapses/neurons. Specifically, the improvement of the number of synapses creates spike-distribution problems; i.e., when the spikes are distributed between neurons since there are few synapses. On the other hand, the improvement in the processing speed of the existing arithmetic circuit is still a challenging task.

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The development of customized digital architectures is currently a challenging task since most digital designs implemented in FPGA are seen as final designs. From a commercial perspective, the improvement of digital design becomes attractive in terms of area/power consumption and processing times since the development of a VLSI circuit is still quite expensive. In this application, the design of efficient hardware architectures to properly simulate new variants of the SN P systems is a challenging task.

Here, we present two proposals to solve the above challenges:

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Development of four compact arithmetic circuits. Here, we propose four arithmetic circuits: adder, subtract, multiplier, and divider. Specifically, we use a cutting-edge variant of SN P systems called communication on request, which has allowed us to improve the distribution time between neurons using the minimum number of synapses. This variant acts as an arbiter to dynamically distribute the spikes between neurons. In this way, the processing time of the proposed circuits is significantly reduced.

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Development of a neuromorphic processor. In this work, we designed a customized neuromorphic processor (NP) to support the variant of SN P systems called communication on request to perform four proposed arithmetic circuits using dynamic neural network connectivity, which is supported by simple multiplexers. As a result, we have created a high-speed and compact neuromorphic processor that can be implemented in resource-constrained FPGAs.

The rest of this article is organized as follows. Section 2 briefly describes the spiking neural P system with communication on request and presents the proposed compact arithmetic circuits, and in Section 3, we show the digital design strategy for the efficient implementation of the proposed neuromorphic processor. Finally, Section 4 presents the conclusions.

2. Proposal of Arithmetic Circuits Based on Spiking Neural P Systems with Communication on Request

Here, we mainly use a cutting-edge variant of SN P systems called communication on request to improve the communication between neurons. Specifically, the use of this variant allows us to efficiently transmit spikes between neurons since each neuron can request the spikes contained in the neighboring neurons. In the case of two or more neurons requesting spikes from the same neuron, the spikes are replicated. In this way, information can be contained safely and transferred during spike propagation between neurons. Before presenting the proposed arithmetic circuits, we introduce the formal definition of the spiking neural P system with communication [6], as follows:

$$\Pi =(O,{\sigma }_1,\dots ,{\sigma }_m,a_{i_0},out)$$

(1)

where the following applies:

• $O=\{a_1,a_2,\dots ,a_k\}$ is the alphabet, $a_i$ is a type of spike, and $k\ge 1$ is the number of different types of spikes.
• The neurons are denoted as ${\sigma }_i=(u_i,R_i)$, $1\le i\le m$, and m is the number of neurons, where the following applies:

  (a)

  $u_i$ is a sequence of elements of O, where each element in O can be omitted or appear with a certain multiplicity.

  (b)

  $R_i$ is a rule of the form $E/Qw$, where E is a regular expression over O, and w is a query of the form $(a_s^p,j)$ and $(a_s^{\infty },j)$, $1\le s\le k$, $p\ge 0$, $1\le j\le m$. There are a finite number of queries and rules.

  (c)

  $\mathit{out}\in \{1,2,\dots ,m\}$ indicates the output neuron (where the computation result is stored).

2.1. Neural Adder Circuit

Figure 1 shows the neural circuit composed of two neurons, ${\sigma }_1$ and ${\sigma }_2$, to perform the addition operation $x+y$.

The proposed neural adder works as follows.

At the initial simulation step, neurons ${\sigma }_1$ and ${\sigma }_2$ are loaded with the numbers x and y, respectively. During the first simulation step, ${\sigma }_2$ requires x spikes from neuron ${\sigma }_1$. Therefore, neuron ${\sigma }_2$ performs an intrinsic addition since x spikes are transferred from neuron ${\sigma }_1$. After this step, the adder circuit stops working because neuron ${\sigma }_1$ is empty.

According to the formal definition of SN P systems (Equation (1)), the proposed neural adder circuit is mathematically expressed as follows:

$$\begin{array}{c}\hfill {\Pi }_{add}=(O,{\sigma }_1,{\sigma }_2,out)\end{array}$$

(2)

where the following applies:

$$O=\left\{a\right\}$$

$${\sigma }_1=\{a=x\}$$

$${\sigma }_2=\{a=y,R_1=a^{*}/Q(a^x,1)\}$$

$$out=\left\{{\sigma }_2\right\}$$

As can be observed from

Table 1. Comparison between the proposed SNQ P adder and existing SN P adders in terms of neurons and simulation steps.

Authors	Number of Neurons	Simulation Steps
This approach	2	1
Frias et al. [35]	1	x
Liu et al. [34]	2	x + y

, the proposed adder maintains the same number of neurons used in [34]. However, our proposal achieves better a processing time when compared with [34,35] since our proposed adder expends only one simulation step to perform the addition of two numbers with any length.

2.2. Neural Subtractor Circuit

Figure 2 shows the proposed neural subtractor circuit to perform the operation $|x-y|$ using four neurons, ${\sigma }_1$, ${\sigma }_2$, ${\sigma }_3$, and ${\sigma }_4$. The proposed neural subtractor circuit works as follows.

At the first simulation step, neuron ${\sigma }_3$ extracts q spikes, where q is the minimum value between x and y. Therefore, neuron ${\sigma }_3$ applies the the first rule, $\lambda /Q(a^x,1)(a^x,2)(a,4)$, when $x<y$; otherwise, the second rule is applied, $\lambda /Q(a^y,1)(a^y,2)(a,4)$. In the next simulation step, neuron ${\sigma }_4$ extracts all spikes from neurons ${\sigma }_1$ and ${\sigma }_2$. After that, no other rules can be applied. At this simulation step, the system stops. In this manner, the neural subtractor circuit is obtained, and the result $|x-y|$ is stored in neuron ${\sigma }_4$.

The proposed neural subtractor circuit is defined as follows:

$${\Pi }_{sub}=(O,{\sigma }_1,{\sigma }_2,{\sigma }_3,{\sigma }_4,out)$$

(3)

where the following applies:

$$O=\left\{a\right\}$$

$${\sigma }_1=\{a=x\}$$

$${\sigma }_2=\{a=y\}$$

$${\sigma }_3=\{a=w,R_1=\lambda /Q(a^x,1)(a^x,2)(a,4),R_2=\lambda /Q(a^y,1)(a^y,2)(a,4)\}$$

$${\sigma }_4=\{a=z=1,R_1=\lambda /Q(a^{\infty },1)(a^{\infty },2)\}$$

$$out=\left\{{\sigma }_4\right\}$$

Table 2. Comparison between the proposed SNQ P subtractor and existing SN P subtractors in terms of neurons and simulation steps.

Authors	Number of Neurons	Simulation Steps
This approach	4	2
Frias et al. [35]	1	y
Liu et al. [34]	2	x + y

shows that our subtractor circuit only requires two simulation steps to perform the operation $|x-y|$. Evidently, this value is much lower than that obtained via other approaches.

2.3. Neural Multiplier Circuit

To design the proposed neural multiplier circuit, we use four neurons: ${\sigma }_1$, ${\sigma }_2$, ${\sigma }_3$, and ${\sigma }_4$ to perform the operation $xy$, as shown in Figure 3.

This multiplier circuit works as follows.

At the first simulation step, neuron ${\sigma }_2$ requests $y-1$ spikes from ${\sigma }_3$ and one spike from ${\sigma }_1$. Therefore, ${\sigma }_2$ contains y spikes, which are requested via neurons ${\sigma }_3$ and ${\sigma }_4$ at the next simulation step. During the subsequent simulation steps, this operation is repeated $x-1$ times until neuron ${\sigma }_4$ stores the product $xy$.

In general terms, the proposed multiplier performs the multiplication based on recursive additions since this circuit includes a feedback loop. Specifically, neuron ${\sigma }_2$ and neuron ${\sigma }_3$ are connected by means of this loop. From the engineering point of view, the use of this strategy has allowed us to improve the area consumption since the implementation of adders requires fewer logic gates than a conventional multiplier.

The proposed neural multiplier is defined as

$${\Pi }_{mul}=(O,{\sigma }_1,{\sigma }_2,{\sigma }_3,{\sigma }_4,out)$$

(4)

where the following applies:

$$O=\left\{a\right\}$$

$${\sigma }_1=\{a=x\}$$

$${\sigma }_2=\{a=v,R_1=\lambda /Q(a^{y-1},3)(a,1)\}$$

$${\sigma }_3=\{a=y,R_1=a^{*}/Q(a^v,2))\}$$

$${\sigma }_4=\{a=w,R_1=a^{*}/Q(a^v,2))\}$$

$$out=\left\{{\sigma }_4\right\}$$

Table 3. Comparison between the proposed SNQ P multiplier and existing SN P multipliers in terms of neurons and simulation steps.

Authors	Number of Neurons	Simulation Steps
This approach	4	2x + 1
Frias et al. [35]	1	xy
Liu et al. [34]	11	xy

shows that our multiplier circuit requires $2x+1$ simulation steps to perform a multiplication. Therefore, the proposed multiplier expends fewer simulation steps than the existing neural multipliers.

2.4. Neural Divider Circuit

Figure 4 shows the neural divider circuit, in which we use two neurons (${\sigma }_1$ and ${\sigma }_2$) to perform the operation $x/y$.

The proposed neural divider circuit works as follows.

At each simulation step, neuron ${\sigma }_2$ extracts y spikes from neuron ${\sigma }_1$ at each simulation step. Therefore, ${\sigma }_2$ increases its number of spikes by one. At the end of the simulation process, ${\sigma }_2$ contains the quotient $\lfloor x/y\rfloor$.

Basically, the proposed divider performs the division based on recursive subtractions since this neural circuit in associated with a requesting rule enabled in neuron ${\sigma }_2$ to cyclically extract spikes from neuron ${\sigma }_1$. In this way, the proposed circuit performs the division based on inherent subtractions. From the engineering point of view, the use of this strategy has allowed us to improve the area consumption since the implementation of the subtractor requires fewer logic gates than a conventional divisor.

The proposed neural divider circuit can be described as follows:

$${\Pi }_{div}=(O,{\sigma }_1,{\sigma }_2,syn,out)$$

(5)

where the following applies:

$$O=\left\{a\right\}$$

$${\sigma }_1=\{a=x\}$$

$${\sigma }_2=\{a=y,R_1=a^{*}/Q(a^y,1)\}$$

$$syn=\left\{sy{n}_1({\sigma }_2,R_1=-(y-1))\right\}$$

$$out=\left\{{\sigma }_2\right\}$$

As can be observed from

Table 4. Comparison between the proposed SNQ P divider and existing SN P dividers in terms of neurons and simulation steps.

Authors	Number of Neurons	Simulation Steps
This approach	2	$\lfloor x/y\rfloor$
Frias et al. [35]	1	x
Frias et al. [38]	8	22x
Liu et al. [34]	10	x/y

, our divider circuit improves the number of neurons by keeping the number of simulation steps low.

3. Digital Design of the Proposed Neuromorphic Processor (NP)

Once the neural arithmetic circuits were carefully analyzed and compared with those of existing approaches, we designed a customized digital architecture to mimic the neural behavior of the proposed arithmetic circuits, as shown in Figure 5. We employed conventional combinational and sequential logic circuits, such as an adder, multiplexers, comparators, and a counter to create a compact and high-speed neuromorphic processor, $NP$. Here, we mainly use a control unit, $CU$, and multiplexers to create a multi-arithmetic circuit implemented in 64 bits; i.e., this processor performs four arithmetic operations of two positive integers, x and y, by enabling their respective operation code, $op$, (00 → addition, 01 → subtraction, 10 → multiplication, and 11 → division). Additionally, we incorporate an adder with a load enabled, $en\_ld$, to execute the request rules, $en\_op$. This allows spikes to be transferred from the registers of the CU to the adder according to the specific operation. Additionally, we use a second adder to obtain the quotient. This occurs when the signal $en\_a$ is enabled. Finally, the result is provided via the output w. On the other hand, this strategy has enabled us to perform four arithmetic operations using a simple adder as the main processing core. To prove their performance, we implement the proposed $NP$ in a low-cost and low-area Altera Cyclone IV EP4CE22F17C6N FPGA. In addition, we implemented an existing processor [35] to achieve a coherent comparison since both neuromorphic processors can perform four operations using dynamic multiplexing connectivity.

Table 5. Performance comparison between the proposed NP and an existing neural processor in terms of area and power consumption.

Works	Logic Elements (LEs)	Power Consumption (mW)
This work	642	13
Frias et al. [35]	563	245
64-bit conventional digital adder	165	70
64-bit conventional digital subtractor	185	90
64-bit conventional digital multiplier	202	101
64-bit conventional digital divider	251	115

shows the comparison between these two 64-bit processors in terms of area/power consumption. As can be observed, the existing processor [35] requires less area since it requires fewer components in comparison with the proposed neural processor; $NP$, however, demands higher power since each number is represented by a sequence of spikes, while the proposed $NP$ represents the number as a group of spikes. Therefore, the existing processor performs processing spike by spike; i.e., the processing time is defined in terms of the length of the number. Therefore, the existing processor was designed mainly using buses of one bit length, which ensures low area consumption. Here, we make extraordinary efforts to design the proposed $NP$ with the minimum digital elements in order to guarantee low area consumption. Specifically, we use dynamic connectivity based on multiplexors. In addition, we implement conventional 64-bit arithmetic circuits, such as an adder, a subtrator, a multiplier, and a divisor. As can be observed from Table 5, existing approaches based on spiking neural P systems can perform four operations using the same processor, while the conventional arithmetic circuits require a specific configuration. In general, each conventional circuit is implemented separately. Therefore, if these circuits are implemented in a single processor, they require more area than the neural circuits.

4. Conclusions

In this work, we have presented an optimized design of four new arithmetic circuits based on spiking neural P (SN P) systems with a communication request. The use of this variant has allowed us to significantly improve the processing speed by keeping a low level of area consumption. In addition, we have designed a compact 64-bit neuromorphic processor, $NP$, to perform the proposed four arithmetic operations. Due to the compactness and high processing speeds of the NP, this element can be useful in IoT applications, especially when it is implemented in resource-constrained devices.