Ibrahim, A.; Gebali, F.; Bouteraa, Y.; Tariq, U.; Ahamad, T.; Nazih, W.
Low-Space Bit-Parallel Systolic Structure for AOP-Based Multiplier Suitable for Resource-Constrained IoT Edge Devices. Mathematics 2022, 10, 815.
https://doi.org/10.3390/math10050815
AMA Style
Ibrahim A, Gebali F, Bouteraa Y, Tariq U, Ahamad T, Nazih W.
Low-Space Bit-Parallel Systolic Structure for AOP-Based Multiplier Suitable for Resource-Constrained IoT Edge Devices. Mathematics. 2022; 10(5):815.
https://doi.org/10.3390/math10050815
Chicago/Turabian Style
Ibrahim, Atef, Fayez Gebali, Yassine Bouteraa, Usman Tariq, Tariq Ahamad, and Waleed Nazih.
2022. "Low-Space Bit-Parallel Systolic Structure for AOP-Based Multiplier Suitable for Resource-Constrained IoT Edge Devices" Mathematics 10, no. 5: 815.
https://doi.org/10.3390/math10050815
APA Style
Ibrahim, A., Gebali, F., Bouteraa, Y., Tariq, U., Ahamad, T., & Nazih, W.
(2022). Low-Space Bit-Parallel Systolic Structure for AOP-Based Multiplier Suitable for Resource-Constrained IoT Edge Devices. Mathematics, 10(5), 815.
https://doi.org/10.3390/math10050815