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A High-Level Synthesis Implementation and Evaluation of an Image Processing Accelerator

1
Department of Informatics and Telecommunications Engineering, University of Western Macedonia, Kozani 50100, Greece
2
Laboratory of Digital Systems and Computer Architecture, Karamanli and Ligeris Str, Kozani GR-50100, Greece
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Author to whom correspondence should be addressed.
This paper is an extended version of our paper published in the Proceedings of the 7th International Conference on Modern Circuit and System Technologies on Electronics and Communications (MOCAST 2018), Thessaloniki, Greece, 7–9 May 2018.
Technologies 2019, 7(1), 4; https://doi.org/10.3390/technologies7010004
Received: 14 November 2018 / Revised: 19 December 2018 / Accepted: 21 December 2018 / Published: 23 December 2018
(This article belongs to the Special Issue Modern Circuits and Systems Technologies on Electronics)
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Abstract

Most frequently, an FPGA is used as an implementation platform in applications of graphics processing, as its structure can effectively exploit both spatial and temporal parallelism. Such parallelization techniques involve fundamental restrictions, namely being their dependence on both the processing model and the system’s hardware constraints, that can force the designer to restructure the architecture and the implementation. Predesigned accelerators can significantly assist the designer to solve this problem and meet his deadlines. In this paper, we present our accelerators for Grayscale and Sobel Edge Detection, two of the most fundamental algorithms used in digital image processing projects. We have implemented those algorithms with a “bare-metal” VHDL design, written purely by hand, as a portable USB accelerator device, as well as an HLS-based overlay of a similar implementation designed to be used by a Python interface. The comparisons of the two architectures showcase that the HLS generated design can perform equally to or even better than the handwritten HDL equivalent, especially when the correct compiler directives are provided. View Full-Text
Keywords: high level synthesis; image processing; accelerator; FPGA; python; HDL high level synthesis; image processing; accelerator; FPGA; python; HDL
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This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).
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Tsiktsiris, D.; Ziouzios, D.; Dasygenis, M. A High-Level Synthesis Implementation and Evaluation of an Image Processing Accelerator. Technologies 2019, 7, 4.

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