#
Multi-Objective Comparative Analysis of Active Modular Rectifier Architectures for a More Electric Aircraft^{ †}

^{1}

^{2}

^{*}

^{†}

## Abstract

**:**

## 1. Introduction

## 2. Suitability of Active Rectifier Topologies in MEA

#### 2.1. Application Requirements and Operating Scenario

#### 2.2. Evaluation and Limitations of Active Rectifier Topologies

- 1.
- Two-stage configuration: considering the best PF operating condition case in Table 1, the active rectifier presents unity PF operation, and, according to the phasor diagram in Figure 2a, ${V}_{conv}$ > ${V}_{ph}$. Thus, the rectifier output voltage (V${}_{DC}$ > 282 V) does not fulfil the application requirements and a posterior DC/DC conversion is required to achieve the specified output 270 V${}_{DC}$, expressed as ${V}_{DC}^{\prime}$.
- 2.
- Single-stage configuration: considering the worst PF operating condition case in Table 1, the active rectifier performs at PF = 0.85 lagging and, therefore, ${V}_{conv}$ ≤ ${V}_{ph}$ condition is fulfilled, as depicted in Figure 2b. Therefore, no additional converter is required downstream for achieving the targeted 270 V${}_{DC}$.

#### 2.3. Proposed Converter Configurations for Operating at Unity PF

## 3. Comparison Framework for Active Rectification Architectures

#### 3.1. Efficiency Estimation

#### 3.2. Volume Estimation

#### 3.2.1. Cooling System Volume

- For safety reasons, the achievable maximum junction temperature was defined as 15 °C lower than the data sheet temperature and, hence, was limited to 185 °C.
- Water-cooling was assumed in order to achieve a high power density architecture. Based on the cooling system specifications of “IQ-evolution” [43], a temperature jump from heat sink to ambient, $\mathrm{\Delta}{T}_{h-amb}$, of 15 °C is defined.
- An ambient temperature of 70 °C is assumed according to the worst case temperature in [30].
- Due to the high frequency of the SG voltage, the junction temperature ripple of the power semiconductor devices is negligible. Thus, instead of the transient impedances, only the thermal resistance is considered in this comparison.

#### 3.2.2. Volume of the Passive Components

#### 3.3. Reliability Estimation

#### 3.3.1. Cosmic Ray Failure Rate

- A 50% for the power devices of the AC/DC stage;
- A 13.5% and 86.5% for the upper and down power devices in the DC/DC stage of 2L${}_{2}$ converter, respectively.

#### 3.3.2. Wear-Out Performance Analysis

- The MOSFET lifetime model and the fitting parameters employed derived from testing data in [46];
- The thermal and electrical parameters related to the power devices, which could vary due to the manufacturing process and semiconductor technology; or
- The simplified mission profile, which could vary with the climate change and load conditions.

## 4. Converter Configuration and Architecture Design

- The operating PF of the power converters were analyzed by the equation describing the phase diagrams in Figure 2, being,$${V}_{conv}^{2}={({V}_{ph}-{V}_{L}\xb7sin\left(\phi \right))}^{2}+{({V}_{L}\xb7cos\left(\phi \right))}^{2}$$$${V}_{L}=2\pi fL{i}_{L}=2\pi fL\xb7\frac{P}{3{V}_{ph}cos\left(\phi \right)}$$We should note that, in the case of 2L${}_{C}$ and 2L${}_{st}$ single-stage configurations (PF < 1), the higher the operating PF, the lower the reactive power to be compensated and, hence, higher efficiency. If (1) and (13) are merged, the maximum operating PF of these topologies can be obtained depending on ${V}_{L}$ for a fixed m,$$cos\left(\phi \right)=\sqrt{1-{\left(\frac{{V}_{ph}^{2}+{V}_{L}^{2}-{\left(\frac{m\xb7{V}_{DC}}{2\sqrt{2}}\right)}^{2}}{2\phantom{\rule{0.166667em}{0ex}}{V}_{ph}\phantom{\rule{0.166667em}{0ex}}{V}_{L}}\right)}^{2}}$$
- Space vector pulse width modulation (SVPWM) pattern is assumed and a maximum m = 1.13 to ensure the minimum conduction and blocking times of the employed semiconductor.
- The converter nominal power is defined by means of a thermal analysis based on the steady-state thermal model described in Section 3.2.1. This way, the maximum converter switching frequency is obtained depending on P while maintaining an efficiency result of ≥ 97%. The results of the thermal analysis are illustratively represented in Figure 6.
- Due to restrictive harmonic limitations imposed, a differential LCL filter mode was considered for this application [30,56], where the grid-side inductance corresponded to an assumed SG synchronous inductance of ${L}_{SG}$ = 93.5 $\mathsf{\mu}$H (calculated in Appendix A) [57]. Thus, an LC filter was assumed for each power converter configuration. The power quality ($TH{D}_{i}$ ≤ 3%) and harmonic requirements must be fulfilled at the point of regulation (POR), i.e., the point where the active modular architecture is connected to the SG. This concept is represented in Figure 7, where a considered number of synchronized converters, ${N}_{conv}$, are connected to the POR. Due to the ${N}_{conv}$ converter parallelization, the filter inductance and capacitance for the ideal LCL filter of the overall architecture are defined as $L/{N}_{conv}$ and $C\xb7{N}_{conv}$, respectively. Thus, based on the transfer function of the equivalent single-phase LCL filter in [58], the transfer function of the architecture LCL filter is defined as$$H\left(s\right)=\frac{{i}_{SG}}{{V}_{conv}}=\frac{1}{{s}^{3}\frac{L}{{N}_{conv}}C{N}_{conv}{L}_{SG}+s\left(\frac{L}{{N}_{conv}}+{L}_{SG}\right)}=\frac{1}{{s}^{3}LC{L}_{SG}+s\left(\frac{L}{{N}_{conv}}+{L}_{SG}\right)}$$Special attention should be paid to the third order filter term in (16), which presents a 60 dB/decade asymptote, since its cut-off frequency is determined by the term $LC{L}_{sg}$. Therefore, independent of the number of converters connected to the POR, the cut-off frequency of the 60 dB/decade asymptote is maintained constant. This fact provides the possibility of defining the input filter capacitor for high frequency harmonics filtering without considering ${N}_{conv}$.
- The dc-link capacitor, ${C}_{link}$, of the three configurations is defined for a specific peak-to-peak switching voltage ripple, $\mathrm{\Delta}{V}_{DC}$, according to [59]. Hence,$${C}_{link}=\frac{\widehat{{i}_{L}}}{4\phantom{\rule{0.166667em}{0ex}}{f}_{sw}\xb7\mathrm{\Delta}{V}_{DC}}$$

#### 4.1. Two-Stage Architecture-2L${}_{2}$

#### 4.2. Single-Stage with Capacitor Bank Architecture-2L${}_{C}$

#### 4.3. Single-Stage with STATCOM Architecture-2L${}_{st}$

## 5. Comparative Analysis among Different Architectures

## 6. Conclusions

## Author Contributions

## Funding

## Institutional Review Board Statement

## Informed Consent Statement

## Data Availability Statement

## Acknowledgments

## Conflicts of Interest

## Appendix A. Starter-Generator Impedance Estimation

## References

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**Figure 1.**Examples of (

**a**) a simplified electric power system architecture based on “single-bus” MEA topology, and (

**b**) the proposed simplified active modular converter architecture.

**Figure 2.**Phasor diagram and converter configuration at (

**a**) two-stage and unity PF operation, and, (

**b**) single-stage and lower than unity PF operation.

**Figure 3.**Schematics of the (

**a**) two-stage 2L${}_{2}$ and the single-stage, (

**b**) 2L${}_{C}$, and (

**c**) 2L${}_{st}$ configurations.

**Figure 4.**(

**a**) Unreliability curves for an architecture formed identical converters based on a single device type, and, (

**b**) zoomed curves where the ${B}_{1}$ parameter is presented.

**Figure 7.**Simplified single-phase architecture equivalent circuit for the high frequency harmonic filtering analysis.

**Figure 9.**Ripple sweep analysis for calculating the stored energy in the input filter passive elements.

**Figure 10.**DM input filter results of 2L${}_{2}$ architecture for fulfilling LF and HF requirements.

**Figure 12.**DM input filter results of 2L${}_{C}$ architecture for fulfilling LF and HF requirements.

**Figure 13.**Comparison of the stored energy in the passive elements for 2L${}_{C}$ converter configurations.

**Figure 15.**The 2L${}_{st}$ architecture efficiency depending on the input filter capacitance (operating at ${V}_{ph}$ = 115 V and f = 360 Hz).

**Figure 16.**DM input filter results of 2L${}_{st}$ architecture for fulfilling LF and HF requirements.

**Figure 17.**Normalized comparative analysis among the designed 2L${}_{2}$, 2L${}_{C}$, and 2L${}_{st}$ architectures.

**Figure 18.**Normalized comparative analysis among 2L${}_{2}$, 2L${}_{C}$, and 2L${}_{st}$ architectures when three redundancies are considered.

Parameter | Value |
---|---|

Nominal phase RMS voltage, ${V}_{ph}$ | 115 V |

Steady state phase RMS voltage | 100–122 V |

Steady state frequency, f | 360–800 Hz |

Power factor, PF | 0.85–1 |

Current total harmonic distortion, THD${}_{i}$ | ≤3% |

Nominal DC voltage, ${V}_{DC}$ | 270 V |

Steady state DC voltage | 250–280 V |

Architecture power rating | 150 kW |

Targeted efficiency | ≥97% |

**Table 2.**Sea level FIT/cm${}^{2}$ rates from the universal curve considering a semiconductor breakdown voltage of ${V}_{bd}$ = 1151 V.

Configuration | ${\mathit{V}}_{\mathit{ds}}$ | ${\mathit{\lambda}}_{\mathbf{0}}$ |
---|---|---|

2L${}_{C}$ & 2L${}_{st}$ | 270 V | 1.74 · 10${}^{-4}$ |

2L${}_{2}$ | 312 V | 3.38 · 10${}^{-5}$ |

2L${}_{st}$ | 459 V | 0.0304 |

**Table 3.**Summary of the design parameters of 2L${}_{2}$, 2L${}_{C}$, and, 2L${}_{st}$ architectures.

2L${}_{2}$ | 2L${}_{\mathit{C}}$ | 2L${}_{\mathbf{st}}$ | |
---|---|---|---|

Converter nominal power, P | 18.75 kW | 16.67 kW | 18.75 kW |

N° of SiC MOSFET, ${N}_{dev}$ | 10 | 6 | 6 |

N° of converters, ${N}_{conv}$ | 8 | 9 | 8 + 3 |

AC/DC switching frequency, ${f}_{sw}$ | 80 kHz | 100 kHz | 80 kHz |

SG current distortion, $TH{D}_{i}$ | 0.05% | 0.11% | 0.13% |

SG inductance, ${L}_{SG}$ | 93.5 $\mathsf{\mu}$H | 93.5 $\mathsf{\mu}$H | 93.5 $\mathsf{\mu}$H |

Input filter inductance, L | 94 $\mathsf{\mu}$H | 342.25 $\mathsf{\mu}$H | 191.4 $\mathsf{\mu}$H |

Input filter capacitance, C | 18 $\mathsf{\mu}$F | 68.64 $\mathsf{\mu}$F | 19 $\mathsf{\mu}$F |

DC bus capacitance, ${C}_{link}$ | 44.73 $\mathsf{\mu}$F | 42.82 $\mathsf{\mu}$F | 52.18 $\mathsf{\mu}$F |

AC/DC stage output voltage, ${V}_{DC}$ | 312 V | 270 V | 270 V & 459 V |

DC/DC stage output voltage, ${V}_{DC}^{\prime}$ | 270 V | - | - |

DC/DC switching frequency, ${f}_{sw}$ | 75 kHz | - | - |

DC/DC inductance, ${L}_{dc}$ | 139.6 $\mathsf{\mu}$H | - | - |

DC/DC capacitance, ${C}_{dc}$ | 1.07 $\mathsf{\mu}$F | - | - |

Maximum temperature rise, $\mathrm{\Delta}{T}_{j-amb}$ | 55.13 °C | 66.28 °C | 58.73 °C |

Heat sink thermal resistance, ${R}_{h-amb}$ | 0.027 °C/W | 0.03 °C/W | 0.032 °C/W |

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**MDPI and ACS Style**

Atutxa, U.; Baraia-Etxaburu, I.; López, V.M.; González-Hernando, F.; Rujas, A. Multi-Objective Comparative Analysis of Active Modular Rectifier Architectures for a More Electric Aircraft. *Aerospace* **2022**, *9*, 98.
https://doi.org/10.3390/aerospace9020098

**AMA Style**

Atutxa U, Baraia-Etxaburu I, López VM, González-Hernando F, Rujas A. Multi-Objective Comparative Analysis of Active Modular Rectifier Architectures for a More Electric Aircraft. *Aerospace*. 2022; 9(2):98.
https://doi.org/10.3390/aerospace9020098

**Chicago/Turabian Style**

Atutxa, Unai, Igor Baraia-Etxaburu, Víctor Manuel López, Fernando González-Hernando, and Alejandro Rujas. 2022. "Multi-Objective Comparative Analysis of Active Modular Rectifier Architectures for a More Electric Aircraft" *Aerospace* 9, no. 2: 98.
https://doi.org/10.3390/aerospace9020098