Single Inductor Multiple Output Auto-Buck-Boost DC–DC Converter with Error-Driven Randomized Control

Abstract

We propose a single inductor multiple output (SIMO) auto-buck-boost DC–DC converter with error-driven randomized control (EDRC). The conventional controls in a SIMO DC–DC converter supply power to outputs that have been selected in a sequential order. Furthermore, they control the inductor current levels at either edge of a switching period in a steady state to be at the same level to alleviate cross-regulation. However, this limits the flexibility of the converter to respond to changes in load requirements. A sequential selection of light loads results in these loads being selected more often than a load demand, degrading the efficiency for light loads. In addition, limited flexibility leads to delayed responses. This paper introduces an auto-buck-boost topology that selects outputs based on output errors, and instantaneously adjusts the inductor current level. Moreover, we propose a technique for allowing any output to avoid selection when all outputs are fully supplied. The proposed EDRC scheme achieves improvements in efficiency in regards to light loads, cross-regulation, and output driving capability.

1. Introduction

Since the early 2000s, researchers have investigated and studied single inductor multiple output (SIMO) DC–DC converters. A SIMO DC–DC converter employs a single inductor (instead of multiple inductors) to convert a DC voltage to multiple DC voltages. Prior to 2005, researchers had proposed SIMO DC–DC converters that regulate only buck outputs or boost outputs [1,2]. In accordance with increasingly diverse power requirements of circuit systems, SIMO DC–DC converters capable of regulating both buck and boost outputs were subsequently proposed [3,4,5]. The works in [3,4,5] were designed based on the assumption that the output type for both buck and boost outputs does not change during the operation of the converter. However, in reality, an input voltage variation dependent upon the state of charge (SoC) of a battery affects the output types. The operating modes of the outputs of a SIMO DC–DC converter must change to maintain a constant supply voltage if the SoC of a battery is altered during operation of the converter. The ability to achieve regulation of output voltages through adaptive changes in the operating mode depending on the varying relationship of the input voltage is known as the auto-buck-boost capability [6,7]. In a SIMO DC–DC converter, the outputs of the converter time-share the single inductor of the converter [1,2,3,4,5,6,7,8]. This causes the outputs to become cross-coupled; thus, any abrupt change in an output load will result in changes in all other outputs. This problem is known as the cross-regulation problem [1,2].

Moreover, the limited capacitance of the filtering capacitors connected in shunt to each output limits the current driving capability. Accordingly, there is a need for a design scheme that enhances performance with regard to both cross-regulation and output-driving capability. Another critical performance indicator regarding SIMO DC–DC converters is the efficiency in light loads. The degradation in efficiency for light loads with low-power outputs is a disadvantage of the SIMO DC–DC converter.

The SIMO converters reported in [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18], select their respective outputs in a sequential order, and adjust the duty ratio of each of their respective outputs to control the power delivered to the respective outputs, as shown in Figure 1a. In the conventional sequential-order-based output selection scheme, an increase in the duty ratio of a SIMO DC–DC converter output reduces the length of the time duration when the inductor can be energized and de-energized for the other outputs, as the outputs time-share a predetermined time interval, causing cross-regulation.

In a SIMO DC–DC converter with a discontinuous conduction mode (DCM), to mitigate the cross-regulation arising from the sequential-order-based output selection, the inductor current is energized at a level equal to zero, returned to zero after a power delivery, and maintained at zero until the start of the energizing cycle of the next output [1]. The timing margin of the zero-inductor-current allows the inductor current level at the start of the energizing cycle of the next output to be zero. However, under certain load requirements, this timing margin is not guaranteed. Such load requirements interfere with the initial value of the inductor current at the start of the energizing cycle of the next output. They cause the SIMO DC–DC converter to deviate from the controllable range, causing severe cross-regulation. Accordingly, the output driving capability is limited, and the cross-regulation is not completely resolved. Moreover, the return of the inductor current level to zero after each power delivery causes the inductor current to flow discontinuously, limiting the total supply of output power.

In a SIMO DC–DC converter with a pseudo-continuous conduction mode (PCCM), the inductor current is energized at a level greater than zero, and returned to the level after a power delivery. The level is then maintained until the start of the energizing cycle of the next output [2]. Continuous conduction of the inductor current improves the current driving capability, more so than in the case of a SIMO DC–DC converter with a DCM. In a PCCM scheme, to maintain the inductor current at a constant level, it is mandatory to have a freewheeling technique for circulating the inductor current, shunting the freewheeling cycle. Consequently, in any given time slot, it is necessary to include an additional cycle for shunting the inductor, and the implementation thereof increases the circuit complexity. Moreover, as in the case of the DCM scheme, under specific load requirements, the related timing margin is not guaranteed. In such cases, severe cross-regulation will occur.

In a control scheme with sequential-order-based output selection, there is a topological disadvantage with regard to efficiency in light loads: in any given time-slot, an output must be selected, regardless of the load–current demand. If an output without a load demand is sequentially selected, it may cause an unwanted output ripple voltage, and a degradation of power efficiency. To alleviate the degradation of efficiency with light loads, the error-based control (EBC) proposed in [14] prioritizes outputs based on output errors, and instantaneously selects output with the maximum output error according to the priority of the output selection, as shown in Figure 1b. Such error-based output selection allows light loads to be selected less often than heavy loads. The EBC adopts a hybrid architecture comprising of a switching converter and an add-on linear regulator to mitigate cross-regulation. The linear regulator instantaneously provides current to any of the output channels requiring additional current because of variations in the load requirements. However, in a SIMO converter with error-based output selection, the topology only regulates buck outputs. Moreover, its design has not been fully investigated in regards to whether it can collectively improve the cross-regulation, efficiency with light loads, and output driving capability.

Figure 2 shows power stage of a single inductor buck-boost DC–DC converter and inductor current paths for switching control modes [3,4,16,17,18,19,20,21,22,23]. There are four possible switching control modes of inductor current paths, which are the energizing inductor (SWE), de-energizing inductor (SWD), bypassing (SWB), and freewheeling path (SWF) [17].

In this study, we propose a SIMO auto-buck-boost DC–DC converter with error-driven randomized control (EDRC). In the proposed SIMO converter, we use an error-based output selection, which is an extended version of the auto-buck-boost topology. Additionally, we introduce a control scheme for instantaneously adjusting the inductor current level according to the load requirement to lessen cross-regulation, without the need of an additional current supply such as an add-on linear regulator.

This paper is organized as follows. Section 2 presents the control method and architecture behind the EDRC scheme of the proposed converter. Section 3 presents the MATLAB simulation results. Section 4 shows experimental results based on implementing the proposed converter with three buck-boost outputs with discrete components. Section 5 presents a discussion of the proposed converter. Finally, we concluded this work in Section 6.

2. Proposed SIMO Architecture and Control Scheme

In this section, we introduced the operational principle, condition setting of the deep boost, and architecture of the proposed SIMO auto-buck-boost DC–DC converter with EDRC.

2.1. Error-driven Randomized Control (EDRC) for Auto Buck-Boost SIMO Converter

We used the power stage shown in Figure 2, which is from a non-inverting buck-boost DC–DC converter in the proposed converter, which is capable of simultaneously regulating buck and boost outputs.

Figure 3a, b illustrates inductor current waveforms of two operation modes, inductor power switching mode A (${\mathrm{IPSM}}_{\mathrm{A} }$) and inductor power switching mode B (${\mathrm{IPSM}}_{\mathrm{B}}$), respectively. ${\mathrm{IPSM}}_{\mathrm{A}}$ mode charges energy in inductor with the energizing phase (T_E) and delivers the energy to one of the outputs with the de-energizing phase (T_D), while ${\mathrm{IPSM}}_{\mathrm{B}}$ delivers energy to an output with the bypassing phase (T_B). If outputs within the range of a typical buck (${\mathrm{V}}_{\mathrm{O}} <{ \mathrm{V}}_{\mathrm{g}}{ \mathrm{or} \mathrm{V}}_{\mathrm{O}} \ll { \mathrm{V}}_{\mathrm{g}}$) or mild boost type (${\mathrm{V}}_{\mathrm{O}} >{ \mathrm{V}}_{\mathrm{g}}$) are operated in ${\mathrm{IPSM}}_{\mathrm{A}}$ and outputs within the range of the deep boost type (${\mathrm{V}}_{\mathrm{O}} \gg { \mathrm{V}}_{\mathrm{g}}$) are operated in ${\mathrm{IPSM}}_{\mathrm{B}}$, then the converter can support auto-buck-boost as in the control scheme in [19], assuming that regulation is achieved.

We denote the duty of ${\mathrm{IPSM}}_{\mathrm{A}}$ as ${\mathrm{D}}_{\mathrm{A}}$, and the duty of ${\mathrm{IPSM}}_{\mathrm{B}}$ as ${\mathrm{D}}_{\mathrm{B}}$. If we set ${\mathrm{D}}_{\mathrm{A}}$ to always be wider than ${\mathrm{D}}_{\mathrm{B}}$, then the transition of the operation mode from ${\mathrm{IPSM}}_{\mathrm{A}}$ to ${\mathrm{IPSM}}_{\mathrm{B}}$ for any output can increase the charge supplied to that output, without affecting the size of the time intervals for the next outputs. The relation of ${\mathrm{D}}_{\mathrm{A}}$ and ${\mathrm{D}}_{\mathrm{B}}$ can be expressed as follows:

$${\mathrm{D}}_{\mathrm{A}}={ \mathrm{D}}_{\mathrm{B}} + \mathsf{\beta }$$

(1)

Here, $\mathsf{\beta }$ is the difference in duty between the two modes and positive. Next, the relationships of the charges supplied to any output of ${\mathrm{IPSM}}_{\mathrm{A}}$ and ${\mathrm{IPSM}}_{\mathrm{B}}$ can be approximated as follows:

$${\mathrm{Q}}_{\mathrm{B}} \approx { \mathrm{Q}}_{\mathrm{A}} +{ \mathrm{T}}_{\mathrm{S}} \cdot \mathsf{\beta } \cdot { \mathrm{I}}_{\mathrm{i}}$$

(2)

Here, ${\mathrm{I}}_{\mathrm{i}}$ is the inductor current level at the start of an energizing phase. The derivation of Equation (2) is explained in Appendix A. Thus, the transition of the mode from ${\mathrm{IPSM}}_{\mathrm{A}}$ to ${\mathrm{IPSM}}_{\mathrm{B}}$ for any output can increase the charge supplied to that output by ${\mathrm{T}}_{\mathrm{S}}\cdot \mathsf{\beta }\cdot {\mathrm{I}}_{\mathrm{i}}$, and the increase in the duration of power delivery for the output does not reduce the size of the time intervals for the next output. In this study, we utilized the operation modes ${\mathrm{IPSM}}_{\mathrm{A}}$ and ${\mathrm{IPSM}}_{\mathrm{B}}$ with the adoption of β, to adjust the inductor current level and amount of charge supplied to the outputs.

The duty ratios of both modes ($D_A$ and $D_B$) were controlled so that the sum of the output errors becomes zero, as in the case of the EBC scheme of [14]. We set the duty difference $\beta$ of the two operation modes to a constant value for simplicity. For a mode transition from $IPS{M}_A$ to $IPS{M}_B$ to raise the inductor current, the condition of $\Delta I_{LA}<\Delta I_{LB}$ should be satisfied. The condition is expressed as follows:

$${\Delta \mathrm{I}}_{\mathrm{LB}} -{ \Delta \mathrm{I}}_{\mathrm{LA}}=\left(- \frac{{\mathrm{V}}_{\mathrm{O}}}{\mathrm{L}} \cdot \mathsf{\beta } + \frac{{\mathrm{V}}_{\mathrm{g}}}{\mathrm{L}} - \frac{{\mathrm{V}}_{\mathrm{g}}}{\mathrm{L}} \cdot { \mathrm{D}}_{\mathrm{A}}\right)\cdot { \mathrm{T}}_{\mathrm{S}} > 0$$

(3)

Here, we set the value of $\mathsf{\beta }$ to satisfy the condition in Equation (3).

Figure 4a–c shows the waveforms of the proposed EDRC scheme under a steady state, positive step change, and negative step change, respectively, where we presumed that output 1 is of the deep boost type. At the preceding edge of each switching period, the output errors were sampled. The output having the maximum output error was selected based on a comparison of the output errors; the output error was the voltage level resulting from subtracting the output voltage from the reference voltage. We denoted the output error as ${\mathrm{V}}_{\mathrm{error}}$.

In Figure 4a, we presumed that load requirement in output 2 is the lowest among all outputs; therefore, the slope of ${\mathrm{V}}_{\mathrm{error}2}$ is the lowest among all outputs while increasing. This makes output 2 the least selected. The error-based output selection also flexibly controls the frequency of selection of the outputs. In Figure 4b, the rise in the load requirement in output 2 at ${\mathrm{t}}_1$ increased the slope of ${\mathrm{V}}_{\mathrm{error}}$. It increased the frequency of the selection of output 2. In Figure 4c, the decline in the load requirement in output 2 at ${\mathrm{t}}_4$ decreased the frequency of selection of output 2. This flexible error-based output selection helped to mitigate load regulation.

The control circuit assigns the operation mode to the selected output at the preceding edge of the switching period. In the following, we will explain the criteria for assigning the operation modes.

The proposed converter should raise the inductor current level or widen the power delivery duration in response to a rise in the load requirement. A rise in the load requirement results in an increase in the sum of the output errors. Therefore, the proposed converter monitors the sum of the output errors to detect variations in the load requirement. We denoted the sum of the output errors by ${\mathrm{V}}_{\mathrm{error}\_\mathrm{sum}}$. We adopted two reference voltage levels, ${\mathrm{V}}_{\mathrm{ref}+}$ and ${\mathrm{V}}_{\mathrm{ref}-}$, for detecting the increase or decrease in ${\mathrm{V}}_{\mathrm{error}\_\mathrm{sum}}$. The reference voltage levels, ${\mathrm{V}}_{\mathrm{ref}+}$ and ${\mathrm{V}}_{\mathrm{ref}-}$, are voltage levels of the same magnitude but different signs, as shown in Figure 4. ${\mathrm{V}}_{\mathrm{error}\_\mathrm{sum}}$ was sampled at the preceding edge of the switching period, and the control circuit assigns an operation mode based on a comparison of ${\mathrm{V}}_{\mathrm{error}\_\mathrm{sum}}$ with ${\mathrm{V}}_{\mathrm{ref}+}$ and ${\mathrm{V}}_{\mathrm{ref}-}$.

If the sampled $V_{error\_sum}$ is sensed to be smaller than $V_{ref+}$ but greater than $V_{ref-}$, that is $V_{ref+} > V_{error\_sum} > V_{ref-}$, then the average inductor current level should be maintained. The control circuit assigns $IPS{M}_A$ to an output within the range of the typical buck type ($V_O < V_g or V_O \ll V_g$) or mild boost type ($V_O > V_g$). The combination of $T_E$ and $T_D$ in $IPS{M}_A$ allows for auto-buck-boost regulation to be achieved [24]. The control circuit assigns $IPS{M}_B$ to an output within the range of the deep boost type ($V_O \gg V_g$), as in [19]. We will cover the criteria for determining the range of the deep boost type in the next section. In Figure 4a, all sampled $V_{error\_sum}$ values were sensed to be $V_{ref+} > V_{error\_sum} > V_{ref-}$. Therefore, outputs 2 and 3 were operated in $IPS{M}_A$, and output 1 was operated in $IPS{M}_B$.

Provided that the sampled V_(error_sum) was greater than V_(ref+), i.e., V_(error_sum) > V_(ref+), the control circuit assigned IPSM_B, to increase both the inductor current level and power delivery duration. In Figure 4b, the rise in the load requirement in output 2 at t_1 increased the slope of V_(error_sum), raising the sampled V_(error_sum) above V_(ref+) between t_2 and t_3. Accordingly, all selected outputs were operated in IPSM_B between t_2 and t_3 as indicated by the N2 mark, whereas IPSM_B (indicated by the N1 mark) was assigned for supplying the deep boost output. The operation mode of outputs 2 and 3 was switched from IPSM_A to IPSM_B. The mode transition instantaneously increased the inductor current level. In particular, IPSM_B of buck output 3 increased the inductor current level for the entire switching period. This instantaneous adjustment in the inductor current level led to an improvement in the drivable load current and cross-regulation. However, the instantaneously increased inductor current level might cause the output ripple voltage to rise instantly. The simulation and experimental results will show how the output ripple voltage was increased.

If the sampled ${\mathrm{V}}_{\mathrm{error}\_\mathrm{sum}}$ is sensed to be lower than ${\mathrm{V}}_{\mathrm{ref}-}$, i.e., ${\mathrm{V}}_{\mathrm{error}\_\mathrm{sum}} <{ \mathrm{V}}_{\mathrm{ref}-}$, then the control circuit assigns ${\mathrm{IPSM}}_{\mathrm{A}}$, to decrease both the inductor current level and power delivery duration. In Figure 4c, the decrease in the load requirement of output 2 at ${\mathrm{t}}_4$ reduced the sampled ${\mathrm{V}}_{\mathrm{error}\_\mathrm{sum}}$ below ${\mathrm{V}}_{\mathrm{ref}-}$ after ${\mathrm{t}}_5$. Thus, all selected outputs were operated in ${\mathrm{IPSM}}_{\mathrm{A}}$ after ${\mathrm{t}}_5$ until the sampled ${\mathrm{V}}_{\mathrm{error}\_\mathrm{sum}}$ was increased over ${\mathrm{V}}_{\mathrm{ref}-}$. The mode transition from ${\mathrm{IPSM}}_{\mathrm{B}}$ to ${\mathrm{IPSM}}_{\mathrm{A}}$ of output 1 led to a reduction in the inductor current level.

When all outputs are fully supplied, the selection of any output forces that output to be supplied with more load current than it demands, wasting power and increasing the output ripple voltage. Therefore, in such cases, the converter does not select any output. We denoted this technique as "no demand no selection (NDNS). We adopted the reference voltage $V_{ref\_NS}$ for determining whether all outputs are sufficiently supplied, as shown in Figure 4c. If the control circuit senses that all sampled output errors at the preceding edge of a switching period are lower than $V_{ref\_NS}$, then it freewheels the inductor current without selecting outputs, as indicated by the N3 mark.

2.2. Condition Setting of Deep Boost

We set the range of the deep boost based on a comparison of the input voltage and scaled-down output voltage, as follows:

$${\mathrm{V}}_{\mathrm{g}} < \mathsf{\alpha } \cdot { \mathrm{V}}_{\mathrm{O}}$$

(4)

where $\mathsf{\alpha }$ is a constant scalar factor. We will provide a guideline for choosing $\mathsf{\alpha }$ in this section. If ${\mathrm{V}}_{\mathrm{g}}$ increases from below $\mathsf{\alpha }\cdot {\mathrm{V}}_{\mathrm{O}}$ to above $\mathsf{\alpha }\cdot {\mathrm{V}}_{\mathrm{O}}$, then the operation mode of the output is switched from ${\mathrm{IPSM}}_{\mathrm{B}}$ to ${\mathrm{IPSM}}_{\mathrm{A}}$, assuming that the sampled ${\mathrm{V}}_{\mathrm{error}\_\mathrm{sum}}$ is sensed to be between ${\mathrm{V}}_{\mathrm{ref}+}$ and ${\mathrm{V}}_{\mathrm{ref}-}$. However, the inductor current changes of ${\mathrm{IPSM}}_{\mathrm{A}}$ and ${\mathrm{IPSM}}_{\mathrm{B}}$ for one switching period, i.e., $\Delta {\mathrm{I}}_{\mathrm{LA}}$ and $\Delta {\mathrm{I}}_{\mathrm{LB}}$, are different. Consequently, a mode transition may cause a change in the inductor current level, resulting in an overshoot of the output voltages.

Figure 5 shows a simulated average overshoot voltage waveform corresponding to $\mathsf{\alpha }$ in the proposed converter, in a case where increasing ${\mathrm{V}}_{\mathrm{g}}$ changes the operation mode of output 2. The constant scalar factor $\mathsf{\alpha }$ is mathematically in the range between 0 and 1. When $\mathsf{\alpha }$ is 0.5, the boundary level for determining the operation mode, ${\mathrm{V}}_{\mathrm{g}}= \mathsf{\alpha }\cdot {\mathrm{V}}_{\mathrm{O}}$, is 1.5 V. In the simulation, 1.5 V of ${\mathrm{V}}_{\mathrm{g}}$ was too small to achieve regulation of the output voltage. Therefore, we simulated the average overshoot voltage by varying $\mathsf{\alpha }$ in the range between 0.6 and 1. Within this range, an average overshoot voltage below 60 mV was guaranteed. Thus, a designer can set $\mathsf{\alpha }$ to ensure that the average overshoot voltage does not exceed a specified value. We selected $\mathsf{\alpha }$ as 0.7, as this value produced the lowest average overshoot voltage for the results in Figure 5.

2.3. Architecture of the Proposed EDRC

Figure 6 shows a block diagram of the proposed EDRC scheme. The analog subtractor comprises of one op-amp and four resistors, and produces the output error voltage. In the maximum output error selector (MOES) block, comparator circuits compare the output errors with each other, and the MOES block selects the output having the maximum output error. An analog adder (comprising one op-amp and four resistors) aggregates the output error voltages to produce V (error_sum). Comparator circuits compare each output error voltage with V (ref_NS) to sense when all outputs are fully supplied. The EDRC operates in a DCM mode when the inductor current becomes zero during the power delivery duration. The zero current detection block detects when the inductor current becomes zero, and is implemented by adopting the method in [1,25]. The IPSM block determines the operation mode of the output selected by the MOES block. The truth table for the IPSM block is summarized in

Table 1. Truth table of output of inductor power switching mode (IPSM) block.

Conditions Based on Comparison of Magnitude of Inputs		Output
$V_{ref+}>V_{error\_sum}>V_{ref-}$	${\mathrm{V}}_{\mathrm{g}}> \mathsf{\alpha }\cdot {\mathrm{V}}_{\mathrm{O}\left(\mathrm{i}\right)}$	0 (${\mathrm{IPSM}}_{\mathrm{A}}$)
	${\mathrm{V}}_{\mathrm{g}}< \mathsf{\alpha }\cdot {\mathrm{V}}_{\mathrm{O}\left(\mathrm{i}\right)}$	1 (${\mathrm{IPSM}}_{\mathrm{B}}$)
${\mathrm{V}}_{\mathrm{error}\_\mathrm{sum}}>{ \mathrm{V}}_{\mathrm{ref}+}$	-	1 (${\mathrm{IPSM}}_{\mathrm{B}}$)
${\mathrm{V}}_{\mathrm{error}\_\mathrm{sum}}<{ \mathrm{V}}_{\mathrm{ref}-}$	-	0 (${\mathrm{IPSM}}_{\mathrm{A}}$)

.

The combination of ${\mathrm{T}}_{\mathrm{E}}$ and ${\mathrm{T}}_{\mathrm{D}}$ allows for the control-to-output transfer function of ${\mathrm{IPSM}}_{\mathrm{A}}$ to have right half plane (RHP) zero [26,27,28,29]. The RHP zero causes a phase lag, and results in the phase margin being negative [26,27,28,29]. To make the phase margin positive, multiple works in [29,30] employed a Type III compensation network. Therefore, we employed a Type III compensation network to compensate for ${\mathrm{V}}_{\mathrm{error}\_\mathrm{sum}}$ as well, as shown in the duty timing controller (DTC) block.

In the DTC block, the comparator circuit produced a pulse width modulation (PWM) signal for ${\mathrm{IPSM}}_{\mathrm{A}}$, based on receiving the compensated ${\mathrm{V}}_{\mathrm{error}\_\mathrm{sum}}$ and ramp signal ${\mathrm{V}}_{\mathrm{rampA}}$. Likewise, another comparator circuit produced a PWM signal for ${\mathrm{IPSM}}_{\mathrm{B}},$ based on receiving the compensated ${\mathrm{V}}_{\mathrm{error}\_\mathrm{sum}}$ and ramp signal ${\mathrm{V}}_{\mathrm{rampB}}$ (which was delayed by $\mathsf{\beta }\cdot {\mathrm{T}}_{\mathrm{S}}$ as compared to ${\mathrm{V}}_{\mathrm{rampA}}$). The mux block selected one of two PWM signals for receiving the output signal of the IPSM block.

The control logic and gate driver block stored the inputs at the rising edge of CLK; the CLK signal is a clock signal whose period is ${\mathrm{T}}_{\mathrm{S}}$. The rising edge of the CLK signal and the falling edge of ${\mathrm{V}}_{\mathrm{rampA}}$ were synchronized.

3. Simulation Results

In this section, we used MATLAB to simulate a version of the proposed converter with three outputs, to verify its effectiveness. The simulation environment includes $V_g$ = 2 V, $V_{out1}$ = 3.3 V, $V_{out2}$ = 2.5 V, $V_{out3}$ = 1.5 V, $f_S$ = 781 kHz, L = 5.8 $\mu$H, $C_{out1}$ = $C_{out2}$ = $C_{out3}$ = 10 $\mu$F, $\alpha$ = 0.7, and $\beta$ = 0.19.

Figure 7 shows simulated waveforms of the output voltages of the proposed EDRC scheme, in a case where the sampled $V_{error\_sum}$ was sensed to be within $V_{ref+} > V_{error\_sum} > V_{ref-}$. The outputs were randomly selected. Output 3 was operated in $IPS{M}_B$ and outputs 1 and 2 were operated in $IPS{M}_A$, according to a comparison of $V_g$ with $\alpha \cdot V_O$. The pulse width in $S_{O3}$ was wider than those of the remaining outputs; this determined the operation modes of the outputs. The load current of output 3 was 330 mA, i.e., the largest among all outputs. Therefore, output 3 seems to be the most frequently selected. However, the wider power delivery duration of $IPS{M}_B$ allowed for more power to be received in one switching period than in the cases of outputs 1 and 2. Therefore, output 3 was the least selected output from among all outputs, even though output 3 had the largest load current among all outputs.

Figure 8a, b shows the simulated transient waveforms of the proposed EDRC scheme, where we measured the maximum driving current, load regulation, and cross-regulation. We compared the measurements with the performances measured in the SIMO auto-buck-boost DC–DC converter of [19], based on the PCCM scheme. Figure 8c shows the simulated transient waveforms of the proposed EDRC scheme, but without the NDNS technique. We show the effectiveness of the NDNS technique through a comparison of Figure 8b,c.

In Figure 8a, 0.372 mV/mA and 0.012 mV/mA were the simulated values of load regulation and cross-regulation in response to a driving current of 250 mA, respectively. In Figure 8b, 0.18 mV/mA and 0.01 mV/mA were the simulated values of load regulation and cross-regulation, respectively. The work in [19] achieves 2 mV/mA and 0.67 mV/mA of load regulation and cross-regulation in response to a maximum driving current of 110 mA, respectively. In reality, the load requirement varies, in units of mA/ms. To show the change in the inductor current level and increase in the output ripple voltage, Figure 8 shows the results of simulating extreme cases, in which an increase or decrease in a load current of 250 mA occurred in 1 ns. Nevertheless, the performances of the load regulation, cross-regulation, and maximum driving current as simulated in Figure 8 are improved over those in [19].

The proposed EDRC scheme instantaneously adjusted the inductor current level in response to a change in the load requirement. In Figure 8a, it allowed the inductor current to rise from 0.97 A to 1.3 A with only five cycles, in response to an increase in load current of 250 mA. The instantaneous adjustment of the inductor current level by the proposed EDRC scheme led to improvements in the performances of the load regulation, cross-regulation, and output driving capability.

In Figure 8c, the load and cross-regulations were measured at 0.46 mV/mA and 0.164 mV/mA, respectively. The proposed EDRC scheme without the NDNS technique achieved worse performances in regards to load regulation and cross-regulation than those in Figure 8b, although it achieves better performances than those of [19]. The selection of an output that does not require a load current increased the output ripple voltage (as shown by the boxes with the dashed lines), thereby aggravating load regulation and cross-regulation.

The instantaneous adjustment in the inductor current level can abruptly increase the output ripple voltage. We assumed a worst-case scenario where the output ripple voltage increases in the proposed EDRC scheme, and show the guaranteed maximum increase in the output ripple voltage from the simulation. The worst-case scenario is that the average inductor current level is elevated, and the operation mode is switched from $IPS{M}_A$ to $IPS{M}_B$. We modeled the increase in the output ripple voltage of the scenario in Appendix A, as expressed in Equation (A5). We plotted Equation (A5) regarding $D_A$ in Figure 9. Figure 9 shows that the increase in output ripple voltage was guaranteed to be less than 65 mV.

Figure 10 shows the waveforms of the output voltages and inductor current where $V_g$ was increased from 1.7 to 3.4 V and decreased from 1.7 to 3.4 V at a slope of 0.4 V/ms. The sections of the graph in Figure 10a that are marked by “(b)”, “(c)”, “(d)”, and “(e)” (4 $\mu$s in width) were enlarged in Figure 10b–e, respectively. In these sections, the sampled $V_{error\_sum}$ was sensed to be within $V_{ref+} > V_{error\_sum} > V_{ref-}$. In Figure 10b, the outputs 3, 2, and 1 operated in $IPS{M}_B$, $IPS{M}_B$, and $IPS{M}_A$, respectively, depending on the relationship between $V_g$ and $V_{Oi}\cdot \alpha$. Likewise, in Figure 10c, the outputs 3, 2, and 1 operated in $IPS{M}_B$, $IPS{M}_A$, and $IPS{M}_A$, respectively, and in Figure 10d,e all outputs operated in $IPS{M}_A$. The proposed EDRC scheme maintained constant output voltages by switching the operation mode seamlessly, according to the variation of $V_g$.

4. Experimental Results

We implemented the power stage of the proposed converter and analog part of the control circuit with discrete components, and the digital part of the control circuit with field-programmable gate arrays. Figure 11 shows the photography of the implemented converter on the PCB board. The specifications and component values for the proposed converter are summarized in

Table 2. Specifications and component values of the proposed converter.

Number of Channels	3
Vg	1~3.5 V (2 V nominal)
Vout1, Vout2, and Vout3	1.5 V, 2.5 V, 3.3 V
Switching frequency	195 kHz
L(DCR)	5.8 $\mathsf{\mu }\mathrm{H}$ (5 m$\mathsf{\Omega }$)
Cout1, Cout2, and Cout3(ESR)	39 $\mathsf{\mu }$F (15 m$\mathsf{\Omega }$)
$\alpha$	0.7
$\beta$	19%

. Figure 12 shows the measured waveforms of the output voltages and gate-drive signal on switch ${\mathrm{S}}_{\mathrm{E}}$ in a case where the sampled ${\mathrm{V}}_{\mathrm{error}\_\mathrm{sum}}$ was sensed to be between ${\mathrm{V}}_{\mathrm{ref}+}$ and ${\mathrm{V}}_{\mathrm{ref}-}$. The output voltage of each output rose, in random order. Outputs 3, 2, and 1 operated in ${\mathrm{IPSM}}_{\mathrm{B}}$, ${\mathrm{IPSM}}_{\mathrm{A}}$, and ${\mathrm{IPSM}}_{\mathrm{A}}$, respectively, depending on the relationship between ${\mathrm{V}}_{\mathrm{g}}$ and ${\mathrm{V}}_{\mathrm{Oi}}\cdot \mathsf{\alpha }$. The operation mode of each output can be confirmed by the pulse width of the gate-drive signal applied to switch ${\mathrm{S}}_{\mathrm{E}}$. In the waveform of the gate-drive signal, two types of pulse widths are shown, “wider width” and “narrower width”. The “wider width” pulse represents ${\mathrm{IPSM}}_{\mathrm{A}}$, and the “narrower width” pulse represents ${\mathrm{IPSM}}_{\mathrm{B}}$. This waveform also shows that one of the output voltages increased randomly while the duty was low in the steady state.

Figure 13 shows the measured transient waveforms. In Figure 13a,b, the load current of output 3 was changed from 33 to 220 mA and from 220 to 33 mA, respectively, where the load currents in the cases of outputs 2 and 1 were ${\mathrm{I}}_{\mathrm{out}2}$ = 250 mA, and ${\mathrm{I}}_{\mathrm{out}1}$ = 220 mA, respectively. Figure 13c,d shows the load current change in output 2 from 7 to 284 mA and from 284 to 7 mA, respectively, where ${\mathrm{I}}_{\mathrm{out}1}$ = 220 mA, and ${\mathrm{I}}_{\mathrm{out}3}$ = 150 mA. Figure 13e, f shows the load current change in output 1 from 5 to 205 mA and from 205 to 5 mA, respectively, where ${\mathrm{I}}_{\mathrm{out}1}$ = 220 mA, and ${\mathrm{I}}_{\mathrm{out}2}$ = 250 mA. The load and cross-regulations were measured as 0.27 mV/mA and 0.042 mV/mA, respectively, which were based on the calculation of measurement in Figure 13c.

In Figure 13c, the output ripple voltages of outputs 1, 2, and 3 increased from 55 to 76 mV, from 42 to 102 mV, and from 53 to 70 mV, respectively, after the occurrence of the transient load. At 0.1 W of total output power, 85.5% efficiency was achieved. At 1.28 W of the total output power, the maximum efficiency of 91.2% was achieved, as shown in Figure 14. To confirm the improvement in efficiency when employing the NDNS technique, we also measured the efficiency when not employing the NDNS technique, as shown by the dashed line in Figure 14. The adoption of the NDNS technique achieved an improvement in efficiency of 1.3% at 0.1 W.

5. Discussions

The operation of the proposed converter was verified in the simulation and experimental results sections. In this section, we discussed the performance improvements and techniques that lead to the advantages over the techniques in previous articles.

Table 3. Comparison of performance with previous publications.

	Ref [14]	Ref [18]	Ref [19]	Ref [20]	Present Work
Published Year	2015	2016	2016	2020	-
Implementation	Discrete component	0.35$\mu$m CMOS	0.35$\mu$m CMOS	0.35$\mu$m CMOS	Discrete component
Input voltage (V)	4.8	5	1.85–2.9	2.5	1.7– 3.4
Number of outputs	2	10	4	4	3
Output voltages (V)	3.3, 1.2	3.3 (3), 2.8 (2), 2.5 (2), 1.8 (3)	3.3, 3, 2.5, 1.8	3.4, 3, 2.5, 1.8	3.3, 2.5, 1.5
Switching frequency (MHz)	0.1	0.7	0.25	0.75~1	0.195
Peak efficiency (%)	78	88.7	89	89.5	91.2
Light-load efficiency	77%@0.11 W	83.5%@0.14 W	7%@0.2 W	83%@0.15W	85.5%@0.1 W
Auto-buck-boost	No	No	Yes	YES	Yes
Output driving capability (mA)	100	185	110	300	277
Load-regulation (mV/mA)	1	0.17	2	0.56	0.27
Cross-regulation (mV/mA)	0.5	0.1	0.67	0.05	0.042

compares the performances between the previous and proposed works. In the simulation results, we described the structural advantage of the proposed instantaneous adjustment of the inductor current level in regards to the output driving capability, load regulation, and cross-regulation. The proposed converter achieved 0.042 mV/mA of cross-regulation and 0.27 mV/mA of load regulation in response to a change in load current of 277 mA. Table 3 shows the performance improvements compared to those of the previous works, except for the load regulation of the EBC control in [14].

The EBC control selects outputs based on output errors to improve efficiency in light loads, and employs an add-on linear regulator to alleviate cross-regulation. We introduced a technique for mitigating cross-regulation by adjusting the inductor current level without a linear regulator, and extend the output selection technique based on output errors to an auto-buck-boost topology.

We introduced the NDNS technique. As shown in Figure 8c in the three dashed-line boxes, the power of 0.45 W was over-supplied. The NDNS technique can save the wasted power. Figure 14 shows that the NDNS technique resulted in an increase of efficiency. An efficiency of 85.5% in the case of the proposed converter was achieved at 0.1 W of the total output power, an improvement over the previous works.

In addition, in our simulation results, we have shown how the NDNS technique could improve performances in the cross-regulation, load regulation, and output ripple voltage. However, an instantaneous adjustment in the inductor current level may cause an abrupt increase in the output ripple voltage. We modeled the increase in the output ripple voltage of the proposed converter in the simulation section. The simulation results show that the increase in output ripple voltage was guaranteed to be less than 65 mV. An increase in the switching frequency can reduce the increase in the output ripple voltage.

To reduce the average inductor current level, the work in [20] allows for the operation modes of outputs within the range of typical buck or mild boost types to include a bypassing cycle. In our scheme, it would be possible to lower the average inductor current level if ${\mathrm{IPSM}}_{\mathrm{A}}$ were to include a bypassing cycle. However, we allowed ${\mathrm{IPSM}}_{\mathrm{A}}$ to consist of only energizing and de-energizing cycles, to reduce the circuit complexity and to instantaneously adjust the inductor current level.

We employed filtering capacitors with a capacitance larger than that of the quoted previous publications in Table 3, as the discrete components used in this study limited the speed of the converter. However, we expected that on-chip fabrication of the proposed converter would increase the switching frequency, and thereby enable the use of 10$\mathsf{\mu }$F capacitors. The operation of the proposed converter with 10 $\mathsf{\mu }$F filtering capacitors was verified through simulation.

6. Conclusions

In this study, we proposed a SIMO auto-buck-boost DC–DC converter with error-driving randomized control. We extended an output selection technique based on output errors to an auto-buck-boost topology, and introduced a technique for instantaneously adjusting the inductor current level. In addition, we introduced the NDNS technique, which does not select any output when the loads are sufficiently supplied. The proposed EDRC scheme achieves performance improvements in efficiency in regards to light loads, cross-regulation, and output driving capability in SIMO auto-buck-boost DC–DC converters.