A Novel Power Decoupling Control Method to Eliminate the Double Line Frequency Ripple of Two Stage Single-Phase DC-AC Power Conversion Systems

Abstract

In two-stage single-phase inverters, inherent double line frequency ripple is present at both the input and output of the front-end converter. Generally, large electrolytic capacitors are used to eliminate this double line frequency ripple. It is well known that low frequency ripple shortens the lifespan of capacitors. Hence, the system reliability can get worse. In order to eliminate the double line frequency ripple, additional hardware combined with an energy storage device is required in most of the methods developed so far. In this paper, a novel power-decoupling control method is proposed to eliminate the double line frequency ripple at the front-end converter of two-stage single phase DC/AC power conversion systems. The proposed control algorithm is composed of two loops, a ripple compensation loop and an average voltage control loop, and no extra hardware is required. Since the proposed method does not require information from the phase-locked-loop (PLL) of the inverter, it is independent of inverter control. In order to verify the validity and feasibility of the proposed algorithm a 5 kW Dual Active Bridge (DAB) DC/DC converter and a single-phase inverter are implemented. The effectiveness of the proposed method is verified through the simulation and experimental results.

1. Introduction

Two-stage DC/AC power conversion systems are widely used since they provide galvanic isolation between the input and output, and a flexible voltage gain for the rear-end inverter. By boosting the low voltage of the source to a suitable DC voltage level, front-end converters play an important role in providing a suitable input DC voltage for the rear-end Voltage Source Inverters (VSIs) to produce an AC voltage [1].

For two-stage single-phase DC/AC systems, the Dual Active Bridge (DAB) converter has attracted a lot of research interests as a front-end converter due to its high-power density, galvanic isolation, and bidirectional power flow. The DAB converter is an efficient topology for bidirectional power applications due to its inherent soft switching capability i.e., ZVS. [2,3].

Typically, a two-stage single phase DC-AC converter system is comprised of a first stage DC-DC converter with galvanic isolation and a second stage single-phase DC-AC inverter [4]. It is well known that the instantaneous input power of the two-stage single-phase inverter pulsates at the double line frequency, which results in double line frequency ripples at both ends of the front-end dc-dc converter. Therefore, large electrolytic capacitors are used at the input to eliminate the double line frequency ripple [5] and to maintain a constant DC link voltage by balancing the power mismatch between the front-end and rear-end converters. Although electrolytic capacitors have higher capacitance to volume ratio than those of other types, their life spans are shorter than those of the other components used in converters. Therefore, the reliability of a system depends heavily on it. It is well known that the electrolytic capacitor is about thirty times less reliable than film capacitors with the help under similar conditions [6,7]. Since low frequency ripple current accelerates the aging of a capacitor, it should be reduced by control algorithms such as Power Decoupling Techniques (PDTs). The main idea of PDTs is to inject the ripple power to an energy storage device such as a capacitor with the help of additional circuits [8] as shown in Figure 1. However, this cannot be achieved without an increase in the volume, weight and cost of the system.

In order to diminish low frequency ripple current and avoid using massive electrolytic capacitors, a method with a DC active filter has been proposed in [9]. In this method, elimination of input ripple current is achieved by using a dc chopper to inject ripple current. A drawback of this approach is that it requires an auxiliary DC chopper, which results in a massive volume and a higher cost of the system [10]. Another ripple current reduction method using a current-loop control for three-phase DC-DC converters can be found in [11]. However, it requires a large capacitor as an energy buffer at the output of the converter since the ripple at the output is not controlled.

Another method proposed in [12] shows that a DC active filter can be implemented with no extra switching devices. The decoupling capacitor is connected at the center tap of the isolation transformer, and common mode voltage is used to decouple the pulsating power. However, the current rating of the transformer is significantly increased, which increases the losses. A ripple rejection technique utilizing current control was proposed in [13]. However, it is not possible to reduce the DC-link capacitors. Moreover, since it uses an electrolytic capacitor for the DC-link, the reliability of system is not sufficiently increased. Three port power decoupling systems were proposed in [14,15,16]. However, these methods require a three-winding transformer with additional circuits. In addition, the control is complex. Hence, the cost, weight, size and complexity of the systems are increased.

A DAB converter is often employed as a front-end DC-DC converter of two stage DC/AC power conversion systems. There are two categories of DAB converters: one is the current-fed DAB and the other is the voltage-fed DAB. In the current-fed DAB, an inductor is required at the input of the DAB to control the current, which increases the volume and cost of the converter. In terms of the component count, the voltage-fed DAB converter is better than the current-fed DAB converter because it does not require a large inductor. However, it is a challenge to use a voltage fed DAB for the power decoupling control since current control is essential in the conventional methods in [17,18,19]. Therefore, most double line frequency component elimination methods have been developed based on the current-fed topology and ripple current control. In this paper, a novel voltage control based double line frequency ripple elimination method is proposed for two stage DC/AC power converters as shown in Figure 2. The double line frequency ripple is extracted by the Band Pass Filter (BPF) and it is compensated by the PI controller. The output of the DC/DC converter is also regulated by the PI controller. However, it is loosely controlled to allow the double line frequency ripple (i.e., the 120 Hz component in this case) to oscillate around the desired output voltage. Since the proposed method does not require phase information of the double line frequency ripple, there is no need to obtain it from the Phase Locked Loop (PLL) of the inverter. Therefore, the double line frequency ripple elimination can be performed without depending on the inverter control. The capacitance values of the input decoupling capacitor and the output DC link capacitor can be significantly reduced by the proposed method.

This paper is organized as follows. In Section 2, an overview of the principle of double line frequency generation and a summary of the proposed control method to eliminate the double line frequency ripple are presented. In Section 3, a simplified model of a DAB is presented to obtain the control-to-output and control-to-input transfer functions for the design of the ripple elimination control loop and the average DC-link voltage control. In Section 4, the design of the proposed control method for double line frequency ripple elimination is discussed in detail. In Section 5, simulation and experimental results are presented along with a comparison between the proposed and conventional ripple elimination methods in terms of reductions in the capacitance, capacitor volume and double line frequency ripple. Finally, some conclusions are given in Section 6.

2. Double Line Frequency Ripple

As mentioned earlier, a typical two-stage single phase DC-AC power conversion system is composed of a DC-DC converter and a single-phase VSI. The input current and the voltage of the VSI are DCs. However, they contain high frequency switching noises and a fundamental low frequency component. The instantaneous output power of the two-stage single-phase inverter pulsates at twice the frequency of the output voltage, which results in a second harmonic current at the input of the single-phase inverter. This harmonic current propagates back into the front-end dc–dc converter and the input source. Therefore, it causes higher current stresses for the power switches and produces additional power losses. It is well known that it may shorten the life of input dc voltage sources such as batteries or fuel cells and degrade the power conversion efficiency.

The principle for the second harmonic generated by the single-phase inverter can be derived as follows. In a single-phase VSI system, the current injected into the AC grid I(t) and the grid AC voltage U(t) can be represented by Equations (1) and (2), respectively.

$$U(t)=U_{m}sin\left({\omega }_{o}t\right)\hspace{0.17em}$$

(1)

$$I(t)=I_{m}sin\left({\omega }_{o}t+\varphi \right)$$

(2)

where, ω_o represents the AC line frequency, and U_m and I_m are the amplitude of the output voltage and current, respectively. ϕ is the phase between the current and the voltage. The instantaneous input power P_t can be calculated by Equation (3).

$$P_t=\frac{1}{2}{U}_m{I}_m+\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\frac{1}{2}{U}_m{I}_m\cos (2{\omega }_{o}t+\varphi )\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}$$

(3)

It can be easily found from Equation (3) that the instantaneous power at the input is composed of two terms, an average DC power and a pulsating power that oscillates at twice the line frequency. A straightforward way to mitigate the ripple power at the DC source side is to use a bulky capacitor. The capacitors can be placed with the inverter stage or connected in parallel with the DC source. However, since the required capacitance is relatively large, many bulky electrolytic capacitors should be connected in parallel. The sizing of the required capacitance value to suppress the double line frequency ripple can be performed as follows. During a half-line cycle, the energy being charged to or discharged from the decoupling capacitor can be calculated by Equation (4).

$$E_{CD}=\frac{1}{2}\hspace{0.17em}\left[U^2{}_{\mathrm{DC}\_\max }-U^2{}_{\mathrm{DC}\_\min }\right]$$

(4)

where U_{DC_max} and U_{DC_min} are the maximum and minimum voltages across the decoupling capacitor, respectively. Therefore, the required decoupling capacitance can be calculated as Equation (5) [20].

$$\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}{C}_D=\left(\frac{P_{dc}}{2\pi f_{grid}{U}_{dc}\Delta u}\right)$$

(5)

where f_grid is the line frequency, U_dc is the average DC voltage across the decoupling capacitor C_D, and Δu is the allowable ripple voltage across C_D. It is suggested from Equation (5) that the decoupling capacitor should be placed at the high voltage side rather than placing it at the low voltage side so the size of the capacitor can be reduced [21]. In order to avoid using a bulky decoupling capacitor to suppress the double line frequency ripple, power decoupling-based control is preferred to buffer the ripple power in two-stage inverters. Since the amplitude of the double line frequency ripple current is determined by the output impedance of the front-end dc–dc converter and the impedance of the dc-bus capacitor at double line frequency, it can be reduced by increasing its output impedance at double line frequency with suitable control schemes.

In this paper, a novel voltage control based double line frequency ripple elimination method is proposed for two stage DC/AC power conversion systems as shown in Figure 2. The double line frequency ripple is extracted by the BPF and it is compensated by the PI controller. The output of the DC/DC converter is also regulated by the PI controller. However, it is loosely controlled to allow the double line frequency ripple (i.e., the 120 Hz component in this case) to oscillate around the desired value of the output. Thanks to the ripple reduction capability of the proposed method, a decoupling capacitor with an even lower capacitance value can be employed at both ends of the front-end DC-DC converter.

3. Simplified Modeling of DAB for Double Line Frequency Ripple Elimination

In this section, simplified modeling of the DAB for power decoupling control is introduced for the control of a converter as well as the elimination of double line frequency ripple. The DAB is a bidirectional DC-DC converter consisting of eight active switches, a high frequency transformer, a leakage inductor and DC-link capacitors as illustrated in Figure 2. Where V_DC and V_{DC_Link} are the input DC source voltage and DC-link voltage of the VSI, respectively. L_lk is the leakage inductance of the transformer, and S_1–8 are the power semiconductor switches in the DAB converter.

As shown in Figure 3, S_1,4 and S_2,3 are the control gate signals for the primary switch S_pri, and S_5,8 and S_6,7 are the control gate signals for the secondary bridge S_sec. Here, power is delivered from the low voltage side bridge to the high voltage side bridge. When the phase shift δ of the secondary bridge signal is positive +δ, the power is delivered from the primary bridge to the secondary bridge. When it is negative −δ, the power flow is reversed. Figure 3 also shows the Transformer leakage current and voltage waveforms at a given phase shift. By using Kirchhoff’s voltage equation, the slope of the inductor current can be represented by Equation (6).

$$\hspace{0.17em}\frac{d{i}_{lk}}{dt}=\left(\frac{V_{pri}(t)-V_{\sec }(t)}{L_k}\right)$$

(6)

A half switching cycle can be divided into two intervals, 0 < θ < δ and δ < θ < π. By solving the above equation for each interval, Equations (7) and (8) can be obtained.

$$V_{\mathrm{DC}}+\frac{V_{\mathrm{DC}\_\mathrm{link}}}{n}=\left(\frac{L_k(I_1+I_2)}{dT}\right)for\hspace{1em}0<t<dT$$

(7)

$$V_{\mathrm{DC}}-\frac{V_{\mathrm{DC}\_\mathrm{link}}}{n}=\left(\frac{L_k(I_1+I_2)}{(1-d)T}\right)\hspace{0.17em}for\hspace{1em}dT<t<T\hspace{1em}$$

(8)

where ‘n’ is the turns-ratio of the transformer, T is a half-cycle of a period, I₁ and I₂ are the inductor currents, and δ/π is the duty d obtained by the phase shift between two bridges.

By averaging Equations (7) and (8), as shown in [22], the average output current of the converter can be represented by Equation (9).

$$I_{P2}=\left[\frac{\left(1-\left|d\right|\right)dT{V}_{\mathrm{DC}}}{n{L}_k}\right]$$

(9)

The output power of the DAB converter can be derived using the average current in Equation (9), as shown in Equation (10).

$$P=V_{\mathrm{DC}\_\mathrm{link}}{I}_{P2}=\left(\frac{\left(1-\left|d\right|\right)dT{V}_{\mathrm{DC}}{V}_{\mathrm{DC}\_\mathrm{link}}}{n{L}_k}\right)$$

(10)

Equation (10) explains the relationship between the power transferred to the output as a function of the duty cycle. Where d denotes the phase shift (δ/π). The maximum power flow occurs at d = ±0.5, as shown in Figure 4. Although the converter can operate with |d| > 0.5 (the dotted lines in Figure 4), the phase shift is usually bounded when |d| ≤ 0.5 to avoid excessive reactive power. The leakage inductance value for the optimal power transfer can be calculated by Equation (11).

$$L_k=\left(\frac{(1-d)d{V}_{\mathrm{DC}}{V}_{\mathrm{DC}\_\mathrm{link}}}{nP\max }\right)$$

(11)

For high-performance control of the converter, to eliminate the low frequency component, a small signal model of the converter needs to be derived first. In order to obtain a small signal average model of the DAB converter, an equivalent circuit of the converter needs to be derived, as shown in Figure 5. Since the DAB converter can be modeled as a controlled DC current source, its equivalent circuit model can be represented by a controlled DC current source and a capacitor connected in parallel with the load.

By using Equation (9), the output current of the DAB converter I_P2 can be expressed by Equation (12).

$$I_{P2}=-\frac{P}{V_{\mathrm{DC}\_\mathrm{link}}}=\frac{V_{\mathrm{DC}}}{n\omega L_k}\delta (1-\hspace{0.17em}\frac{\left|\delta \right|}{\pi })$$

(12)

where the negative sign represents the direction of the current. Since the current source is nonlinear, it should be linearized at the operating point δ_o (at light load), as shown in Equation (13).

$$G_o=-\frac{d{I}_{P2}}{d\delta }=\frac{V_{\mathrm{DC}}}{n\omega L_k}(1-2\frac{\left|\delta \right|}{\pi })$$

(13)

where G_o is the linearized equation of the DAB, which represents the gain of the DAB converter. In addition, ω is equal to 2πfs, and f_s is the switching frequency. The linearized small signal model equation for the DAB converter can be obtained as shown in Equation (14).

$$I_{\mathrm{P}2}^{\prime }=G_o\times {\delta }^{\prime }=-\frac{V_{\mathrm{DC}}}{n\omega L_k}(1-2\frac{\left|\delta \right|}{\pi })\hspace{1em}{\delta }^{\prime }$$

(14)

The small signal model equation in Equation (14) is a proportional function. A higher gain of the converter can be achieved with a smaller phase shift, and a larger phase shift results in a smaller gain of the converter.

$$H(s)=\left[\frac{R_L}{1+C_{\mathrm{DC}\_\mathrm{Link}}{R}_{L}s}\right]$$

(15)

The H(s) in Equation (15) is the transfer function of the output capacitor and the load, as shown in Figure 5. Here, R_L is the equivalent load resistance, and C_{DC_link} is the output capacitance. The transfer function of the PI compensator can be expressed by Equation (16).

$$G_c(s)=K_p\left[\frac{1+\tau s}{\tau s}\right]$$

(16)

where K_p is the proportional gain, and τ is the time constant. In a small signal model of a DAB converter, the leakage inductance L_k and the ESR of the capacitor can be neglected for simplicity of analysis, otherwise, the order of the system is increased [23]. Since the leakage inductance is very small and the pole frequency associated with it is far beyond the bandwidth of the controller, it can be neglected. Therefore, the above-mentioned small signal model is valid around the operating frequency.

By using Equations (13) and (15), the control to output transfer functions at each direction of the DAB converter can be derived by Equations (17) and (18), respectively.

$$\begin{array}{l}\hspace{1em}\hspace{0.33em}\hspace{1em}{G}_{V_{\mathrm{DC}\_\mathrm{link}}}=\frac{v_{\mathrm{DC}\_\mathrm{link}}^{\prime }}{{\delta }^{\prime }}=Go\times H(s)\hspace{0.17em}\hspace{1em}\hspace{0.17em}\hspace{1em}\\ G_{V_{\mathrm{DC}\_\mathrm{link}}}=\frac{V_{\mathrm{DC}}}{n\omega L_k}\hspace{0.17em}\hspace{0.17em}\left(1-2\frac{\left|\delta \right|}{\pi }\right)\left(\frac{R_L}{1+C_{\mathrm{DC}\_\mathrm{Link}}{R}_{L}s}\right)\end{array}$$

(17)

Similarly, the control to input voltage transfer function can be obtained by Equation (18).

$$\begin{array}{c}{G}_{V_{\mathrm{DC}}}=\frac{v_{\mathrm{DC}}^{\prime }}{{\delta }^{\prime }}=-Go\times H(s)\\ G_{V_{\mathrm{DC}}}=-\frac{V_{\mathrm{DC}\_\mathrm{link}}}{n\omega L_k} \left(1-2\frac{\left|\delta \right|}{\pi }\right)\left(\frac{R_L}{1+C_{\mathrm{DC}}{R}_{L}s}\right)\end{array}$$

(18)

with a pure resistive load, the transfer function is comprised of two poles and one zero. Since the pole frequency is affected by the load resistance, it is low at light loads and high at heavy loads. The order of the transfer function of the DAB converter is the first order at a given operating condition with δ_o. Therefore, it is easy to design the PI controller for the DAB converter and it can be regarded as another advantage of the proposed method.

In order to verify the validity of the proposed transfer function of the DAB, both MATLAB and PSIM simulations are performed with the specification of the DAB given in

Table 1. Specification of the System.

Designator	Parameters	Values
VDC	PV Simulator Voltage	380 V
VDC_link	DC-Link Voltage	400 Vrms
Vrms	Inverter Output Voltage	220 Vrms
Po	Inverter Output Power	5 kW

and

Table 2. Component for the Hardware Test.

Component	Manufacturer	Part Number
Mosfet	Rohm	SCH2080 KE
Filim Capacitor	Panasonic
Magnetic Core	Changsung	PQ72/52
Gate Driver	Silicon Lab	Si8275

. First, the circuit is implemented in PSIM using the parameters in Table 1 and

Table 3. Design Parameters.

Designator	Parameters	Values
CDC	DC-Source Capacitance	200 µF
CDC_link	DC-Link Capacitance	400 µF
CBlocking	DC-Blocking Capacitance	8 µF
Llk	Leakage Inductance	20.71 µH
n	Transformer turns ratio	1:1
Fs	Switching Frequency (DAB)	100 kHz
Fg	Switching Frequency (Inverter)	10 kHz

, and its transfer function is drawn by using a built-in AC SWEEP function in PSIM. Second, a bode plot of the proposed simplified transfer function of the DAB converter is drawn using MATLAB. As clearly indicated in Figure 6, the Bode plots drawn by MATLAB and PSIM are well matched, which verifies that the proposed simplified model is valid. Therefore, the derived transfer functions can be used to analyze the converter response and to design the closed loop control of the system.

4. Design of the Controllers for DAB Converters Voltage Control and the Elimination of Double Line Frequency Ripple

Figure 7 represents a block diagram of the control loop for a conventional DAB to control the output voltage. Here, the block H(s) represents the transfer function of the output filter and the load of the equivalent circuit model expressed in Equation (15) and G_o is the gain of the DAB converter shown in Equation (13). The block with a gain of “−1” indicates the direction of the current I_P2 in Figure 7, and G_c(s) represents the transfer function of the PI controller.

There are two controllers in the proposed double line frequency ripple elimination method. One is a PI controller to compensate the double line frequency ripple, and the other is another PI controller to regulate the DC link voltage. As explained earlier, the transfer functions of the DAB converter in each direction are given by Equations (17) and (18).

A block diagram of the proposed control loop is shown in Figure 8a. Figure 8b shows the double line frequency ripple compensation loop, in which the average control loop for the DC link voltage of the VSI is neglected since the ripple compensation loop is much faster than the average control loop. In the ripple compensation loop, where the BPF(s) and PI_VDC(s) are the band pass filter and the PI controller, where the transfer functions are expressed in Equations (16) and (19), respectively. Another PI controller, shown as PI_{VDC_link}(s), is used for regulating the average voltage across the DC link capacitor.

At first, the double line frequency ripple compensation loop is designed as shown in Figure 8b. In designing the BPF its center frequency is selected at 120 Hz and the lower value of the damping factor is selected to obtain a higher gain at 120 Hz. Therefore, the transfer function of the BPF can be obtained by Equation (19).

$$BPF(s)=\frac{k\omega S}{S^2+k\omega S+{\omega }^2}$$

(19)

where, ω is the resonant angular frequency, and k is the damping factor.

The PI controller needs to be designed to reject all of the frequency components other than 120 Hz ripple by allowing a higher gain at 120 Hz. Thus, the loop gain T_VDC for the double line frequency ripple compensation loop can be represented by Equation (20).

$$T_{(\mathrm{VDC})}=BPF(s)\times P{I}_{\mathrm{VDC}}\times G_{\mathrm{VDC}}$$

(20)

where G_VDC is the control to input transfer function in Equation (18).

The double line frequency ripple controllers are designed using MATLAB and the resulting Bode plots are drawn as shown in Figure 9a. The parameters for the PI controller are K_p = −0.3 and the time constant τ = 10 × 10⁻³. It can be clearly seen from the Bode plot that the design of the controller has been accomplished as expected. It only shows a very high gain at 120 Hz. The loop gain is 29.6 dB at 120 Hz, which is adequate to eliminate the 120 Hz ripple component.

The voltage controller for the DC link voltage of the VSI is designed using the block diagram shown in Figure 8c. The main consideration for this controller is to allow the 120 Hz AC ripple at the DC link by loosely controlling. Hence, the bandwidth of the DC link voltage controller is selected to be as far below 120 Hz as possible.

Figure 8c shows a control block diagram of the entire system including the double line frequency ripple elimination loop. The loop gain T_{VDC_link} of the average voltage control loop can be represented by Equation (21). Where G_VDC-link is the plant transfer function, as shown in Equation (17), and PI_VDC-link is the transfer function of the PI controller for the DC link voltage control.

$$T_{(\mathrm{VDC}\_\mathrm{link})}(s){|}_{\mathrm{Vdc}\_\mathrm{ref}=0}=\frac{P{I}_{\mathrm{VDC}\_\mathrm{link}}{G}_{\mathrm{VDC}\_\mathrm{link}}}{1+BPF(s)\times P{I}_{\mathrm{VDC}}\times G_{\mathrm{VDC}}}$$

(21)

By using MATLAB, the controller can be designed with the procedure mentioned above. A Bode plot of the loop gain T_{VDC_link(s)} can be found in Figure 9b. The parameters for the PI controller are obtained as Kp = 0.003 and τ = 30 × 10 ⁻³. The bandwidth of the DC link voltage controller is 32.4 Hz and the phase margin is 80.3 deg.

5. Experimental and Simulation Results

5.1. Simulation Results

In order to verify the performance of the proposed method a PSIM simulation is performed. The circuit parameters and system specification can be found in Table 1 and Table 3. It is desirable to limit the input ripple to be as small as possible to minimize the losses caused by the interactions among the renewable energy source, the double line frequency ripple and the power rating of the components used in the converter such as the transformer and the switches [24,25]. Here, the input capacitance value is 200 µF. Since the double line frequency ripple at the DC link side is allowed up to 60 Vp-p (7.5% variation of the DC link voltage) at 5 kW, the required DC link capacitance is just 400 uF in accordance with Equation (5). The double line frequency ripple can be further reduced if a larger DC link capacitance is used.

Figure 10 shows simulation results with and without the double line frequency ripple elimination control at 1 kW and 5 kW in order to show the effectiveness of the proposed method. Figure 10a,b shows simulation results when the proposed algorithm is not applied. It can be clearly seen that the voltage at the DC source includes a 120 Hz ripple of with an amplitude of 40 Vp-p and 110 Vp-p at 1 kW and 5 kW, respectively. The DC-link voltage also has a double line frequency ripple component of 18 Vp-p and 60 Vp-p at 1 kW and 5 kW, respectively. Figure 10c,d show PSIM simulation results when the proposed algorithm is applied. It can be observed from Figure 10c,d that the 120 Hz ripple is effectively suppressed by the proposed method and that only a 3 Vp-p ripple at 1 kW and a 6 Vp-p ripple at 5 kW remains at the DC source, which is less than 2% of the DC input voltage. Although the amplitude of the double line frequency ripple at the DC link is the same as before, the inverter can successfully generate a 60 Hz output current over the entire load range.

5.2. Experimantal Results

For experimental verification of the proposed method, a DAB converter and a single phase full-bridge inverter have been implemented as shown in Figure 11. Here, a TeraSAS ETS (600/17) photovoltaic simulator has been used as a DC Source since it can allow a 120 Hz ripple at its input with a very small output capacitance. The DAB converter and the VSI inverter are controlled by a DSP TMS320F28335. The proposed double line frequency elimination technique has been implemented in the DSP for the DAB converter.

In order to show the effectiveness of the proposed method, experiments are performed with and without the proposed double line frequency ripple elimination algorithm. Figure 12 shows experimental waveforms of the two stage DC/AC power conversion system without the proposed double line frequency ripple elimination algorithm. The waveforms from top to bottom in Figure 12 are I_p, I_s, V_{DC_link}, V_DC and I_L, which show the primary and secondary current of the transformer, DC link voltage, DC input voltage and inverter output current, respectively.

Figure 12 clearly indicates that the voltage at the DC input side and the current at the primary and secondary side of the transformer all have a 120 Hz ripple component. When the power of the converter is increased, the amplitude of the ripple is also increased. Here, experiments are performed up to a 2.0 kW output power since the DC source PV simulator turns off due to the double line frequency ripple when the power exceeds 2.0 kW.

Experimental results obtained with the proposed double line frequency ripple elimination control are obtained at 1 kW, 2 kW, 3 kW, 4 kW and 5 kW in order to verify the validity of the proposed control method. Figure 13 illustrates results when the proposed method is enabled. It can be seen from Figure 13 that the 120 Hz ripple is effectively suppressed by the proposed method. It can also be observed that the currents at both sides of the transformer are free of low frequency ripple.

In Figure 13, the maximum ripple at the DC source is only 6.5 Vp-p at 5 kW, which proves that the ripple at the input is effectively suppressed by the proposed control algorithm. The ripple can be eliminated from the input side with only a 200 μF capacitance at the DC input side. In addition, the capacitance value used at the DC link is only 400 μF. Furthermore, experimental results show that the controller successfully regulates 400 V at the DC link to obtain AC 220 Vrms at the inverter output.

In order to obtain a 6.5 Vp-p ripple at the DC input source without the double line frequency ripple elimination method, the required capacitance is 5000 μF according to Equation (5). This is 25 times larger than that of the proposed system (200 μF). The reduction in the DC source side decoupling capacitance is calculated as 96%. On the other hand, only a 400 uF capacitor can be used at the DC link side if a peak ripple voltage of 30 V is allowed.

Figure 14a shows a comparison chart for the double line frequency ripple with and without the proposed method at 1 kW, 1.5 kW and 2 kW. As shown in Figure 14, the double line frequency ripple can be effectively suppressed by the proposed method up to 95.8%.

Table 4. Comparison of the reduction of 120 Hz ripple at the DC input.

	Input Capacitor Values	Input Capacitor Reduction (%)	Ripple Reduction at DC input (%)	DC Input Voltages (V)	Ripple at the DC-Link (Vp-p)	Power	Additional Hardware Required	C × V/Power (μF×kV/kW)
[10]	2 × 50 µF	64	NP 1	200	20	425 W	Yes	47.05
[18]	100 µF	74	94.3	400	NP	2 kW	Yes	20
[26]	2 × 100 µF	90	90	150	50	500 W	No	60
[27]	2 × 30 µF	90	50	100	150	400 W	No	15
[28]	320 µF	90.4	58.6	200	50	1 kW	No	40
[29]	100 µF	78	NP 1	100	130	500 W	No	20
[30]	100 µF	89	68	450	10.5	2 kW	No	22.5
[31]	120 µF	82	92	400	10.8	1 kW	Yes	48
[32]	2 × 90 µF	74.21	91	380	10	1 kW	Yes	68.4
[33]	9 × 5 µF	68	97	1100	280	3 kW	No	16.5
[34]	2 × 12 µF/30 µF	97	NP	165	150	1 kW	No	27
[35]	30/120/10 µF	95	96	150	146	4 kW	Yes	32
(Proposed)	2 × 100 µF	96	95	380	60	5 kW	No	15.2

¹ NP (Not Provided).

shows a comparison of several double line frequency ripple reduction methods in terms of the percentage of the ripple reduction, the required capacitance and the volume of the capacitor used. It is clearly shown in Table 4 that the proposed method is outstanding among the methods developed so far in terms of capacitor volume, ripple reduction and capacitance reduction.

6. Conclusions

This paper has presented a novel double line frequency ripple elimination method for two-stage single-phase DC-AC power conversion systems. With the proposed ripple elimination method, the input capacitance of the front-end dc-dc converter can be reduced by 96% and the double line frequency ripple can be suppressed by up to 95.8%. The main advantage of the proposed method is that it does not require any additional circuits to reduce the ripple at the DC source side. Thanks to the ripple elimination capability of the proposed technique, it can achieve several advantages such as elimination of the power loss associated with ripple current, reduction in the rating of the components used in the circuit, and prolonged lifetime of the power conversion system owing to the use of film capacitors. In addition, the volume and cost of the converter can be further reduced due to the small capacitance value required to maintain the DC link. The validity and the feasibility of the proposed control method have been verified by experimental results with a 5 kW two-stage single-phase inverter.