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Peer-Review Record

Error-Vulnerable Pattern-Aware Binary-to-Ternary Data Mapping for Improving Storage Density of 3LC Phase Change Memory

Electronics 2020, 9(4), 626; https://doi.org/10.3390/electronics9040626
by Jeong Beom Hong 1, Young Sik Lee 2, Yong Wook Kim 2 and Tae Hee Han 3,*
Reviewer 1: Anonymous
Reviewer 2: Anonymous
Electronics 2020, 9(4), 626; https://doi.org/10.3390/electronics9040626
Submission received: 28 February 2020 / Revised: 6 April 2020 / Accepted: 7 April 2020 / Published: 9 April 2020
(This article belongs to the Section Computer Science & Engineering)

Round 1

Reviewer 1 Report

Multi-level-cell phase-change memory is a interesting topic and can potentially boost the current memory market to another level. This paper is helpful to the researchers in this area. A reference to GST material can help the readers to quickly understand this memory from fundamental side.  

Author Response

Please see the attachment.

Author Response File: Author Response.pdf

Reviewer 2 Report

I think this manuscript is a good job. The only improvement, which is essential, is to compare it with a very recent reference, making a comparative analysis, even if it is theoretical of what is proposed and of the results presented, with respect to the results of this work.

The reference is:

T. Kwon, M. Imran and J. Yang, "Cost-Effective Reliable MLC PCM Architecture Using Virtual Data Based Error Correction," in IEEE Access, vol. 8, pp. 44006-44018, 2020.

Author Response

Please see the attachment.

Author Response File: Author Response.pdf

Round 2

Reviewer 2 Report

Nice work!!!

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