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Article

Optimization and Implementation of Synthetic Basis Feature Descriptor on FPGA

1
School of Electrical and Computer Engineering, Nanfang College of Sun Yat-sen University, Guangzhou 510970, China
2
Department of Electrical and Computer Engineering, Brigham Young University, Provo, UT 84602, USA
*
Author to whom correspondence should be addressed.
Electronics 2020, 9(3), 391; https://doi.org/10.3390/electronics9030391
Received: 25 January 2020 / Revised: 21 February 2020 / Accepted: 24 February 2020 / Published: 27 February 2020
(This article belongs to the Special Issue Convolutional Neural Networks and Vision Applications)
Feature detection, description, and matching are crucial steps for many computer vision algorithms. These steps rely on feature descriptors to match image features across sets of images. Previous work has shown that our SYnthetic BAsis (SYBA) feature descriptor can offer superior performance to other binary descriptors. This paper focused on various optimizations and hardware implementation of the newer and optimized version. The hardware implementation on a field-programmable gate array (FPGA) is a high-throughput low-latency solution which is critical for applications such as high-speed object detection and tracking, stereo vision, visual odometry, structure from motion, and optical flow. We compared our solution to other hardware designs of binary descriptors. We demonstrated that our implementation of SYBA as a feature descriptor in hardware offered superior image feature matching performance and used fewer resources than most binary feature descriptor implementations. View Full-Text
Keywords: synthetic basis; FPGA; feature descriptor synthetic basis; FPGA; feature descriptor
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MDPI and ACS Style

Lee, D.-J.; Fuller, S.G.; McCown, A.S. Optimization and Implementation of Synthetic Basis Feature Descriptor on FPGA. Electronics 2020, 9, 391. https://doi.org/10.3390/electronics9030391

AMA Style

Lee D-J, Fuller SG, McCown AS. Optimization and Implementation of Synthetic Basis Feature Descriptor on FPGA. Electronics. 2020; 9(3):391. https://doi.org/10.3390/electronics9030391

Chicago/Turabian Style

Lee, Dah-Jye, Samuel G. Fuller, and Alexander S. McCown. 2020. "Optimization and Implementation of Synthetic Basis Feature Descriptor on FPGA" Electronics 9, no. 3: 391. https://doi.org/10.3390/electronics9030391

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