A New Hybrid Ćuk DC-DC Converter with Coupled Inductors

Abstract

This paper proposes a new hybrid Ćuk-type converter employing two inductors built on the same core which can be successfully used in applications requiring an output voltage considering higher than the input one. With few components added, in the proposed converter the static conversion ratio can be easily extended becoming wider compared to the classical Ćuk topology. At the same duty cycle range the output voltage is higher than in the classical Ćuk converter. The output voltage remains with negative polarity and with a reduced ripple. An advantage of the new converter is given by its two degrees of freedom. A DC and AC analysis is carried out, device stresses are evaluated and a comparative analysis of the proposed hybrid Ćuk topology to other indirect converters has also been performed. All the equations necessary for designing the converter are provided. The simulations performed together with the practical experiments carried out, all results confirm that the theoretical considerations are correct and validate the features that the proposed converter can provide a higher static conversion ratio without operating at high duty cycles.

1. Introduction

Dc-dc converters are used in a large variety of applications: unidirectional and bidirectional chargers in automotive, renewable energies in photovoltaic cells for example, dc grids, cellphones, computers, laptops and so forth. These power circuits should be able to step-up [1,2,3,4,5,6,7,8,9], step-down [10,11,12,13] or step-up/step-down [14,15,16,17,18,19,20,21] the voltage from the input. The polarity of the output voltage can be the same [1,2,3,4,6,7,8] or reverse [5,22,23,24,25,26,27,28,29] compared to that of the input voltage. Regarding to the static conversion ratio, the converter can be used in applications where a small or large difference between the input and output voltages of the converter are encountered. Therefore, depending on the application requirements, considering the few parameters mentioned before, different types of converters exist on the market. Because this paper introduces a new Ćuk topology, different types of both step-down/step-up converters have been analyzed [14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32]. If isolation is not necessary, the classical Buck-Boost converter [30] can be used. It even has the advantage of a reduced number of components and simplicity; however, control is sometimes difficult because its transistor is floating. Another step-up/step-down structure it is the classical Ćuk converter [32]. This topology can be used with coupled [32] or uncoupled inductors [31]. The advantage of coupling the inductors is that the current through the one of the inductors can be made with a very small ripple. For increasing the step-down nature of the converter, the authors of References [25,27], are using a switched-capacitor or switched inductor structure [25,27] that it is inserted in the traditional Ćuk converter. The same work reported in References [25,27] improve the step-up capabilities by inserting a switched inductor structure in the classical Ćuk converter. In References [24,28], it is shown that coupling the inductors in the additional switching cell inserted in a Ćuk converter, this leads to a higher step-up conversion ratio than in the classical one. Different structures of isolated Ćuk converters are presented in References [33,34]. The step-up and step-down nature can be also found in quadratic converters [20].

How it was mentioned, in this paper a new hybrid Ćuk-type topology with coupled inductors exhibiting a higher static conversion ratio than in a classical Ćuk converter is introduced. The development of the new proposed converter, dc analysis and the main waveforms are depicted in Section 2. The semiconductors current and voltage stresses, the peak-to-peak ripples and the Continuous Conduction Mode (CCM) operation condition are derived in Section 3. In Section 4 a theoretical comparative study to other step-up/step-down topologies is performed and a design example is presented in Section 5.

In order to confirm the theoretical considerations at set of simulations are performed in Section 6. Finally, the practical experiments that validate the feasibility of the proposed converter are presented in Section 7, while Section 8 is devoted to the conclusions.

2. Description of Operation and Steady State Analysis of the Proposed Hybrid Ćuk Converter

The origin of the new proposed converter is the hybrid step-up converter with switching structure Up3 from Reference [25], enfaced in Figure 1.

The first step in developing the proposed converter was to couple the inductors L₁ and L₂. Assuming perfect coupling and denoting by N₁ and N₂ the turns number corresponding to L₁ and L₂ respectively, the transformer ratio n is assumed higher than unity.

The transformer ratio is defined as:

$$n=\frac{N_2}{N_1}>1.$$

(1)

For n > 1, diode D₃ will be always off and therefore it can be removed from the circuit.

The new proposed converter, as Figure 2 reveals includes one transistor, three diodes, three inductors out of which two are coupled, therefore two magnetic cores are used and two capacitors.

Modelling the coupled inductors by an ideal transformer (IT) together with a magnetizing inductor, L_M, the equivalent schematic is represented in Figure 3. In this approach the magnetizing inductor L_M is considered equal with L₁ and all components are assumed to be ideal.

In Continuous Conduction Mode (CCM), depending on the state of the power transistor, two topological states are possible. The switching frequency and the corresponding switching period are denoted f_s and T_s respectively. The converter is controlled by a pulse width modulated signal of duty cycle D. The first topological state, last from 0 to D∙T_s and the configured circuits is presented in Figure 4a, where transistor Q and diode D₁ are on, while the other two diodes D₂ and D₄ are off, as they are reversely biased. From D∙T_s to T_s, the second topological state is configured with transistor Q and diode D₁ off, while diodes D₂ and D₄ are on. The corresponding circuit is depicted in Figure 4b.

Taking into consideration the notations from Figure 3, the ideal transformer equations are:

$$\{\begin{array}{c}\frac{v_1}{1}=\frac{v_2}{n}\\ i_1+n·i_2=0\end{array}$$

(2)

The small ripple assumptions is assumed for the capacitor voltages and inductor currents, therefore in the subsequent analysis these variable are assumed constant and equal to their dc value.

Invoking the volt-second balance principle for the magnetizing inductor L_M and inductor L₃, the equations are:

$$\{\begin{array}{c}D·V_g+\left(1-D\right)·\frac{V_g-V_C}{1+n}=0\\ D·(V_C-V_{CO})+\left(1-D\right)·\left(-V_{CO}\right)=0\end{array}$$

(3)

After solving system (3), the dc voltages across the internal capacitor C and across the output capacitor C_O can be written as:

$$V_C=\frac{1+n·D}{1-D}·V_g.$$

(4)

$$V_{CO}=\left(1+n·D\right)·\frac{D}{1-D}·V_g.$$

(5)

As $V_{CO}=V_O$, the ideal static conversion ratio M of the new converter is given by (5):

$$M=\left(1+n·D\right)·\frac{D}{1-D}.$$

(6)

From (6), the duty cycle can be expressed in terms of static conversion ratio as:

$$D=\frac{-1-M+\sqrt{{\left(1+M\right)}^2+4nM}}{2n}.$$

(7)

Examining the Equation (6), after some simple algebra, it follows that if the duty cycle is higher than $\frac{\sqrt{1+n}-1}{n}$ the static conversion ratio is higher than unity. For n = 2, we have $\frac{\sqrt{1+n}-1}{n}=0.365$, for n = 3, $\frac{\sqrt{1+n}-1}{n}=0.33$, which means that the proposed converter from Figure 2 has a both step-up and step-down nature. However, compared to the Buck-Boost or the Ćuk converter the converter starts to step-up as a considerably lower duty cycle, in the example provided around 0.33 compared to the value of 0.5. The higher the value of n the lower will be the duty cycle that defines the step-up region. In conclusion, the step-up region is more extended compared to the Buck-Boost and the Ćuk converter.

For calculating the dc magnetizing inductor current I_LM and the dc output inductor current I_L3, the charge balance principle related to the capacitor C and C_O is invoked:

$$\{\begin{array}{c}D·(-I_{L3})+\left(1-D\right)·\frac{I_{LM}}{1+n}=0\\ D·\left(I_{L3}-\frac{V_{CO}}{R}\right)+\left(1-D\right)·\left(I_{L3}-\frac{V_{CO}}{R}\right)=0\end{array}$$

(8)

Solving (8) the dc magnetizing inductor current I_LM is:

$$I_{LM}=\frac{D^2·\left(1+n·D\right)·\left(1+n\right)}{{\left(1-D\right)}^2}·\frac{V_g}{R}.$$

(9)

and, the dc output inductor current I_L3 is:

$$I_{L3}=\frac{D·\left(1+n·D\right)}{1-D}·\frac{V_g}{R}.$$

(10)

The steady state waveforms for the reactive components and semiconductor devices are drawn in Figure 5, Figure 6 and Figure 7.

The control voltage q(t) associated to the transistor is chosen as a reference, where q(t) is given by:

$$q\left(t\right)=\{\begin{array}{c}1, Q-ON\\ 0, Q-OFF\end{array}.$$

(11)

Because the inductive voltages are piecewise constant, exhibiting a rectangular shape, the inductive currents will be piecewise linear, increasing if the voltage is positive and decreasing if the voltage is negative. Similarly, the internal capacitor current is piecewise constant, resulting in a piecewise linear internal capacitor voltage. As the output node is a non-switched one, the current through the output capacitance, Co, is piecewise linear - has the same shape as i_L3 but with zero dc value. Since the current of the capacitance Co is piecewise linear, its voltage will be piecewise parabolic.

3. Semiconductor Stresses and Inductor Currents and Capacitor Voltages Peak-to-Peak Ripple

In the design process of the converter and practical implementation is necessary that the current and voltage stresses related to the semiconductors to be known. These stresses will be expressed in terms of the supply voltage V_g, the control duty cycle D, load R and the circuit parameters.

The voltage across switch Q is calculated from the second topological state as being equal to the voltage across the internal capacitor V_C. By replacing V_c from (4), the transistor voltage stress is:

$$V_Q=\frac{1+n·D}{1-D}·V_g.$$

(12)

The dc transistor current stress is the sum between I_LM and I_L3, so the dc transistor current is:

$$I_Q=D·(I_{LM}+I_{L3})=\frac{D^2·{\left(1+n·D\right)}^2}{{\left(1-D\right)}^2}·\frac{V_g}{R}.$$

(13)

The voltage stress across diode D₁ results from second topological state:

$$V_{D_1}=n·\frac{V_g-V_C}{1+n}=\frac{n·D}{1-D}·V_g.$$

(14)

The dc current through diode D₁ is given by:

$$I_{D_1}=D·I_{LM}=\frac{D^2·\left(1+n·D\right)·\left(1+n\right)}{{\left(1-D\right)}^2}·\frac{V_g}{R}.$$

(15)

The voltage across diode D₂ can be found from first topological state:

$$V_{D_2}=n·V_g.$$

(16)

The dc current through the diode D₂ is calculated as:

$$I_{D_2}=\left(1-D\right)·\frac{I_{LM}}{1+n}=\frac{D^2·\left(1+n·D\right)}{1-D}·\frac{V_g}{R}.$$

(17)

The voltage across diode D₄ can be found from first topological state:

$$V_{D_4}=\frac{1+n·D}{1-D}·V_g.$$

(18)

The dc current through diode D₄ can be written as:

$$I_{D_4}=\left(1-D\right)·\left(\frac{I_{LM}}{1+n}+I_{L3}\right)=\frac{D·\left(1+n·D\right)}{1-D}·\frac{V_g}{R}.$$

(19)

Regarding the ripples, the magnetizing peak-to-peak current ripple is given by:

$$\Delta I_{LM}=\frac{D·V_g}{L_M·f_s}.$$

(20)

The peak-to-peak current ripple for L₃ inductor can be expressed as:

$$\Delta I_{L3}=\frac{D·\left(1+n·D\right)·V_g}{L_3·f_s}.$$

(21)

The internal capacitor voltage ripple, $\Delta V_C,$ is provided by:

$$\Delta V_C=\frac{D^2·\left(1+n·D\right)}{1-D}·\frac{V_g}{C·R·f_s}.$$

(22)

In order to calculate the output capacitor voltage ripple, the same technique applied for the Buck converter output voltage ripple calculations is used. The charge injected in the capacitor between the time moments corresponded to the minimum and the maximum capacitor voltage is:

$$\Delta Q=\frac{1}{2}·\frac{T_s}{2}·\frac{\Delta I_{L3}}{2}.$$

(23)

Now, the capacitor voltage ripple can be easily estimated as:

$$\Delta V_{CO}=\Delta V_O=\frac{\Delta Q}{C}.$$

(24)

The CCM operation condition requires the diodes to be permanently on during the whole topological state they are assumed to conduct. This imposes the condition that diode currents have to stay positive during those topological states or equivalently the minimum current to be positive.

Because D₁ and D₂ currents are equal to i_LM for these diodes the CCM condition is the same and imposes that the minimum magnetizing current, I_LMmin to be positive. As, $I_{LMmin}=I_{LM}-\frac{1}{2}·\Delta I_{LM}$, using (9) and (20), the final condition is:

$$\frac{2·L_M·f_s}{R}\ge \frac{{\left(1-D\right)}^2}{D·\left(1+n·D\right)·\left(1+n\right)}.$$

(25)

The CCM condition for diode D₄ takes into account the current flowing through it is $\frac{i_{LM}}{n+1}+i_{L3}$. Because i_LM and i_L3 have the same monotonicity, the CCM condition results immediately.

$$\frac{2·L_e·f_s}{R}\ge \frac{{\left(1-D\right)}^2}{1+n·D},$$

(26)

where, the equivalent inductor is:

$$L_e=(L_M·\left(1+n·D\right))|| \frac{L_3}{1+n}.$$

(27)

It can be remarked that (26) has the same form to that of Buck-Boost or Ćuk converter.

Although the inductors can be designed from the CCM operation conditions, a more realistic design comes from the small ripples condition. It is known that this small ripple conditions imposes the peak-to-peak current ripple to be less than 25% of the dc value of the corresponding inductor current:

$$\Delta I_{LM}\le \frac{1}{4}·I_{LM}$$

(28)

$$\Delta I_{L3}\le \frac{1}{4}·I_{L3}.$$

(29)

From Equations (9), (10), (20) and (21) the minimum inductor values results:

$$L_{Mmin}=\frac{4}{M·\left(1+n\right)}·\frac{R}{f_s}·\left(1-D\right)$$

(30)

$$L_{3min}=4·\left(1-D\right)·\frac{R}{f_s}.$$

(31)

Similarly, the minimum capacitor values result also from the small ripple conditions that in this case requires the capacitor voltage ripple to be less than a percent of its dc value. Using (4) and (22) the minimum required value is:

$$C_{min}=\frac{D^2·\left(1+n·D\right)}{1-D}·\frac{V_g}{\Delta V_C·f_s·R}.$$

(32)

The output capacitor is design such that to be high enough to assure an output voltage ripple less than the value imposed by specifications. From Equations (5) and (24) its minimum value is given by:

$$C_{Omin}=\frac{1-D}{8·f_s{}^2·L_3}·\frac{V_{CO}}{\Delta V_{CO}}.$$

(33)

4. Comparison to Similar Converter Topologies

A comparison between the proposed hybrid Ćuk dc-dc converter and different step-up/step-down topologies namely the classical Buck-Boost [30], classical Ćuk [32] and hybrid Ćuk from Reference [24] is presented in

Table 1. Comparison between main parameters of different step-up converters.

Parameter	Type of Converter
	Classical Buck-Boost [30]	Classical Ćuk [32]	Hybrid Ćuk [24]	Proposed Hybrid Ćuk
Switches	1	1	1	1
Diodes	1	1	3	3
Total no. of components	4	6	8	8
System order	2	4	4	4
Static conversion ratio-M	$\frac{D}{1-D}$	$\frac{D}{1-D}$	$\frac{D·\left(n+D\right)}{n·\left(1-D\right)}$	$\frac{D·\left(1+n·D\right)}{1-D}$
Duty cycle-D	$\frac{M}{1+M}$	$\frac{M}{1+M}$	$\frac{A-n·\left(1+M\right)}{2}$	$\frac{B-\left(1+M\right)}{2n}$
Switch current stress	$M^2·\frac{V_g}{R}$	$M·\left(1+M\right)·\frac{V_g}{R}$	$M^2·\frac{V_g}{R}$	$M^2·\frac{V_g}{R}$
Switch voltage stress	$\left(1+M\right)·V_g$	$\left(1+M\right)·V_g$	$\frac{2·M·V_g}{-n-n·M+A}$	$\frac{2nM·V_g}{-1-M+B}$
Maximum diode dc current stress	$M^2·\frac{V_g}{R}$	$M·\left(1+M\right)·\frac{V_g}{R}$	$M·\frac{V_g}{R}$	$M·\frac{V_g}{R}$
Maximum diode voltage stress	$\left(1+M\right)·V_g$	$\left(1+M\right)·V_g$	$\frac{2·M·V_g}{-n-n·M+A}$	$\frac{2nM·V_g}{-1-M+B}$

where, $A=\sqrt{n^2{\left(1+M\right)}^2+4\mathrm{nM}}$, $B=\sqrt{{\left(1+M\right)}^2+4nM}$.

. In order the comparison to be fair, it is considered that they are supplied by the same input voltage V_g, they deliver the same output voltage V_o on the same load R. Hence, the conversion ratio M and the output power P_o are the same. The comparative parameters are: the number of active and passive semiconductors, total number of components, the system order, the expression of the static conversion ratio M, the expression of the duty cycle D, the current and voltage semiconductor stresses.

From Table 1, it can be seen that each topology has only one transistor. In comparison to the classical Ćuk, the proposed topology has two additional diodes, the same system order but smaller transistor and diode dc current stresses. How it was demonstrated in Section 2, at the same duty cycle D, the static conversion ratio of the proposed topology is higher than that of any of the compared converters. This is revealed in Figure 8, where the dependency of the static conversion ratios against duty cycle for classical Ćuk and the proposed topology, at different transformer ratios, is presented. Therefore, for step-up applications where a big difference between the input and output voltage is needed the proposed hybrid Ćuk topology is better suitable.

5. Design Example

It is desired to design a hybrid Ćuk converter according to the following specifications:

• Input voltage: V_g = 24 ÷ 36 V
• Output voltage: V_o = 120 V
• Output power: P_o = 30 ÷ 50 W
• Switching frequency: f_s = 100 kHz

It is assumed that operation is in closed loop size that the output voltage is maintained constant.

Because the input and output voltages are known, the maximum and minimum value of the static conversion ratio can be calculated:

$$M_{min}=\frac{V_O}{V_{g_{max}}}=3.33$$

(34)

$$M_{max}=\frac{V_O}{V_{g_{min}}}=5.$$

(35)

We shall choose to operate at a moderate duty cycle range D ∈ [0.6, 0.7].

With D_min = 0.6, because the minimum static conversion ratio corresponds to D_min, the necessary turns ratio results from Equations (6) and (34):

$$n=\frac{M_{min}-M_{min}·D_{min}-D_{min}}{D_{min}^2}=2.03.$$

(36)

From Equations (7), the maximum duty cycle, that corresponds to maximum static conversion ratio is:

$$D_{max}=\frac{-1-M_{max}+\sqrt{{\left(1+M_{max}\right)}^2+4\mathrm{n}{M}_{max}}}{2n}=0.68.$$

(37)

The minimum and the maximum load resistor results from the maximum and the minimum output power.

$$R_{min}=\frac{V_O^2}{P_{Omax}}=288$$

(38)

$$R_{max}=\frac{V_O^2}{P_{Omin}}=480.$$

(39)

The minimum value of the magnetizing inductor was calculated from Equation (30) in the worst case, that is for maximum load resistor and maximum input voltage $L_{Mmin}=492.9 \mu \mathrm{H}$ was obtained. The value of L₁ will be equal to the value of L_M, so L_1min= L_Mmin = 492.9 μH and L_2min = n²·L_Mmin = 2.03 mH. For practical implementation, a value of $L_M=773.38 \mu \mathrm{H}$ was used. From (31) the minimum value for inductor L₃ is obtained for maximum input voltage and minimum output power. It results $L_{3min}=3.1 \mathrm{m}\mathrm{H}$ and L₃ = 3.45 mH was used.

The value of the internal capacitor can be calculated from (32), imposing that the voltage ripple to be less than 5% of its dc value. A minimum value of $C_{min}=24.4 \mu \mathrm{F}$, results. A standard value of 33$\mu \mathrm{F}$ is chosen. For the output capacitor the ripple is considered 10% of its dc value and from (33) a value of $C_{Omin}=2.08 \mu \mathrm{F}$ is calculated. In this case a standard value of 3.3$\mu \mathrm{F}$ is chosen.

The transistor voltage stress will be V_Q = 210 V, according to (12) and its average current using (13) is I_Q = 1.5 A. respectively. To evaluate the voltage and current stresses across the diodes, Equations (14)–(19) will be used. The highest stresses for diodes are V_D = 210 V calculated from (18) and the maximum dc current I_D = 1.2 A, given by (15).

6. Simulation Results

In order to check the validity of the theoretical considerations in case of the ideal hybrid Ćuk converter, a set of simulation in Caspoc [35] tool were performed. Converter parameters were the same values used for implementing the practical prototype according with the previous design specifications:

V_g = 35 V, L₁ = 773.38 μH, L₂ = 2.39 mH, L₃ = 3.45 mH, C = 33 µF, C₀ = 3.3 µF, R = 360 Ω, f_s = 100 kHz.

Since the inductors were practically realized, a small change to the initial value of transformer ratio is found. Therefore, the new transformer ratio is n = 1.758. With this value, the required duty cycle is calculated (7) as D = 0.621. The delivered dc output voltage V₀, resulted from the simulation, is shown in Figure 9.

It can be remarked that the required value from the specifications is obtained.

The magnetizing inductor current cannot be directly displayed and only a part of the triangular shape will be seen, on the first winding, Figure 10 and the other part of triangular shape on the second winding in Figure 11. Also, the inductive voltages for the windings L₁ and L₂ are shown in these figures.

The correct CCM operation of the converter is proven both by the voltage and currents in the two windings and the triangular shape of the inductor current i_L3 together with the two-level inductor voltage v_L3, presented in Figure 12.

The voltage and current waveforms for the capacitors are illustrated in Figure 13 and Figure 14. The triangular capacitor voltage shape is validated by the simulation and also its peak-to-peak ripple value. For the output capacitor Co, the current through it is verified to have the same shape as i_L3 but with zero dc value, due to the non-switched output node.

In the following figures, Figure 15, Figure 16, Figure 17 and Figure 18, the simulation results for current and voltage of the semiconductors are presented.

The simulation results have validated the theoretical considerations, not only qualitatively but also quantitatively with respect to dc currents, dc voltages and peak-to-peak ripples, as all this magnitude have been measured in the simulation and compared to the theoretical predictions.

7. Experimental Results

In order to validate the feasibility of the proposed converter, a prototype was built with the same parameters like in the design example. The chosen transistor was Infineon Mosfet STW37N60DM2AG and the chosen diodes D_1,2,4 was of RFN10NS6SFH type. In all the acquired waveforms the reference signal on the oscilloscope was the drain-to source voltage of the transistor Q. The experiments were performed, with a fixed input voltage V_g = 35 V, a fixed switching frequency f_s = 100 kHz and a load R = 360 Ω.

The acquired waveforms for a duty cycle D = 0.2 are shown in Figure 19. It can be remarked that at this low duty cycle the operation is in DCM with respect to diodes D₁ and D₂. This is confirmed by Equation (25).

The acquired waveforms for a duty cycle D = 0.66 are shown in Figure 20, Figure 21, Figure 22 and Figure 23. The typical rectangular shape for inductor voltages and triangular shape for the inductor currents with corresponding monotonicity can be remarked, like in the theory. These waveforms also match the simulated ones and the rectangular shape of the inductor voltages and piece-wise linear shape of the inductor currents are verified both regarding monotonicity and phase.

The static conversion ratio for the prototype was measured modifying the duty cycle D and measuring the output voltage, V_o. The comparison between the ideal conversion ratio, theoretical conversion ratio in the presence of the conduction losses and the measured one is presented in Figure 24. It can be remarked that: up to a duty cycle of 0.6, all three curves are almost overlapping. At higher duty cycles the measured curve deviates, which is a typical phenomenon encountered in converters with step-up nature. In Figure 25, the theoretical statical conversion ratio in the presence of losses is presented at very high duty cycles. It can be remarked that the theoretical curve in the presence of conduction losses reaches a maximum and then start to decrease. This is a typical behavior in step-up converters in which the maximum attainable conversion ratio is a finite and limited value. The dependency of the efficiency against the output power at a constant output voltage of 120 V is shown in Figure 26.

8. Conclusions

This paper introduces a new converter that has the conversion ratio (1 + n∙D) times higher than the classical Ćuk topology. Therefore, in the step-up region, a wide static conversion ratio is achieved, being useful in applications where there is very big difference between the input and output voltage. Compared to the classical Ćuk converter, it includes two additional diodes but it exhibits lower semiconductor dc current stresses. Moreover, the turns ratio brings an additional degree of freedom that facilitate the design process. The operating principle, the steady state equations are revealed, the main waveforms are presented and the relationship for designing the converter are provided. The simulation and the experimental results validate the theoretical consideration, thus confirming the feasibility and the applicability of the proposed converter.