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Open AccessArticle

A Programmable Impedance Tuner with a High Resolution Using a 0.18-um CMOS SOI Process for Improved Linearity

1
Department of Electronics and System Engineering, Hanyang University, Ansan 15588, Korea
2
Department of Electrical, Information and Communication Engineering, Mokpo National University, Mokpo 530729, Korea
*
Authors to whom correspondence should be addressed.
Electronics 2020, 9(1), 7; https://doi.org/10.3390/electronics9010007
Received: 30 November 2019 / Revised: 17 December 2019 / Accepted: 18 December 2019 / Published: 19 December 2019
(This article belongs to the Special Issue New CMOS Devices and Their Applications)
In this paper, a novel coupler/reflection-type programmable electronic impedance tuner combined with switches that were fabricated by a 0.18-um complementary metal–oxide–semiconductor (CMOS) silicon-on-insulator (SOI) process is proposed for replacement of the conventional mechanical tuner in power amplifier (PA) load-pull test. By employing the multi-stacked field-effect transistors (FETs) as a single-branch switch, the proposed tuner has the advantage of precise impedance variation with systematic and magnitude and phase adjustment. Additionally, it led to high standing wave ratio (SWR) coverage and a good impedance resolution with a high power handling capability. Furthermore, the double-branch based on multi-stacked FET was applied to switches for additional enhancement of the intermodulation distortion (IMD) performance through the mitigated drain-source voltage of the single-FET. Drawing upon the measurement results, we demonstrated that SWR changed from 2 to 6 sequentially with a 12–15° phase angle step over a mid/high-band range of a 1.5–2.1 GHz band for 3G/4G handset application. In addition, the PA load-pull measurement results obtained using the proposed tuners verified their practicality and competitive performance with mechanical tuners. Finally, the measured linearity using the double-branch switch demonstrated the good IMD3 performance of −78 dBc, and this result is noteworthy when compared with conventional electronic impedance tuners. View Full-Text
Keywords: CMOS SOI process; impedance tuner; intermodulation distortion; multi-stacked FET switch; programmable CMOS SOI process; impedance tuner; intermodulation distortion; multi-stacked FET switch; programmable
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Bae, Y.; Jhon, H.; Kim, J. A Programmable Impedance Tuner with a High Resolution Using a 0.18-um CMOS SOI Process for Improved Linearity. Electronics 2020, 9, 7.

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