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Article

Construction of Residue Number System Using Hardware Efficient Diagonal Function

1
Department of Applied Mathematics and Mathematical Modeling, North-Caucasus Federal University, Stavropol 355009, Russia
2
Department of Higher Algebra and Geometry, North-Caucasus Federal University, Stavropol 355009, Russia
3
Department of Automation and Control Processes, St. Petersburg Electrotechnical University “LETI”, Saint Petersburg 197376, Russia
*
Author to whom correspondence should be addressed.
Electronics 2019, 8(6), 694; https://doi.org/10.3390/electronics8060694
Submission received: 8 March 2019 / Revised: 12 June 2019 / Accepted: 18 June 2019 / Published: 20 June 2019
(This article belongs to the Section Circuit and Signal Processing)

Abstract

:
The residue number system (RNS) is a non-positional number system that allows one to perform addition and multiplication operations fast and in parallel. However, because the RNS is a non-positional number system, magnitude comparison of numbers in RNS form is impossible, so a division operation and an operation of reverse conversion into a positional form containing magnitude comparison operations are impossible too. Therefore, RNS has disadvantages in that some operations in RNS, such as reverse conversion into positional form, magnitude comparison, and division of numbers are problematic. One of the approaches to solve this problem is using the diagonal function (DF). In this paper, we propose a method of RNS construction with a convenient form of DF, which leads to the calculations modulo 2 n , 2 n 1 or 2 n + 1 and allows us to design efficient hardware implementations. We constructed a hardware simulation of magnitude comparison and reverse conversion into a positional form using RNS with different moduli sets constructed by our proposed method, and used different approaches to perform magnitude comparison and reverse conversion: DF, Chinese remainder theorem (CRT) and CRT with fractional values (CRTf). Hardware modeling was performed on Xilinx Artix 7 xc7a200tfbg484-2 in Vivado 2016.3 and the strategy of synthesis was highly area optimized. The hardware simulation of magnitude comparison shows that, for three moduli, the proposed method allows us to reduce hardware resources by 5.98–49.72% in comparison with known methods. For the four moduli, the proposed method reduces delay by 4.92–21.95% and hardware costs by twice as much by comparison to known methods. A comparison of simulation results from the proposed moduli sets and balanced moduli sets shows that the use of these proposed moduli sets allows up to twice the reduction in circuit delay, although, in several cases, it requires more hardware resources than balanced moduli sets.

1. Introduction

The residue number system (RNS) is a non-positional number system that allows large length numbers to be presented as numbers in independent bits of a small length, which enables computations and the organizing of their parallelisms to be sped up. RNS has several advantages, such as the possibility of faster addition and multiplication compared to all other number systems. Moreover, the use of short numbers in RNS computations can significantly reduce the power consumption of digital devices [1]. It is useful in the synthesis of RNS computational devices with parallel structure, such as field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC). All these attractive features increase interest to RNS in the areas where large amounts of computation are needed. The applications of RNS are digital signal processing [2,3,4], cryptography [5,6,7], digital image processing [8], cloud computing [9], Internet of Things [10] and others. In [11], the authors propose a technique to estimate real-valued numbers by means of the Chinese remainder theorem (CRT), employing for this goal a Kroenecker based M-Estimation, to improve robustness. A new method based on the Chinese remainder theorem (CRT) is proposed for absolute position computation in [12]. This has advantages in terms of hardware and flexibility because it does not use memory. The authors of [13] offer to use RNS to improve the performance of the convolutional neural network developed for pattern recognition tasks. Reference [14] describes the method of construction for finite impulse response filers using RNS.
However, the limitations of RNS include some operations such as reverse conversion into positional form, magnitude comparison and division of numbers in RNS [15,16]. These limitations exist because RNS is a non-positional number system, and magnitude comparison of numbers in RNS form is impossible, so the division operation consists of a magnitude comparison operation that is also a problematic operation. Improving the efficiency of the comparison operation in RNS is something that can be used in the development of new approaches to the implementation of other problematic operations in RNS, such as subtraction-based division and the detection of dynamic range overflow. Dynamic range overflow detectors in RNS are widely applied in the design of fault-tolerant systems and secure communication channels [17].
The state-of-the-art in the described problem is as follows. The most common approaches to performing non-modular RNS operations are based on mixed radix conversion (MRC) and the Chinese remainder theorem (CRT) [1,18]. Another class of approaches to perform magnitude comparison in RNS, which is based on the core functions defined from the RNS to the integer [19], was first proposed Akushskii et al. [20]. Recently new alternatives have been developed for the implementation of the non-modular RNS operations problem. These approaches are the use of CRT with fractional values (CRTf) [21] and diagonal function (DF) [22,23]. References [24] and [25] demonstrate that the use of DF has a significant drawback in the necessity to perform modulo sum of quotients (SQ) operations. The authors of these papers show that DF usually does not provide advantages in comparison with MRC and CRT. Therefore, in this paper, we will discuss the issue of constructing RNS with a convenient form of DF, which leads to the calculations modulo 2 n , 2 n 1 or 2 n + 1 since the numbers of this form have very effective methods of hardware implementation, as designed in [26,27,28]. How balanced the moduli set is plays an important role in this method. Table 1 shows samples of known moduli sets.
The proposed approach to the construction of RNS can be effective in those applications in which the comparison operation is a significant part of the calculations. One of the examples of such an application is the motion estimation on video, estimated by using high-efficiency video coding (HEVC/H.265) [38]. Another example of a such application is customized signal processing units. For example, the sorting network uses a large number of comparators and is one of the key elements in electronic finance data management systems, digital computers and communication systems [39]. Due to the excessive number of magnitude comparisons required in sorting a large pool of data, the speed of the magnitude comparator determines the overall delay of the sorting process [35].
The rest of the paper is organized as follows. Section 2 discusses RNS issues, represented numbers, and arithmetic operations in RNS. The Section 3 presents the construction of RNS with a convenient form of DF and the results of the hardware simulation of magnitude comparison and reverse conversion into the positional form using CRT, CRTf, and DF. Section 4 discusses the methods of RNS construction presented in this paper and hardware simulation results. The conclusion of the paper is reported in Section 5.

2. Materials and Methods

2.1. Background on RNS

Numbers in RNS are represented in the form of relatively prime numbers which are called moduli β = { m 1 , , m k } , G C D ( m i , m j ) = 1 , for i j . Any integer number 0 X < M = i = 1 k m i can be uniquely represented in RNS as a tuple { x 1 , x 2 , , x k } , where x i = | X | m i = X   mod   m i . Operations of addition, subtraction, and multiplication in RNS are defined by the formulas showing the carry-free parallel nature of RNS:
A ± B = ( | a 1 ± b 1 | m 1 , , | a n ± b n | m n ) ,   A × B = ( | a 1 × b 1 | m 1 , , | a n × b n | m n )
The reverse conversion of a number X from residues { x 1 , x 2 , , x k } is based on CRT
X = | i = 0 n | | M i 1 | m i x i | m i M i | M ,
where M i = M / m i , γ i = | M i 1 | m i and | M i 1 | m i means a multiplicative inverse of M i modulo m i .
The DF is defined as
D ( X ) = | i = 1 n k i x i | S Q ,
where S Q = i = 1 n M i is called the “diagonal modulus” of the RNS and k i = | m i 1 | S Q . The principles of applying the DF for reverse conversion and numbers comparison are thoroughly shown in [24] and [25]. Reverse conversion using DF can be implemented by the formula
X = M D ( X ) + i = 1 n x i M i S Q ,
In [25], magnitude comparison is presented using DF. The work uses the magnitude comparison Algorithm 1 of X and Y, presented in [22], which relies on the following properties of the DF.
Algorithm 1. Magnitude comparison using DF [22].
Input: X = { x 1 , x 2 , , x n } , Y = { y 1 , y 2 , , y n } , k = { k 1 , , k n } , S Q ;
Variable: D x , D y ;
Calculations:
D x = 0 ; D y = 0 ;
for i = 0 , n 1 ¯ do
D x = | D x + k i x i | S Q ;
D y = | D y + k i y i | S Q ;
end for;
if D x < D y then
return (" X < Y ");
else
if D x > D y then
return (" X > Y ");
else
if x 1 < y 1 then
return (" X < Y ");
else
if x 1 > y 1 then
return (" X > Y ");
else
return (" X = Y ");
end if;
end if;
end if;
end if;
It is obvious that the main obstacle to the development of very-large-scale integration (VLSI) architectures based on the DF is the necessity to perform modulo SQ operations. Below, we show how to construct RNS with a convenient form of DF that leads to modulo 2 n , 2 n 1 or 2 n + 1 computations.

2.2. Construction Methods of RNS with Hardware Efficient DF

The choice of the optimal moduli set is a very important question in RNS theory since it has an impact on performance and the quality of operations. In [26,27,28], authors perform high-speed architectures of modulo 2 n ± 1 adders. The use of moduli 2 n , 2 n 1 or 2 n + 1 allows for there to be an increase in computation performance. In addition, the choice of enough RNS dynamic range is a very important question too. In [40], authors considered the influence of the RNS dynamic range on the quality of image filtering. Therefore, it is necessary to choose optimal moduli sets, so we propose the method of RNS construction with a convenient form of DF.
Let us consider two possible cases.
  • Among the RNS moduli m 1 , m 2 , …, m n there is an even one, and the others are odd. Then among M 1 , M 2 , …, M n there is an odd one, and the others are even and therefore S Q is odd.
  • All RNS moduli m 1 , m 2 , …, m n are odd. Then all M 1 , M 2 , …, M n are odd and parity of S Q is the same as the parity of the number of moduli n .

2.2.1. RNS with Even Module

One can suppose that m 1 , m 2 , …, m n 1 are odd and m n = 2 ρ ( 2 l n + 1 ) is even. We will choose m 1 , m 2 , …, m n in such a way to satisfy S Q = 2 k 1 or S Q = 2 k + 1 . We denote M 0 = m 1 m 2 m n 1 and S 0 = M 0 m 1 + M 0 m 2 + + M 0 m n 1 , thus S Q = S 0 m n + M 0 . If n is odd then S 0 is even and therefore S 0 = 2 ω or S 0 = 2 ω ( 2 l 0 + 1 ) . If n is even then S 0 is odd and S 0 = 2 l 0 + 1 .
If S Q = 2 k 1 then three cases are possible
2 k 1 = M 0 + 2 ω 2 ρ ( 2 l n + 1 )   or
2 k 1 = M 0 + 2 ω ( 2 l 0 + 1 ) 2 ρ ( 2 l n + 1 )   or
2 k 1 = M 0 + ( 2 l 0 + 1 ) 2 ρ ( 2 l n + 1 ) .
Hence
2 k = M 0 + 1 + 2 ω 2 ρ ( 2 l n + 1 )   or  
2 k = M 0 + 1 + 2 ω ( 2 l 0 + 1 ) 2 ρ ( 2 l n + 1 )   or
2 k = M 0 + 1 + ( 2 l 0 + 1 ) 2 ρ ( 2 l n + 1 ) .
We choose M 0 in a way that M 0 = m 1 m 2 m n 1 = 2 t 1 is a composite number and G C D ( m i , m j ) = 1 for i j . Since among the 2 t 1 numbers, there are composite numbers much more than prime numbers, then the choice of M 0 is obviously possible. Therefore
2 k = 2 t + 2 ω 2 ρ ( 2 l n + 1 )   or
2 k = 2 t + 2 ω ( 2 l 0 + 1 ) 2 ρ ( 2 l n + 1 )   or
2 k = 2 t + ( 2 l 0 + 1 ) 2 ρ ( 2 l n + 1 ) .
Hence, since t < k and t ω + ρ we have
2 k t = 1 + 2 ω + ρ t ( 2 l n + 1 )   or
2 k t = 1 + 2 ω + ρ t ( 2 l 0 + 1 ) ( 2 l n + 1 )   or
2 k t = 1 + 2 ρ t ( 2 l 0 + 1 ) ( 2 l n + 1 ) .
Suppose that ω + ρ t = 0 or ρ t = 0 . We have
2 k t = 1 + ( 2 l n + 1 )   or
2 k t = 1 + ( 2 l n + 1 )   or
2 k t = 1 + ( 2 l 0 + 1 ) ( 2 l n + 1 ) .
Hence
2 l n + 1 = 2 j 1 ,   where   j = 1 , 2 , 3 ,
or   2 k t 1 ( mod ( 2 l 0 + 1 ) )
Congruence (21) is solvable due to the fact that G C D ( 2 , 2 l 0 + 1 ) = 1 . If r is an order of 2 modulo 2 l 0 + 1 , then k t = r j , where j = 1 , 2 , , n . Hence 2 l n + 1 = 2 r j 1 2 l 0 + 1 . From this, if it is necessary to find M = m 1 m 2 m n , where m n is even and S Q = 2 k 1 then proceed as follows.
  • Choose a composite M 0 = m 1 m 2 m n 1 = 2 t 1 .
  • Compute S 0 .
  • Consider the possible cases.
    • If S 0 = 2 ω then ρ = t ω , 2 l n + 1 = 2 j 1 , were G C D ( 2 j 1 , m i ) = 1 for i = 1 , 2 , , n 1 . m n = 2 t ω ( 2 j 1 ) , where j = 1 , 2 , 3 , , G C D ( 2 j 1 , m i ) = 1 , i = 1 , 2 , , n 1 .
    • If S 0 = 2 ω ( 2 l 0 + 1 ) then ρ = t ω , 2 l n + 1 = 2 r j 1 2 l 0 + 1 , where G C D ( 2 l n + 1 , m i ) = 1 , i = 1 , 2 , , n 1 , and r is order of 2 modulo 2 l 0 + 1 .
    • If S 0 = 2 l 0 + 1 then ρ = t , 2 l n + 1 = 2 r j 1 2 l 0 + 1 , where G C D ( 2 l n + 1 , m i ) = 1 , i = 1 , 2 , , n 1 , and r is order of 2 modulo 2 l 0 + 1 .
Example 1.
Suppose that M 0 = m 1 m 2 = 3 5 = 2 4 1 , t = 4 . Then S 0 = 3 + 5 = 2 3 , ω = 3 . m 3 = 2 ρ ( 2 l 3 + 1 ) , ρ = 4 3 = 1 . 2 l 3 + 1 = 2 j 1 , j = 1 , 2 , 3 , , G C D ( 2 j 1 , 3 ) = 1 , G C D ( 2 ε j 1 , 5 ) = 1 . Examining a power of two, we have
  • 2 1 1 = 1 , 2 l 3 + 1 = 1 , m 3 = 2 .
  • 2 2 1 = 3 , G C D ( 3 , 3 ) 1 .
  • 2 3 1 = 7 , 2 l 3 + 1 = 7 , m 3 = 14 .
  • 2 4 1 = 15 , G C D ( 15 , 3 ) 1 .
  • 2 5 1 = 31 , 2 l 3 + 1 = 31 , m 3 = 62 etc.
Thus, we obtained the following RNS: { 3 , 5 , 2 } , S Q = 31 = 2 5 1 , { 3 , 5 , 14 } , S Q = 127 = 2 8 1 , { 3 , 5 , 62 } , S Q = 511 = 2 9 1 .
Note. For the case S Q = 2 k + 1 one needs to take M 0 = 2 t + 1 . The conclusions obtained are the same as for S Q = 2 k 1 .
Example 2.
Suppose that M 0 = m 1 m 2 = 3 11 = 2 5 + 1 , t = 5 . Then
  • S 0 = 3 + 11 = 14 = 2 1 7 , ω = 1 , 2 l 0 + 1 = 7 .
  • m 3 = 2 ρ ( 2 l 3 + 1 ) , ρ = 5 1 = 4 , 2 r 1 ( mod 7 ) , r = 3 j .
  • 2 3 1 7 = 1 , 2 l 3 + 1 = 1 , m 3 = 2 4 1 = 16 .
  • 2 6 1 7 = 63 7 = 9 , G C D ( 9 , 3 ) 1 .
  • 2 9 1 7 = 511 7 = 73 , 2 l 3 + 1 = 73 , m 3 = 16 73 = 1168 etc.
Thus we obtained the following RNS: { 3 , 11 , 16 } , S = 257 = 2 8 + 1 , { 3 , 11 , 1168 } , S = 16385 = 2 14 + 1 .

2.2.2. RNS with Odd Moduli

We only consider the most important practical cases, for example, when RNS contains three, four or five moduli [41].
Case 1. RNS with three moduli. In analogy with the above notations M 0 = m 1 m 2 , S 0 = m 1 + m 2 , and S Q = M 0 + S 0 m 3 . One can verify that S 3 ( mod 4 ) . Let us see whether it is possible for the odd m 1 and m 2 to choose such an odd m 3 , such that S Q = 2 k 1 . If S = 2 k 1 then 2 k = S + 1 = M 0 + 1 + S 0 m 3 . It is clear that G C D ( M 0 + 1 , S 0 ) = 2 ω ( 2 l + 1 ) . If 2 l + 1 1 , then the right part of equality
2 k = M 0 + 1 + S 0 m 3   or
divisible by 2 l + 1 , and left part of Equality (22) is not divisible by 2 l + 1 . This means that for the satisfy Equality (22) it is necessary that
G C D ( M 0 + 1 , S 0 ) = 2 ω .
Under Condition (23) we have
2 k ω = M 0 + 1 2 ω + S 0 2 ω m 3 ,
where G C D ( M 0 + 1 2 ω , S 0 2 ω ) = 1 . If one of the numbers M 0 + 1 2 ω or S 0 2 ω is even, then (24) is impossible. Thus, for the validity of (24), it is necessary that both numbers M 0 + 1 2 ω and S 0 2 ω are odd.
Suppose that both conditions are performed.
  • G C D ( M 0 + 1 , S 0 ) = 2 ω .
  • M 0 + 1 2 ω and S 0 2 ω are odd.
Let us write (24) as a congruence
2 k ω M 0 + 1 2 ω ( mod   S 0 2 ω ) .
If S 0 2 ω is prime and 2 is a primitive root modulo S 0 2 ω then Congruence (25) will have solutions concerning k ω by mod ( S 0 2 ω 1 ) . Suppose that ρ is the smallest non-negative solution of Congruence (25). Then
k ω = ρ + ( S 0 2 ω 1 ) t ,   t = 0 , 1 , 2 ,
And therefore 2 ρ + ( S 0 2 ω 1 ) t = M 0 + 1 2 ω + S 0 2 ω m 3 . Hence S 0 2 ω m 3 = 2 ρ + ( S 0 2 ω 1 ) t M 0 + 1 2 ω . This means that
m 3 = 2 ρ + ( S 0 2 ω 1 ) t M 0 + 1 2 ω ( S 0 2 ω ) ,   t = 0 , 1 , 2 ,
According to the RNS definition, the number m 3 must be relatively prime with m 1 and m 2 .
If the number S 0 2 ω is prime and 2 is not a primitive root modulo S 0 2 ω then Congruence (25) may have no solutions. In addition, Congruence (25) may have no solutions if S 0 2 ω is a composite number. Thus, to construct RNS with three odd moduli and S Q = 2 k 1 , four conditions must be fulfilled.
  • G C D ( m 1 m 2 + 1 , m 1 + m 2 ) = 2 ω .
  • m 1 m 2 + 1 2 ω is odd.
  • m 1 + m 2 2 ω is prime and not equal to 2.
  • 2 is a primitive root modulo mod m 1 + m 2 2 ω .
Note that these conditions are not sufficient, since the numbers m 3 found by Formula (27) may not be relatively prime with m 1 or m 2 .
Example 3.
Suppose that m 1 = 3 , m 2 = 7 . Then G C D ( 3 7 + 1 , 3 + 7 ) = G C D ( 12 , 10 ) = 2 , 3 7 + 1 2 = 11 is odd, 3 + 7 2 = 5 is prime, 2 is a primitive root modulo 5.
From the equality 2 k 1 = 11 + 5 m 3 , we obtain a congruence 2 k 1 11 ( mod 5 ) which implies k 1 = 4 t , t = 1 , 2 , or 2 4 t = 11 + 5 m 3 , m 3 = 2 4 t 11 5 .
Testing of the value t gives the following result:
  • t = 1 gives m 3 = 1 < 2 ,
  • t = 2 gives m 3 = 256 11 5 = 49 , G C D ( 49 , 7 ) 1 ,
  • t = 3 gives m 3 = 4096 11 5 = 817 , G C D ( 817 , 3 ) = 1 , G C D ( 817 , 7 ) = 1 .
So, we get the RNS { 3 , 7 , 817 } with S Q = 8191 = 2 13 1 .
Case 2. RNS with 4 moduli. In this case, S Q is even. Consider the problem: for m 1 , m 2 , m 3 choose m 4 in such a way as to S Q = 2 k . If we denote M 0 = m 1 m 2 m 3 , S 0 = m 1 m 2 + m 1 m 3 + m 2 m 3 then S = M 0 + S 0 m 4 . It is clear that G C D ( M 0 , S 0 ) = 1 . From the equality 2 k = M 0 + S 0 m 4 follows
2 k M 0 ( mod S 0 ) .
If S 0 is prime and 2 is a primitive root modulo S 0 then Congruence (28) has a solution on k . Suppose that ρ is the smallest non-negative solution of ongruence (28). Then k = ρ + ( S 0 1 ) t , t = 0 , 1 , 2 , . It means that 2 ρ + ( S 0 1 ) t = M 0 + S 0 m 4 from which
m 4 = 2 ρ + ( S 0 1 ) t M 0 S 0 ,   t = 0 , 1 , 2 ,
Since G C D ( 2 ρ + ( S 0 1 ) t , m 1 ) = G C D ( 2 ρ + ( S 0 1 ) t , m 2 ) = G C D ( 2 ρ + ( S 0 1 ) t , m 3 ) = 1 then for any t = 0 , 1 , 2 , it will be obtained that the number m 4 is relatively prime with m 1 , m 2 and m 3 . If S 0 is a composite number, then Congruence (28) may have no solutions. If S 0 is prime and 2 is not a primitive root modulo S 0 then Congruence (28) may have no solutions too. In other words, to construct RNS with four odd moduli and S Q = 2 k , two conditions must be fulfilled.
  • S 0 = m 1 m 2 + ( m 1 + m 2 ) m 3 is prime.
  • 2 is a primitive root modulo S 0
Example 4.
Suppose that m 1 = 3 , m 2 = 7 , m 3 = 11 . In this case M 0 = m 1 m 2 m 3 = 231 and S 0 = m 1 m 2 + ( m 1 + m 2 ) m 3 = 131 is prime. Two is a primitive root modulo 131. From the equality 2 k = 231 + 131 m 4 follows congruence 2 k 100 ( mod 131 ) . The least nonnegative solution of this congruence is 94 , therefore k = 94 + 130 t , t = 0 , 1 , 2 ,
Hence m 4 = 2 94 + 130 t 231 131 , t = 0 , 1 , 2 , For t = 0 we have m 4 = 2 94 231 131 .
We received RNS { 3 , 7 , 11 , 2 94 231 131 } with S Q = 2 94 .
Case 3. RNS with 5 moduli. In analogy with the above notations, we denote M 0 = m 1 m 2 m 4 m 4 and S 0 = m 1 m 2 m 3 + m 1 m 2 m 4 + m 1 m 3 m 4 + m 2 m 3 m 4 and S = M 0 + S 0 m 5 . One can verify that S 1 ( mod 4 ) . Let us see whether it is possible for the odd m 1 , m 2 , m 3 and m 4 choose such an odd m 5 that the S Q = 2 k + 1 .
If S = 2 k + 1 then 2 k = S 1 = M 0 1 + S 0 m 5 . Similar to case 1, the equality
2 k = M 0 1 + S 0 m 5
is possible if:
  • G C D ( M 0 1 , S 0 ) = 2 ω ;.
  • M 0 1 2 ω and S 0 2 ω are odd
Then 2 k ω = M 0 1 2 ω + S 0 2 ω m 5 or
2 k ω M 0 1 2 ω ( mod   S 0 2 ω ) .
If S 0 2 ω is prime and 2 is a primitive root modulo S 0 2 ω then Congruence (31) has solutions concerning k ω modulo S 0 2 ω 1 . Suppose that ρ is the smallest nonnegative such a solution. Then 2 ρ + ( S 0 ω 1 ) t = M 0 1 2 ω + S 0 2 ω m 5 and t = 0 , 1 , 2 ,
Hence m 5 = 2 ρ + ( S 0 ω 1 ) t M 0 1 2 ω ( S 0 2 ω ) wherein t should be chosen so that m 5 will be relatively prime with m 1 , m 2 , m 3 and m 4 .
Example 5.
Suppose that m 1 = 3 , m 2 = 5 , m 3 = 7 and m 4 = 11 . Then
  • M 0 = 1155 , M 0 1 = 1154 , S 0 = 886 .
  • G C D ( M 0 1 , S 0 ) = G C D ( 1154 , 886 ) = 2 .
  • M 0 1 2 = 577 is odd, S 0 2 = 443 is prime and 2 is a primitive root modulo 443.
Hence, we can choose such an odd number as m 5 that the following S Q = 2 k + 1 . From the equality 2 k 1 = 577 + 443 m 5 , we obtain 2 k 1 557 ( mod 443 ) , from which k 1 = 53 + 443 t , t = 0 , 1 , 2 ,
Hence m 5 = 2 53 + 443 t 577 443 , t = 0 , 1 , 2 , where t needs to be chosen such that G C D ( 3 , m 5 ) = G C D ( 5 , m 5 ) = G C D ( 7 , m 5 ) = G C D ( 11 , m 5 ) = 1 .
The smallest t = 3 where this condition is performed t = 3 , therefore m 5 = 2 1382 577 443 . We obtain RNS { 3 , 5 , 7 , 11 , 2 1382 577 443 } with S Q = 2 1383 + 1 .
The above methods for constructing RNS with a diagonal function of the 2 n , 2 n 1 and 2 n + 1 forms allow us to develop efficient circuits for comparing numbers and reverse conversion. In the rest of this article, we demonstrate examples of such circuits and show the advantages of their technical characteristics in comparison with the known analogs.

3. Results

The goal of modeling is a comparison of the methods of implementing the numbers comparison operation and reverse RNS to binary conversion by the proposed methods, a method based on CRT [18] and a method based on CRTf [21]. We use { 3 , 5 , 14 } , { 7 , 9 , 124 } and { 5 , 29 , 93 , 313 } moduli sets, because their DF has form 2 n 1 and 2 n which are low-cost RNS [42]. Figure 1 shows the circuit for numbers comparison in RNS with DF of the form 2 n 1 . The bit-widths of the RNS moduli { m 1 , m 2 , m 3 } are denoted as a 1 , a 2 , a 3 . Multipliers by constants | X i k i | 2 n 1 , i = 1 , 2 , 3 modulo 2 n 1 implement the generation of partial products modulo 2 n 1 . A modulo 2 n 1 compressor is implemented as in [21]. Kogge–Stone adder with end-around carry (KSA-EAC) uses for modulo 2 n 1 addition, and it is implemented as in [27]. The circuit for numbers comparison in RNS with DF of the form 2 n has a similar structure to that presented in Figure 1, but it should have four inputs for compared numbers X and Y , since in the theoretical part, we demonstrate that only RNS with four modules can have DF of the form 2 n . In addition, compressors and Kogge-Stone adders (KSAs) must implement modulo 2 n operations that are achieved by simply dropping the carrying of the most significant bit (MSB).
Figure 2 shows the reverse conversion circuit for RNS with the DF of the form 2 n 1 . The bit-widths of the RNS moduli { m 1 , m 2 , m 3 } are denoted as a 1 , a 2 , a 3 . Multipliers by constants | X i k i | 2 n 1 , i = 1 , 2 , 3 modulo 2 n 1 , modulo 2 n 1 compressor and KSA-EAC blocks are realized as in Figure 1. The rest of the blocks are implemented in standard binary form. The symbol a R denotes the bit-width of RNS range and symbol a t denotes the bit-width of the value M D ( X ) + i = 1 n x i M i . Division by S Q is implemented as multiplication by multiplicative inverse S Q modulo 2 a t . The output of the circuit presented in Figure 2 is a group of a R most significant bits (MSBs) of the last KSA output. The reverse converter circuit for RNS with a DF of the form 2 n has a similar structure to that presented in Figure 2, with differences similar to the comparator described above.
Also, modeling was done to compare the proposed moduli sets with balanced RNS moduli sets. The following types of moduli sets were chosen for the simulation: { 2 n 1 , 2 n , 2 n + 1 } [29,30], { 2 n 1 , 2 n + k , 2 n + 1 } [31], { 2 n 1 , 2 n , 2 n + 1 , 2 n + 1 + 1 } [34], { 2 n 1 , 2 n + 1 , 2 n ± 1 1 , 2 n + k } [35].
All simulated circuits were described in very high speed integrated circuit (VHSIC) hardware description language (VHDL). Hardware modeling was performed on Xilinx Artix 7 xc7a200tfbg484-2 in Vivado 2016.3 and the strategy of synthesis was highly area optimized. The modeling results are presented in Table 2, Table 3 and Table 4 and show time, hardware costs and the area·delay (A·D) metrics calculated as a product of delay by a number of look up tables (LUTs).
A simulation of magnitude comparison shows that for the { 3 , 5 , 14 } moduli set, the method using CRTf works 21.22 % faster than the proposed method, and 29 , 93 % faster than the method using CRT. However, the proposed method uses 34.91 % fewer hardware resources than CRTf, and 18.52 % less than CRT. For { 7 , 9 , 124 } , the circuit, based on CRTf, works 5.98 % faster than the circuit, which is based on the proposed method, and 30.96 % faster than the circuit which is based on CRT. Furthermore, the circuit, based on the proposed method, uses 17.02 % fewer hardware resources than CRTf method and 49.72 % less than CRT. For { 5 , 29 , 93 , 313 } , the proposed method works 4.92 % faster than the method using CRTf, and 21.95 % faster than the method using CRT. Moreover, the proposed method uses 36.38 % fewer hardware resources than the method using CRTf, and two times fewer resources than the method using CRT. Thus, for the magnitude comparison operation, the proposed method reduces the consumption of hardware resources compared tp known methods. In addition, in the case of using the moduli set { 5 , 29 , 93 , 313 } the proposed method also reduced the delay of the devices. Table 2 also demonstrates the advantages of the proposed method in A·D metrics and power consumption.
A simulation of reverse RNS to binary conversion shows that for the { 3 , 5 , 14 } moduli set method using CRTf works 19.12 % faster than the proposed method, and 0 , 29 % faster than the method using CRT. Moreover, CRTf method uses 43.81 % fewer hardware resources than the proposed method and 6.35 % less than CRT. For { 7 , 9 , 124 } , circuit, based on CRTf, works 1.33 % faster than the circuit based on the proposed method, and 13.82 % faster than circuit based on CRT. Furthermore, the circuit based on the proposed method uses 20.39 % fewer hardware resources than CRTf method and 1.38 % less than CRT. For { 5 , 29 , 93 , 313 } , the method using CRTf works 4.47 % faster than the proposed method, and 20.79 % faster than the method using CRT. Moreover, it uses 12.30 % fewer hardware resources than the proposed method and 7.72 % fewer resources than the method using CRT. Therefore, the proposed method allows us to reduce hardware resources for the moduli set { 7 , 9 , 124 } compared to known methods.
For the { 3 , 5 , 14 } moduli set, the RNS dynamic range is equal to M = 210 . Due to comparing the performance of the circuit using the proposed moduli set with a circuit using known common moduli sets, two balanced moduli sets were chosen: { 2 n 1 , 2 n , 2 n + 1 } , n = 3 [29,30] and { 2 n 1 , 2 n + k , 2 n + 1 } , n = 2 , k = 2 [26], which are close to this dynamic range. Modeling of the magnitude comparison showed that the circuit using the proposed { 3 , 5 , 14 } moduli set works 24.73 % faster than { 2 n 1 , 2 n , 2 n + 1 } , n = 3 moduli set and 15.47 % faster than { 2 n 1 , 2 n + k , 2 n + 1 } , n = 2 , k = 2 moduli set. Moreover, the proposed moduli set uses 2.5 times fewer hardware resources than { 2 n 1 , 2 n , 2 n + 1 } , n = 3 moduli set and 26.67 % less than { 2 n 1 , 2 n + k , 2 n + 1 } , n = 2 , k = 2 moduli set. Hardware simulation of reverse RNS to binary conversion showed that using the proposed moduli set { 3 , 5 , 14 } requires 25.22 % fewer time costs than the { 2 n 1 , 2 n , 2 n + 1 } , n = 3 moduli set and 10.32 % less than the { 2 n 1 , 2 n + k , 2 n + 1 } , n = 2 , k = 2 moduli set. Although the proposed moduli set uses 13.33 % more hardware resources than { 2 n 1 , 2 n + k , 2 n + 1 } , n = 2 , k = 2 moduli set, it uses 37.87 % less than the { 2 n 1 , 2 n , 2 n + 1 } , n = 3 moduli set.
For the proposed { 7 , 9 , 124 } moduli set, the dynamic RNS range is equal to M = 7812 . For this dynamic range, two known balanced moduli sets were chosen: { 2 n 1 , 2 n , 2 n + 1 } , n = 4 [29,30] and { 2 n 1 , 2 n , 2 n + 1 , 2 n + 1 + 1 } , n = 3 [34]. Modeling of magnitude comparison showed that circuit using proposed { 7 , 9 , 124 } moduli set works 20.94 % faster than the { 2 n 1 , 2 n , 2 n + 1 } , n = 4 moduli set and 29.20 % faster than the { 2 n 1 , 2 n , 2 n + 1 , 2 n + 1 + 1 } , n = 3 moduli set. In addition, the proposed moduli set uses 0.73 % fewer hardware resources than the { 2 n 1 , 2 n , 2 n + 1 } , n = 4 moduli set and 36.06 % less than the { 2 n 1 , 2 n , 2 n + 1 , 2 n + 1 + 1 } , n = 3 moduli set. Hardware simulation of reverse RNS to binary conversion showed that using the proposed moduli set { 7 , 9 , 124 } requires 14.66 % less time cost than the { 2 n 1 , 2 n , 2 n + 1 } , n = 4 moduli set and 33.07 % less than the { 2 n 1 , 2 n , 2 n + 1 } , n = 4 moduli set. Although the proposed moduli set uses 7.72 % more hardware resources than the { 2 n 1 , 2 n , 2 n + 1 } , n = 4 moduli set, it uses 36.24 % less than the { 2 n 1 , 2 n , 2 n + 1 } , n = 4 moduli set.
For the proposed { 5 , 29 , 93 , 313 } moduli set, the dynamic range of RNS was equal to M = 4220805 . For this dynamic range, two known balanced moduli sets were chosen: { 2 n 1 , 2 n + 1 , 2 n + 1 1 , 2 n + k } , n = 4 , k = 4 and { 2 n 1 , 2 n + 1 , 2 n 1 1 , 2 n + k } , n = 6 , k = 0 [33]. Modeling of the magnitude comparison showed that the circuit using the proposed { 5 , 29 , 93 , 313 } moduli set works 28.06 % faster than the { 2 n 1 , 2 n + 1 , 2 n + 1 1 , 2 n + k } , n = 4 , k = 4 moduli set and 2 times faster than the { 2 n 1 , 2 n + 1 , 2 n 1 1 , 2 n + k } , n = 6 , k = 0 moduli set. Although the proposed moduli set uses 44.81 % more hardware resources than the { 2 n 1 , 2 n + 1 , 2 n + 1 1 , 2 n + k } , n = 4 , k = 4 moduli set, it uses 3 times less than the { 2 n 1 , 2 n + 1 , 2 n 1 1 , 2 n + k } , n = 6 , k = 0 moduli set. Hardware simulation of reverse RNS to binary conversion showed that the using of the proposed moduli set { 5 , 29 , 93 , 313 } requires 27.16 % fewer time costs than the { 2 n 1 , 2 n + 1 , 2 n + 1 1 , 2 n + k } , n = 4 , k = 4 moduli set and 42.91 % less than the { 2 n 1 , 2 n + 1 , 2 n 1 1 , 2 n + k } , n = 6 , k = 0 moduli set. Although the proposed moduli set uses 45.47 % more hardware resources than the { 2 n 1 , 2 n + 1 , 2 n + 1 1 , 2 n + k } , n = 4 , k = 4 moduli set, it uses 29.88 % less than the { 2 n 1 , 2 n + 1 , 2 n 1 1 , 2 n + k } , n = 6 , k = 0 moduli set.
Thus, in comparison to known balanced moduli sets, the proposed moduli sets reduce the delay of magnitude comparison and reverse conversion in devices. In case of operation magnitude comparison, using the proposed moduli sets, { 3 , 5 , 14 } and { 7 , 9 , 124 } , reduces the use of hardware resources in devices.
The experimentally obtained results showed that the approach developed in this paper allows us to improve two problem operations in the RNS: the comparison of numbers and reverse conversion. The proposed devices for such operations can be used in those applications of the RNS for which these operations are the most important, for example, in video processing systems, sorting networks, etc.

4. Discussion

The results obtained in Section 3 are summarized in Table 5. The main conclusion we can assume is that the RNS construction with all cases S Q = 2 n , S Q = 2 n 1 , S Q = 2 n + 1 is principally possible. The cases S Q = 2 n 1 and S Q = 2 n + 1 for RNS with one even module are easiest for practical implementation. All cases for RNS with all odd moduli are more complicated. However, among these cases, there is one particularly attractive option. As we have demonstrated, there is the possibility of RNS constructing with S Q = 2 n . This case requires the use of four odd RNS moduli.
According to the proposed construction method of RNS with a convenient form of DF, moduli sets with three and four moduli were chosen: { 3 , 5 , 14 } , { 7 , 9 , 124 } and { 5 , 29 , 93 , 913 } . We performed the hardware simulation of magnitude comparison and reverse RNS to binary conversion using RNS with the presented moduli sets and using different approaches to perform the non-modulo comparison operation: the proposed method, method [18], and method [21]. The hardware simulation results of magnitude comparison show that, for three moduli, the use of the proposed method reduces hardware resources, and the use of method [21] reduces circuit delay. For four moduli, the proposed method reduces both time and hardware costs. The modeling of reverse RNS to binary conversion shows that method [21] works faster and requires fewer hardware resources than the others considered methods. Comparison of the simulation results of proposed moduli sets and balanced moduli sets shows that the use of the proposed moduli sets reduces circuit delay, although, in several cases, it required more hardware resources than balanced moduli sets.

5. Conclusions

The paper concerns the problem of RNS construction with convenient forms of DF. We propose several methods of RNS construction with SQ forms 2 n , 2 n 1 and 2 n + 1 . The use of these forms of moduli allow for developing efficient methods of hardware implementation. We performed hardware implementation of magnitude comparison and reverse RNS to binary conversion using the proposed method, method [18] method [21]. A comparison of the implementation results shows that using the proposed method is effective for magnitude comparison operation, but for the reverse RNS to binary conversion operation, method [21] performs better modeling results than the proposed method and method [18]. In addition, according to the simulation results, the proposed moduli sets reduce circuit delay in comparison with balanced moduli sets, although, in several cases, require more hardware resources than balanced moduli sets.
The proposed method allows more efficient and problematic operations in RNS, such as sign detection, number comparison, and division, to be performed. It can be used in the development of video processing systems and customized signal processing units using RNS.

Author Contributions

Conceptualization, M.V.; Data curation, N.C.; Formal analysis, D.B.; Investigation, P.L., G.V. and D.K.; Methodology, N.S.; Project administration, P.L.; Resources, D.K. and D.B.; Software, P.L., G.V. and N.S.; Validation, M.V., N.C., P.L. and D.K.; Visualization, G.V., N.S., D.B.; Writing—original draft, M.V. and N.C.; Writing—review & editing, D.K., and P.L.

Funding

The research is supported by the grant of the Russian Science Foundation (Project No. 19-19-00566).

Conflicts of Interest

The authors declare no conflict of interest.

References

  1. Akkal, M.; Siy, P. A new mixed radix conversion algorithm MRC-II. J. Syst. Archit. 2007, 53, 577–586. [Google Scholar] [CrossRef]
  2. Ramirez, J.; Garcia, A.; Lopez-Buedo, S.; Lloris, A. RNS-enabled digital signal processor design. Electron. Lett. 2002, 38, 266–268. [Google Scholar] [CrossRef]
  3. Chang, C.; Molahosseini, A.S.; Zarandi, A.A.E.; Tay, T.F. Residue number systems: A new paradigm to datapath optimization for low-power and high-performance digital signal processing applications. IEEE Circuits Syst. Mag. 2015, 15, 26–44. [Google Scholar] [CrossRef]
  4. Kaplun, D.; Butusov, D.; Ostrovskii, V.; Veligosha, A.; Gulvanskii, V. Optimization of the FIR filter structure in finite residue field algebra. Electronics 2018, 7, 372. [Google Scholar] [CrossRef]
  5. Esmaeildoust, M.; Schinianakis, D.; Javashi, H.; Stouraitis, T.; Navi, K. Efficient RNS implementation of elliptic curve point multiplication GF(p). IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2013, 21, 1545–1549. [Google Scholar] [CrossRef]
  6. Bajard, J.-C.; Imbert, L. A full RNS implementation of RSA. IEEE Trans. Comput. 2004, 53, 769–774. [Google Scholar] [CrossRef]
  7. Sousa, L.; Antao, S.; Martins, P. Combining residue arithmetic to design efficient cryptographic circuits and systems. IEEE Circuits Syst. Mag. 2016, 16, 6–32. [Google Scholar] [CrossRef]
  8. Chervyakov, N.I.; Lyakhov, P.A.; Babenko, M.G. Digital filtering of images in a residue number system using finite-field wavelets. Autom. Control Comput. Sci. 2014, 48, 180–189. [Google Scholar] [CrossRef]
  9. Kar, A.; Sur, K.; Godara, S.; Basak, S.; Mukherjee, D.; Sukla, A.S.; Das, R.; Choudhury, R. Security in cloud storage: An enhanced technique of data storage in cloud using RNS. In Proceedings of the IEEE 7th Annual Ubiquitous Computing, Electronics & Mobile Communication Conference (UEMCON), New York, NY, USA, 20–22 October 2016; pp. 1–4. [Google Scholar]
  10. Navi, K.; Esmaeildoust, M.; Molahosseini, A.S. A general reverse converter architecture with low complexity and high performance. IEICE Trans. Inf. Syst. 2011, 94, 264–273. [Google Scholar] [CrossRef]
  11. Milanezi Junior, J.; da Costa, J.P.C.L.; Römer, F.; Miranda, R.K.; Marinho, M.A.M.; Del Galdo, G. M-estimator based Chinese remainder theorem with few remainders using a kroenecker product based mapping vector. Digit. Signal Process. 2019, 87, 60–74. [Google Scholar] [CrossRef]
  12. Cardarilli, G.C.; Di Nunzio, L.; Fazzolari, R.; Gerardi, L.; Re, M.; Campolo, G.; Cascone, D. A new electric encoder position estimator based on the Chinese Remainder Theorem for the CMG performance improvements. In Proceedings of the 2017 IEEE International Symposium on Circuits and Systems (ISCAS), New York, NY, USA, 28–31 May 2017; pp. 1–4. [Google Scholar]
  13. Chervyakov, N.I.; Lyakhov, P.A.; Valueva, M.V. Increasing of convolutional neural network performance using residue number system. In Proceedings of the 2017 IEEE International Multi-Conference on Engineering, Computer and Information Sciences (SIBIRCON), New York, NY, USA, 18–22 September 2017; pp. 135–140. [Google Scholar]
  14. Cardarilli, G.C.; Del Re, A.; Nannarelli, A.; Re, M. Impact of RNS coding overhead on FIR filters performance. In Proceedings of the 2007 Conference Record of the Forty-First Asilomar Conference on Signals, Systems and Computers, New York, NY, USA, 4–7 November 2007; pp. 1426–1429. [Google Scholar]
  15. Chang, C.; Lee, W.; Liu, Y.; Goi, B.; Phan, R.C.-W. Signature gateway: Offloading signature generation to IoT gateway accelerated by GPU. IEEE Internet Things J. 2019, 6, 4448–4461. [Google Scholar] [CrossRef]
  16. Chervyakov, N.I.; Babenko, M.G.; Lyakhov, P.A.; Lavrinenko, I.N. An approximate method for comparing modular numbers and its application to the division of numbers in residue number systems. Cybern. Syst. Anal. 2014, 50, 977–984. [Google Scholar] [CrossRef]
  17. Selvam, R.; Tyagi, A. Power side channel resistance of RNS secure logic. In Proceedings of the 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID), New York, NY, USA, 6–10 January 2018; pp. 143–148. [Google Scholar]
  18. Mohan, P.V.A. Residue Number Systems: Theory and Applications; Birkhauser: Basel, Switzerland, 2016; ISBN 9783319413853. [Google Scholar]
  19. Gonnella, J. The application of core functions to residue number system. IEEE Trans. Signal Process. 1991, 39, 69–75. [Google Scholar] [CrossRef]
  20. Akushskii, I.J.; Burcev, V.M.; Pak, I.T. A new positional characteristic of nonpositional codes and its applications. Coding Theory Optim. Complex Syst. 1977, 8–16. [Google Scholar]
  21. Matos, R.; Paludo, R.; Chervyakov, N.; Lyakhov, P.A.; Pettenghi, H. Efficient implementation of modular multiplication by constants applied to RNS reverse converters. In Proceedings of the 2017 IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore, MD, USA, 28–31 May 2017; pp. 1–4. [Google Scholar]
  22. Dimauro, G.; Impedovo, S.; Pirlo, G. A new technique for fast number comparison in the residue number system. IEEE Trans. Comput. 1993, 42, 608–612. [Google Scholar] [CrossRef]
  23. Dimauro, G.; Impedovo, S.; Pirlo, G.; Salzo, A. RNS architectures for the implementation of the ‘diagonal function’. Inf. Process. Lett. 2000, 73, 189–198. [Google Scholar] [CrossRef]
  24. Mohan, P.V.A. RNS to binary conversion using diagonal function and pirlo and impedovo monotonic function. Circuits Syst. Signal Process. 2015, 35, 1–14. [Google Scholar] [CrossRef]
  25. Piestrak, S.J. A note on RNS architectures for the implementation of the diagonal function. Inf. Process. Lett. 2015, 115, 453–457. [Google Scholar] [CrossRef]
  26. Kalampoukas, L.; Nikolos, D.; Efstathiou, C.; Vergos, H.T.; Kalamatianos, J. High-speed parallel-prefix modulo 2n − 1 Adders. IEEE Trans. Comput. 2000, 49, 673–680. [Google Scholar] [CrossRef]
  27. Efstathiou, C.; Vergos, H.T.; Nikolos, D. Fast parallel-prefix Modulo 2n + 1 Adders. IEEE Trans. Comput. 2004, 53, 1211–1216. [Google Scholar] [CrossRef]
  28. Vergos, H.T.; Dimitrakopoulos, G. On Modulo 2n + 1 Adder design. IEEE Trans. Comput. 2012, 61, 173–186. [Google Scholar] [CrossRef]
  29. Chaves, R.; Sousa, L. Improving residue number system multiplication with more balanced moduli sets and enhanced modular arithmetic structures. IET Comput. Digit. Tech. 2007, 1, 472. [Google Scholar] [CrossRef]
  30. Jaberipur, G.; Nejati, S. Balanced minimal latency RNS addition for moduli set {2n − 1, 2n, 2n + 1}. In Proceedings of the 18th International Conference on Systems, Signals and Image Processing, Sarajevo, Bosnia and Herzegovina, 16–18 June 2011; pp. 1–7. [Google Scholar]
  31. Hiasat, A. Efficient RNS Scalers for the extended three-moduli set {2n − 1, 2n+p, 2n + 1}. IEEE Trans. Comput. 2017, 66, 1253–1260. [Google Scholar] [CrossRef]
  32. Patronik, P.; Piestrak, S.J. Design of reverse converters for the new RNS moduli set {2n + 1, 2n − 1, 2n, 2n−1 + 1} (n odd). IEEE Trans. Circuits Syst. I Regul. Pap. 2014, 61, 3436–3449. [Google Scholar] [CrossRef]
  33. Hiasat, A. A reverse converter and sign detectors for an extended RNS five-moduli set. IEEE Trans. Circuits Syst. I Regul. Pap. 2017, 64, 111–121. [Google Scholar] [CrossRef]
  34. Mohan, P.V.A.; Premkumar, A.B. RNS-to-Binary converters for two four-moduli sets {2n + 1, 2n − 1, 2n, 2n−1 − 1} and {2n + 1, 2n − 1, 2n, 2n+1 + 1}. IEEE Trans. Circuits Syst. I Regul. Pap. 2007, 54, 1245–1254. [Google Scholar] [CrossRef]
  35. Kumar, S.; Chang, C.-H.; Tay, T.F. New algorithm for signed integer comparison in {2n+k, 2n − 1, 2n + 1, 2n±1 − 1} and its efficient hardware implementation. IEEE Trans. Circuits Syst. I Regul. Pap. 2017, 64, 1481–1493. [Google Scholar] [CrossRef]
  36. Kumar, S.; Chang, C.-H. A scaling-assisted signed integer comparator for the balanced five-moduli set RNS {2n − 1, 2n, 2n + 1, 2n+1 − 1, 2n−1 − 1}. IEEE Trans. Very Large Scale Integr. Syst. 2017, 25, 3521–3533. [Google Scholar] [CrossRef]
  37. Skavantzos, A.; Abdallah, M.; Stouraitis, T.; Schinianakis, D. Design of a balanced 8-modulus RNS. In Proceedings of the 2009 16th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2009), New York, NY, USA, 13–16 December 2009; pp. 61–64. [Google Scholar]
  38. Vayalil, N.C.; Paul, M.; Kong, Y. A residue number system hardware design of fast-search variable-motion-estimation accelerator for HEVC/H.265. IEEE Trans. Circuits Syst. Video Technol. 2019, 29, 572–581. [Google Scholar] [CrossRef]
  39. Cheng, S.W. A high-speed magnitude comparator with small transistor count. In Proceedings of the 10th IEEE International Conference on Electronics, Circuits and Systems, 2003 (ICECS 2003), New York, NY, USA, 14–17 December 2003; pp. 1168–1171. [Google Scholar]
  40. Chervyakov, N.I.; Lyakhov, P.A.; Kalita, D.I.; Shulzhenko, K.S. Effect of RNS dynamic range on grayscale images filtering. In Proceedings of the XV International Symposium Problems of Redundancy in Information and Control Systems (REDUNDANCY), St. Petersburg, Russia, 26–29 September 2016; pp. 33–37. [Google Scholar]
  41. Molahosseini, A.S.; Sorouri, S.; Zarandi, A.A.E. Research challenges in next-generation residue number system architectures. In Proceedings of the IEEE 7th International Conference on Computer Science & Education (ICCSE), Melbourne, VIC, Australia, 14–17 July 2012; pp. 1658–1661. [Google Scholar]
  42. Parhami, B. Computer Arithmetic: Algorithms and Hardware Designs; Oxford University Press: Oxford, UK, 2010; ISBN 9780195328486. [Google Scholar]
Figure 1. Magnitude comparison circuit using the diagonal function (DF) of the form 2 n 1 .
Figure 1. Magnitude comparison circuit using the diagonal function (DF) of the form 2 n 1 .
Electronics 08 00694 g001
Figure 2. Reverse conversion circuit for the residue number system (RNS) with a DF of the form 2 n 1 .
Figure 2. Reverse conversion circuit for the residue number system (RNS) with a DF of the form 2 n 1 .
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Table 1. Known balanced moduli sets.
Table 1. Known balanced moduli sets.
Number of ModulesModuli SetConditionReferences
3 { 2 n 1 , 2 n , 2 n + 1 } [29,30]
{ 2 n 1 , 2 n + p , 2 n + 1 } [31]
{ 2 2 n + p , 2 2 n 1 , 2 2 n + 1 } n odd, p n 5 2 [32]
4 { 2 n 1 , 2 n , 2 n + 1 , 2 n 1 1 } n even[33]
{ 2 n + 1 , 2 n 1 , 2 n , 2 n 1 + 1 } n odd[32]
{ 2 n + 1 , 2 n 1 , 2 n , 2 n + 1 + 1 } n odd[34]
{ 2 n + k , 2 n 1 , 2 n + 1 , 2 n ± 1 1 } n even, k [ 0 , n ] [35]
5 { 2 n 1 , 2 n , 2 n + 1 , 2 n + 1 1 , 2 n 1 1 } n even[36]
{ 2 2 n + p , 2 n 1 , 2 n + 1 , 2 n 2 n + 1 2 + 1 , 2 n + 2 n + 1 2 + 1 } n odd, p n 5 2 [33]
8 { 2 n 5 1 , 2 n 3 1 , 2 n 3 + 1 , 2 n 2 + 1 , 2 n 1 1 , 2 n 1 + 1 , 2 n , 2 n + 1 } n = 2 k , k 4 [37]
Table 2. Modeling results of the circuit of magnitude comparison.
Table 2. Modeling results of the circuit of magnitude comparison.
Moduli SetKnown MethodsProposed Method
CRT [18]CRTf [21]
Delay, ns { 3 , 5 , 14 } 10.9617.6809.749
{ 7 , 9 , 124 } 16.11011.12311.830
{ 5 , 29 , 93 , 313 } 15.36312.61111.991
LUTs { 3 , 5 , 14 } 135169110
{ 7 , 9 , 124 } 543329273
{ 5 , 29 , 93 , 313 } 1,141863549
A·D { 3 , 5 , 14 } 147912971072
{ 7 , 9 , 124 } 874736593229
{ 5 , 29 , 93 , 313 } 17529108836583
Power, W { 3 , 5 , 14 } 4.0615.7574.581
{ 7 , 9 , 124 } 21.75113.92911.840
{ 5 , 29 , 93 , 313 } 40.95047.12824.733
Table 3. Modeling results of the circuit of reverse RNS to binary conversion.
Table 3. Modeling results of the circuit of reverse RNS to binary conversion.
Moduli SetKnown MethodsProposed Method
CRT [18]CRTf [21]
Delay, ns { 3 , 5 , 14 } 8.1818.15710.085
{ 7 , 9 , 124 } 15.49313.35113.531
{ 5 , 29 , 93 , 313 } 21.22816.81417.600
LUTs { 3 , 5 , 14 } 6359105
{ 7 , 9 , 124 } 289358285
{ 5 , 29 , 93 , 313 } 9979201,049
A·D { 3 , 5 , 14 } 5154811,058
{ 7 , 9 , 124 } 4,4774,7793,856
{ 5 , 29 , 93 , 313 } 21,16415,46818,462
Power, W { 3 , 5 , 14 } 5.9465.50411.733
{ 7 , 9 , 124 } 22.22639.15426.789
{ 5 , 29 , 93 , 313 } 65.901106.867117.797
Table 4. Modeling results of magnitude comparison and reverse RNS to binary conversion for proposed and balanced moduli sets.
Table 4. Modeling results of magnitude comparison and reverse RNS to binary conversion for proposed and balanced moduli sets.
Moduli SetRef.Magnitude ComparisonReverse Conversion
Delay, nsLUTsA·DDelay, nsLUTsA·D
{ 2 n 1 , 2 n , 2 n + 1 } n = 3 [29,30]12.9532723,52313.4861692,279
{ 2 n 1 , 2 n + k , 2 n + 1 } n = 2 , k = 2 [31]11.5331501,72911.246911,023
{ 3 , 5 , 14 } , Proposed9.7491101,07210.0851051,058
{ 2 n 1 , 2 n , 2 n + 1 } n = 4 [29,30]14.9642754,11515.8552634,169
{ 2 n 1 , 2 n , 2 n + 1 , 2 n + 1 + 1 } n = 3 [34]16.7104277,13520.2174479,036
{ 7 , 9 , 124 } Proposed11.8302733,22913.5312853,856
{ 2 n 1 , 2 n + 1 , 2 n + 1 1 , 2 n + k } n = 4 , k = 4 [35]16.6693035,05024.16357213,821
{ 2 n 1 , 2 n + 1 , 2 n 1 1 , 2 n + k } n = 6 , k = 0 [35]24.9621,76744,10730.8311,49646,123
{ 5 , 29 , 93 , 313 } Proposed11.9915496,58317.6001,04918,462
Table 5. The possibility of RNS constructing with a given sum of quotients (SQ) form.
Table 5. The possibility of RNS constructing with a given sum of quotients (SQ) form.
Type and Number of RNS ModuliForm of SQ
S Q = 2 n 1 S Q = 2 n S Q = 2 n + 1
one even moduleexistnot existexist
all moduli are odd3 moduliexistnot existnot exist
4 modulinot existexistnot exist
5 modulinot existnot existexist

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Valueva, M.; Valuev, G.; Semyonova, N.; Lyakhov, P.; Chervyakov, N.; Kaplun, D.; Bogaevskiy, D. Construction of Residue Number System Using Hardware Efficient Diagonal Function. Electronics 2019, 8, 694. https://doi.org/10.3390/electronics8060694

AMA Style

Valueva M, Valuev G, Semyonova N, Lyakhov P, Chervyakov N, Kaplun D, Bogaevskiy D. Construction of Residue Number System Using Hardware Efficient Diagonal Function. Electronics. 2019; 8(6):694. https://doi.org/10.3390/electronics8060694

Chicago/Turabian Style

Valueva, Maria, Georgii Valuev, Nataliya Semyonova, Pavel Lyakhov, Nikolay Chervyakov, Dmitry Kaplun, and Danil Bogaevskiy. 2019. "Construction of Residue Number System Using Hardware Efficient Diagonal Function" Electronics 8, no. 6: 694. https://doi.org/10.3390/electronics8060694

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