Random Dopant Fluctuation-Induced Variability in n-Type Junctionless Dual-Metal Gate FinFETs
Abstract
:1. Introduction
2. Device Structure and Simulation
3. Results and Discussion
4. Conclusions
Author Contributions
Funding
Conflicts of Interest
References
- Pradhan, K.P.; Saha, S.K.; Sahu, P.K.; Priyanka. Impact of Fin Height and Fin Angle Variation on the Performance Matrix of Hybrid FinFETs. IEEE Trans. Electron Devices 2017, 64, 52–57. [Google Scholar] [CrossRef]
- Lü, W.F.; Dai, L. Impact of work-function variation on analog figures-of-merits for high-k/metal-gate junctionless FinFET and gate-all-around nanowire MOSFET. Microelectron. J. 2019, 84, 54–58. [Google Scholar] [CrossRef]
- Saha, R.; Bhowmick, B.; Baishya, S. Statistical Dependence of Gate Metal Work Function on Various Electrical Parameters for an n-Channel Si Step-FinFET. IEEE Trans. Electron Devices 2017, 64, 969–976. [Google Scholar] [CrossRef]
- Dadgour, H.F.; Endo, K.; De, V.K.; Banerjee, K. Grain-Orientation Induced Work Function Variation in Nanoscale Metal-Gate Transistors—Part I: Modeling, Analysis, and Experimental Validation. IEEE Trans. Electron Devices 2010, 57, 2504–2514. [Google Scholar] [CrossRef]
- Long, W.; Ou, H.; Kuo, J.M.; Chin, K.K. Dual material gate (DMG) field effect transistor. IEEE Trans. Electron Devices 1999, 46, 865–870. [Google Scholar]
- Hong, Y.; Guo, Y.; Yang, H.; Yao, J.F.; Zhang, J.; Ji, X.C. A novel Bulk-FinFET with dual-material gate. In Proceedings of the IEEE International Conference on Solid-state and Integrated Circuit Technology (ICSICT), Guilin, China, 28–31 October 2014. [Google Scholar]
- Saha, R.; Baishya, S.; Bhowmick, B. 3D analytical modeling of surface potential, threshold voltage, and subthreshold swing in dual-material-gate (DMG) SOI FinFETs. J. Comput. Electron. 2017, 17, 153–162. [Google Scholar] [CrossRef]
- Pravin, J.C.; Nirmal, D.; Prajoon, P.; Menokey, M. A New Drain Current Model for a Dual Metal Junctionless Transistor for Enhanced Digital Circuit Performance. IEEE Trans. Electron Devices 2016, 63, 3782–3789. [Google Scholar]
- Munteanu, D.; Autran, J.L.; Moindjie, S. Single-event-transient effects in Junctionless Double-Gate MOSFETs with Dual-Material Gate investigated by 3D simulation. Microelectron. Reliab. 2017, 76–77, 719–724. [Google Scholar] [CrossRef]
- Raksharam; Dutta, A.K. A Unified Analytical Drain Current Model for Double-Gate Junctionless Field-Effect Transistors Including Short Channel Effects. Solid State Electron. 2017, 130, 33–40. [Google Scholar]
- Lou, H.; Zhang, L.; Zhu, Y.; Lin, X.; Yang, S.; He, J.; Chan, M. A Junctionless Nanowire Transistor with a Dual-Material Gate. IEEE Trans. Electron Devices 2012, 59, 1829–1836. [Google Scholar]
- Nawaz, S.M.; Dutta, S.; Chattopadhyay, A.; Mallik, A. Comparison of Random Dopant and Gate-Metal Workfunction Variability Between Junctionless and Conventional FinFETs. IEEE Electron Device Lett. 2014, 35, 663–665. [Google Scholar]
- Colinge, J.; Lee, C.; Afzalian, A.; Akhavan, N.; Yan, R.; Ferain, I.; Razavi, P.; O’Neill, B.; Blake, A.; White, M.; et al. Nanowire transistors without junctions. Nat. Nanotechnol. 2010, 5, 225–229. [Google Scholar] [CrossRef] [PubMed]
- Shin, Y.H.; Weon, S.; Hong, D.; Yun, L. Analytical Model for Junctionless Double-Gate FET in Subthreshold Region. IEEE Trans. Electron Devices 2017, 64, 1433–1440. [Google Scholar] [CrossRef]
- Paz, B.C.; Casse, M.; Barraud, S.; Reimbold, G.; Faynot, O.; Avila-Herrera, F.; Cerdeira, A.; Pavanello, M.A. Drain current model for short-channel triple gate junctionless nanowire transistors. Microelectron. Reliab. 2016, 63, 1–10. [Google Scholar] [CrossRef]
- Kumar, A.; Tripathi, M.M.; Chaujar, R. Comprehensive analysis of sub-20nm Black Phosphorus based Junctionless-Recessed Channel MOSFET for Analog/RF applications. Superlattices Microstruct. 2018, 116, 171–180. [Google Scholar] [CrossRef]
- Ru, L.Y.; Che-Hsiang, C.; Yi-Ruei, J.; Erry, D.K.; Du, Y.T.; Lin, Y.H. Hybrid p-Channel/N-Substrate Poly-Si Nanosheet Junctionless Field-Effect Transistors with Trench and Gate-All-Around Structure. IEEE Trans. Nanotechnol. 2018, 17, 1014–1019. [Google Scholar]
- Lee, C.W.; Ferain, I.; Afzalian, A.; Yan, R.; Akhavan, N.D.; Razavi, P.; Colinge, J.P. Performances estimation of junctionless multigate transistors. Solid State Electron. 2009, 54, 97–103. [Google Scholar] [CrossRef]
- Leung, G.; Chui, C.O. Variability impact of random dopant fluctuation on nanoscale junctionless FinFETs. IEEE Electron Device Lett. 2012, 33, 767–769. [Google Scholar] [CrossRef]
- Kim, J.; Han, J.W.; Meyyappan, M. Reduction of Variability in Junctionless and Inversion-Mode FinFETs by Stringer Gate Structure. IEEE Trans. Electron Devices 2018, 65, 470–475. [Google Scholar] [CrossRef]
- Sano, N.; Matsuzawa, K.; Mukai, M.; Nakayamab, N. On discrete random dopant modeling in drift-diffusion simulations: Physical meaning of ‘atomistic’ dopants. Microelectron. Reliab. 2002, 42, 189–199. [Google Scholar] [CrossRef]
- Sentaurus Device User Guide; Synopsys, Inc.: Mountain View, CA, USA, 2017.
- Nayak, K.; Agarwal, S.; Bajaj, M.; Murali Kota, V.R.M.; Rao, V.R. Random Dopant Fluctuation Induced Variability in Undoped Channel Si Gate all Around Nanowire n-MOSFET. IEEE Trans. Electron Devices 2015, 62, 685–688. [Google Scholar] [CrossRef]
- Saha, S.K. Modeling Statistical Dopant Fluctuations Effect on Threshold Voltage of Scaled JFET Devices. IEEE Access 2016, 4, 507–513. [Google Scholar] [CrossRef]
- Saxena, M.; Haldar, S.; Gupta, M.; Gupta, R.S. Design considerations for novel device architecture: Hetero-material double-gate (HEM-DG) MOSFET with sub-100 nm gate length. Solid State Electron. 2004, 48, 1169–1174. [Google Scholar] [CrossRef]
- Lee, Y.; Shin, C. Impact of Equivalent Oxide Thickness on Threshold Voltage Variation Induced by Work-Function Variation in Multigate Devices. IEEE Trans. Electron Devices 2017, 64, 2452–2456. [Google Scholar] [CrossRef]
© 2019 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).
Share and Cite
Dai, L.; Lü, W.; Lin, M. Random Dopant Fluctuation-Induced Variability in n-Type Junctionless Dual-Metal Gate FinFETs. Electronics 2019, 8, 282. https://doi.org/10.3390/electronics8030282
Dai L, Lü W, Lin M. Random Dopant Fluctuation-Induced Variability in n-Type Junctionless Dual-Metal Gate FinFETs. Electronics. 2019; 8(3):282. https://doi.org/10.3390/electronics8030282
Chicago/Turabian StyleDai, Liang, Weifeng Lü, and Mi Lin. 2019. "Random Dopant Fluctuation-Induced Variability in n-Type Junctionless Dual-Metal Gate FinFETs" Electronics 8, no. 3: 282. https://doi.org/10.3390/electronics8030282
APA StyleDai, L., Lü, W., & Lin, M. (2019). Random Dopant Fluctuation-Induced Variability in n-Type Junctionless Dual-Metal Gate FinFETs. Electronics, 8(3), 282. https://doi.org/10.3390/electronics8030282