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Peer-Review Record

Aging-Resilient Topology Synthesis of Heterogeneous Manycore Network-On-Chip Using Genetic Algorithm with Flexible Number of Routers

Electronics 2019, 8(12), 1458; https://doi.org/10.3390/electronics8121458
Reviewer 1: Anonymous
Reviewer 2: Anonymous
Reviewer 3: Anonymous
Electronics 2019, 8(12), 1458; https://doi.org/10.3390/electronics8121458
Received: 5 November 2019 / Revised: 22 November 2019 / Accepted: 25 November 2019 / Published: 2 December 2019
(This article belongs to the Section Computer Science & Engineering)

Round 1

Reviewer 1 Report

This paper presented an aging aware topology synthesis of heterogenous manycore NoC using the GA algorithm to reduce the performance degradation of the links when they have been aged over time. This is an interesting idea. I have some questions as follows:

1. Do you have any stress tests to accelerate your testing and analysis?

2. Do you have any special reason why are the tests repeated after 1 day (in the lifetime analysis)?

Author Response

Dear Editor and Reviewers,

 

We greatly appreciate your efforts and valuable comments on our manuscript. All comments by the reviewer have been addressed, with corresponding changes made directly to the manuscript where appropriate.

 

Comment 1: Do you have any stress tests to accelerate your testing and analysis?

Response: We accelerated the test by increasing network traffic and allocating corresponding simulation time in applications with a large number of PEs.

Five of the eight application models simulated are widely used for NoC simulation. Because they have defined communication specifications, the original simulations must be done for accurate average latency and lifetime comparisons. In applications with less than 16 PEs (PIP, MWD, MPEG-4, VOPD), the simulation calculation amount per cycle was small, enabling fast simulation. However, the DVOPD with 32 PEs required significantly higher test times.

Three applications created by TGFF can set a particular communication specification. For the simulation time acceleration, MAX( ) and AVG( ) are given about 1.25 times higher than the existing models. Correspondingly, the flow of NoC operating time was assigned 1.25 times faster in the simulation. As a result, simulations on TGFF-36 and TGFF-50 completed faster than DVOPD with fewer PEs.

The response to Comment 2 can also be regarded as another work to accelerate the simulation.

 

Comment 2: Do you have any special reason why are the tests repeated after 1 day (in the lifetime analysis)?

Response: The following sentences in the paper are as follows.

“Because a 15-year simulation is an unrealistic computational time, we assume that the scenario is repeated after the NoC simulation for  cycles (≈ 1 day).”

This sentence seems to have been written inappropriately for our intention. We revise this as follows:

“Because a 15-year simulation is an unrealistic computational time, we proceeded with NoC simulation for  cycles ( 1 day) and assumed that the scenario was repeated for 15 years(=5475 days) of NoC operation.”

Repeated simulation scenarios should be long enough to reflect the nature of the application. However, scenarios that are too long result in increased simulation time and, therefore, require scenarios of moderate length. In this study, we simulated a one-day simulation scenario considering test time.

 

 

Sincerely,

 

Author Response File: Author Response.pdf

Reviewer 2 Report

In the manuscript, the authors propose a heterogeneous manycore network-on-chip topology synthesis that predicts the aging effect of each link and deploys routers and error correction code logic. The authors have provided a detailed explanation of their methodology and results. I would like to suggest few minor changes.

In page 6, "???−?? and ???−?? can be replaced by the threshold voltage values of the internal transistor". The authors need to clearly explain the relation between Vt and propagation delay and reword this statement for better clarity. In page 7, as time elapses, (9) left hand side becomes greater than T not negative. "If the left side of the relation becomes negative, an aging-induced delay fault occurs on the link." Authors need to reduce the content length in the manuscript. Some of the methodology details can be shortened or put in the appendix to improve readability.  

 

 

Author Response

Dear Editor and Reviewers,

 

We greatly appreciate your efforts and valuable comments on our manuscript. All comments by the reviewer have been addressed, with corresponding changes made directly to the manuscript where appropriate.

 

Comment 1: In page 6, "  and  can be replaced by the threshold voltage values of the internal transistor". The authors need to clearly explain the relation between  and propagation delay and reword this statement for better clarity.

Response: As the threshold voltage of the transistor increases,  and  also increase. This relationship is represented by Figure 3 and equation (13), including the effect of wire resistance on . We revised this statement to make it more transparent:

“As the threshold voltage of the transistor inside the flip-flop increases,  and  also increase.”

 

Comment 2: In page 7, as time elapses, (9) left hand side becomes greater than T not negative. "If the left side of the relation becomes negative, an aging-induced delay fault occurs on the link."

Response: Thank you for pointing out this error. We revised the sentence as follows:

“If the left side of the relation becomes greater than , an aging-induced delay fault occurs on the link.”

Comment 3: Authors need to reduce the content length in the manuscript. Some of the methodology details can be shortened or put in the appendix to improve readability.

Response: We determined that the contents of the 4.3 Non-uniform ECC Generation, 5.2 Initialization, 5.4 Crossover, and 5.5 mutations were long and detailed. Therefore, the contents of these sections have been modified and summarized. Detailed changes are described in the revised manuscript.

 

 

Sincerely,

Author Response File: Author Response.pdf

Reviewer 3 Report

The paper is devoted to actual topic as a design automation of integrated circuits (IC) based on network-on-chip (NoC) architecture. Reliability of the state-of-the-art ICs is one of the most important characteristics for a customer. Therefore up-to-date methodologies and techniques are used for design reliable ICs such as design-for-testability, design-for-manufacturability, etc. Aging is a reason of appearing defects in a topology of IC. Smart synthesis of aging-resilient topologies is important and actual topic.

The authors proposed a technique to synthesis of aging-resilient topologies for heterogeneous multicore NoC. The contribution concerns with application genetic algorithms to selection the reasonable minimum number of the routers with taking into account the aging-awareness and resilience. Both theoretical and experimental parts are described and explained.

The following recommendations for improvement the paper are proposed:
1) Authors use term “optimal” for the process of selection a number of routers, topology floorplanning, providing a minimal latency etc. In fact, the optimality should be mathematically proved. The term reasonable solution(s) is more relevant in the current case. Even more, GA as rule provides search of a local optimum.

2) It seems, there is the misprint at the sub-indexes for the routers description (r) in line 172.

3) Figure 6 requires correction in the corresponding data representation because actual coordinates for r1 and r2 are wrong. The third shift in cases r0-p1:(U1) and r2-p6:(\0) are not obvious.

4) The experimental results represented in Fig. 10 – Fig. 12 contain only absolute values. But for comparison purpose the relative values are important especially for the proper conclusions.

In general, the paper presented a complete research work with exhaustive experimental case studies. The paper can be published after minor corrections and taking into account comments described above.

Author Response

Dear Editor and Reviewers,

 

We greatly appreciate your efforts and valuable comments on our manuscript. All comments by the reviewer have been addressed, with corresponding changes made directly to the manuscript where appropriate.

 

Comment 1: Authors use term “optimal” for the process of selection a number of routers, topology floorplanning, providing a minimal latency etc. In fact, the optimality should be mathematically proved. The term reasonable solution(s) is more relevant in the current case. Even more, GA as rule provides search of a local optimum.

Response: Thank you for the recommendation for appropriate terms. We also think that the term "reasonable" is appropriate for the intention of the paper. In this paper, words related to the "optimal solution" have been revised.

 

Comment 2: It seems, there is the misprint at the sub-indexes for the routers description (r) in line 172.

Response: The sentence mentioned is:

“If there is a physical link between routers  and , and this link is included in the routing path of data transmission from PEs  to , then the value of  is 1.”

Thank you for pointing out this error. We corrected the sentence as follows:

“If there is a physical link between routers  and , and this link is included in the routing path of data transmission from PEs  to , then the value of  is 1.”

 

Comment 3: Figure 6 requires correction in the corresponding data representation because actual coordinates for r1 and r2 are wrong. The third shift in cases r0-p1:(U1) and r2-p6:(\0) are not obvious.

Response: Thank you for pointing out this error. We corrected the figure

 

Comment 4: The experimental results represented in Fig. 10 – Fig. 12 contain only absolute values. But for comparison purpose the relative values are important especially for the proper conclusions.

Response: The results represented in Fig. 10 – Fig. 12 has been changed to have a relative value. Horizontal lines have been added to make each content look accurate.

 

 

Sincerely,

Author Response File: Author Response.pdf

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