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Electronics 2019, 8(1), 13;

An 11 GHz Dual-Sided Self-Calibrating Dynamic Comparator in 28 nm CMOS

ESAT-MICAS—KU Leuven, Kasteelpark Arenberg 10, B-3001 Leuven, Belgium
Nokia, Bell Labs, Copernicuslaan 50, B-2018 Antwerp, Belgium
Author to whom correspondence should be addressed.
Received: 28 October 2018 / Revised: 18 December 2018 / Accepted: 18 December 2018 / Published: 21 December 2018
(This article belongs to the Special Issue Signal Processing and Analysis of Electrical Circuit)
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This paper demonstrates a high-speed, low-noise dynamic comparator, employing self-calibration. The proposed dual-sided, fully-dynamic offset calibration is able to reduce the input-referred offset voltage by a factor of ten compared to the uncalibrated value without any speed or noise penalty and with less than 5% power overhead. Moreover, the implemented multi-stage topology significantly advances the state-of-the-art comparator performance, achieving the highest reported operating frequency, as well as the lowest delay slope and sensitivity to supply and common mode variations compared to existing works, with similar energy/comparison. This makes the proposed self-calibrating comparator an ideal candidate for high resolution (>10 b) multi-GHz Analog-to-Digital Converters (ADCs). The 28 nm bulk CMOS prototype measures an input-referred noise and calibrated offset of 0.82 mV and 0.99 mV, respectively clocked at 11 GHz, consuming only 0.89 mW from a 1 V supply, for an area of 0.00054 mm2, including calibration. View Full-Text
Keywords: CMOS; dynamic comparator; offset calibration; high speed; low noise; low power; ADC CMOS; dynamic comparator; offset calibration; high speed; low noise; low power; ADC

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This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).

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Ramkaj, A.; Strackx, M.; Steyaert, M.; Tavernier, F. An 11 GHz Dual-Sided Self-Calibrating Dynamic Comparator in 28 nm CMOS. Electronics 2019, 8, 13.

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