# Soft-Decision Low-Complexity Chase Decoders for the RS(255,239) Code

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## Abstract

**:**

## 1. Introduction

## 2. RS Decoders

## 3. Low-Complexity Chase Decoder

## 4. Decoder Architecture

#### 4.1. Multiplicity Assignment Block

Algorithm 1 Pseudocode for the Sorting Array block | |

Input: For every symbol location $i\in [0,N-1]$ in the frame and its bit $k\in [0,m-1]$, the Min. Finder block provides ${\gamma}_{i}=min\left\{\right|{r}_{i,k}\left|\right\}$ and ${\delta}_{i}\phantom{\rule{3.33333pt}{0ex}}=\phantom{\rule{3.33333pt}{0ex}}\underset{k\in [0,m-1]}{arg}min\left\{\right|{r}_{i,k}\left|\right\}$ (where ${r}_{i,k}$ are the bit-level received voltages) | |

begin | |

Step 1 Sort symbols of the frame according to ${\gamma}_{i}$. | |

Step 2 $\mathbf{s}[1:\eta ]$ = symbol locations of the $\eta $ symbols with lowest ${\gamma}_{i}$ | |

Step 3 | |

for$h=1:\eta $ | // for all symbols selected in Step 2 |

$\mathbf{root}\left[h\right]={\alpha}^{-\mathit{s}\left[h\right]}$ | // root associated with its position in the frame |

$\mathbf{pos}\left[h\right]={\delta}_{\mathbf{s}\left[h\right]}$ | // location of the least reliable bit in the symbol |

end | |

end | |

Output: root,pos |

#### 4.2. Syndrome Update Block

Algorithm 2 Pseudocode for the Syndrome Update block | |

Input: root and pos from the Sorting Array block, and hard-decision syndromes ${\mathbf{S}}^{HD}$ from the | |

Syndrome Computer | |

begin | |

for all the test vectors (tv) assigned to this block | |

h=index in root of the symbol that is different from previous tv | |

$\mathrm{factor}=\mathbf{root}\left[h\right]$ | // $\mathbf{root}\left[h\right]={\alpha}^{-j}$ |

$\mathrm{pos}=\mathbf{pos}\left[h\right]$ | |

for $i=1:2t$ | // for all the syndromes |

if tv = first test vector (one with 1 symbol change from HD) | |

${\mathbf{S}}^{prev}\left[i\right]={\mathbf{S}}^{HD}\left[i\right]$ | |

end | |

${\mathbf{S}}^{new}\left[i\right]={\mathbf{S}}^{prev}\left[i\right]+{2}^{\mathrm{pos}}\xb7\mathrm{factor}$ | // $\mathrm{factor}={\alpha}^{-j\xb7i}$ |

${\mathbf{S}}^{prev}\left[i\right]={\mathbf{S}}^{new}\left[i\right]$ | |

$\mathrm{factor}=\mathrm{factor}\xb7\mathbf{root}\left[h\right]$ | |

end | |

Output: ${\mathbf{S}}^{new}$ | // $2t$ syndromes for the current test vector |

end | |

end |

#### 4.3. Vector Selection Block

#### 4.4. Symbol Modification Block

Algorithm 3 Pseudocode for the Symbol Modification block | |

Input: root and pos from the Sorting Array block, and | |

ntv = number of the selected test vector (tv) from Vector Selection block | |

begin | |

for$h=1:\eta $ | |

$\mathbf{root}\left[h\right]=0$ if the symbol associated with that root is not changed | |

end | |

for $i=1:N$ | // for all the symbols in the frame |

$\mathbf{d}\left[i\right]=0$ | |

for $h=1:\eta $ | // compare with the $\eta $ roots |

if $\left(\mathrm{ntv}<>0\right)$&$({\alpha}^{-i}=\phantom{\rule{0.166667em}{0ex}}\mathbf{root}\left[h\right])$ | // no changes if HD is selected |

$\mathbf{d}\left[i\right]={2}^{\mathbf{pos}\left[h\right]}$ | |

end | |

end | |

end | |

end | |

Output:$\mathbf{d}$ | // differences between ${y}_{i}^{HD}$ and ${y}_{i}^{2HD}$ for the selected tv |

## 5. Implementation Results

## 6. Conclusions

## Author Contributions

## Funding

## Conflicts of Interest

## References

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**Figure 4.**Test vectors used by the Q5 and Q6 decoders. The arrows show the processing order followed by each KES. ■ = 1, □ = 0.

**Figure 5.**Schematics of the Sorting Array block. Note that the first column is different than the rest, since “Din” and “shift in” inputs do not exist.

**Figure 7.**Chip layout of the proposed $\eta \phantom{\rule{3.33333pt}{0ex}}=\phantom{\rule{3.33333pt}{0ex}}4$ LCC decoder.

Block | Q6 | Q5 | $\mathit{\eta}\phantom{\rule{3.33333pt}{0ex}}=\phantom{\rule{3.33333pt}{0ex}}4$ |
---|---|---|---|

Root Generator | 55 | 54 | 55 |

Minimum Finder | 597 | 596 | 596 |

Sorting Array | 619 | 506 | 407 |

Syndrome Update | 3373 | 1681 | 830 |

Vector Selection | 3911 | 2387 | 1626 |

Symbol Modification | 304 | 269 | 219 |

Syndrome Computer | 1538 | 1538 | 1538 |

KES | 15,717 | 7906 | 3937 |

Polynomial Evaluation | 9054 | 4493 | 2242 |

CSEE | 1664 | 1665 | 1665 |

Others | 2480 | 1852 | 1528 |

Decoder (without BUFFER) | 39,312 | 22,947 | 14,643 |

BUFFER | 12,289 | 12,281 | 12,282 |

Total gate count (#XOR) | 51,601 | 35,228 | 26,925 |

RS(255,239) | Ours Q6 | Ours Q5 | Ours $\mathit{\eta}\phantom{\rule{3.33333pt}{0ex}}=\phantom{\rule{3.33333pt}{0ex}}4$ LCC | $\mathit{\eta}\phantom{\rule{3.33333pt}{0ex}}=\phantom{\rule{3.33333pt}{0ex}}5$ DCD [21] | $\mathit{\eta}\phantom{\rule{3.33333pt}{0ex}}=\phantom{\rule{3.33333pt}{0ex}}3$ LCC [20] |
---|---|---|---|---|---|

Process (nm) @ Supply Volt. (V) | [email protected] | [email protected] | [email protected] | [email protected] | 130@- |

Chip area (mm${}^{2}$)/# Metal layers | 0.632/8 | 0.435/8 | 0.336/8 | 0.216/9 | 0.332/- |

Gate ct. (kXOR) no/with buffer | 39.3/51.6 | 22.9/35.2 | 14.6/26.9 | 22.5/45.3 | -/- |

Frequency (MHz) | 446 * | 450 * | 450 * | 320 ${}^{\u2020}$ | 220 |

Throughput (Gb/s) | 3.55 | 3.58 | 3.58 | 2.56 | 1.6 |

Latency (clock cycles) | 256 × 2 + 34 | 256 × 2 + 34 | 256 × 2 + 34 | 259 × 3 | 275 × 2 ${}^{\S}$ |

Power consumpt. (mW@MHz) | 62.2@446 ${}^{\u2021}$ | 32.1@450 ${}^{\u2021}$ | 28.8@450 ${}^{\u2021}$ | 19.6@320 ${}^{\u2020}$ | - |

Coding gain (dBs@FER) | 0.60@${10}^{-6}$ | 0.52@${10}^{-6}$ | 0.45@${10}^{-6}$ | 0.38@${10}^{-6}$ | 0.37@${10}^{-6}$ |

Critical path | T${}_{*}$ + T${}_{+}$ + T${}_{\mathrm{x}}$ | T${}_{*}$ + T${}_{+}$ + T${}_{\mathrm{x}}$ | T${}_{*}$ + T${}_{+}$ + T${}_{\mathrm{x}}$ | 2T${}_{*}$ + 2T${}_{+}$ + T${}_{\mathrm{x}}$ | T${}_{*}$ + T${}_{+}$ + T${}_{\mathrm{x}}$ |

RS(255,239) | Ours Q6 | Ours Q5 | Ours $\mathit{\eta}=4$ LCC | $\mathit{\eta}\phantom{\rule{3.33333pt}{0ex}}=\phantom{\rule{3.33333pt}{0ex}}3$ LCC [20] | $\mathit{\eta}\phantom{\rule{3.33333pt}{0ex}}=\phantom{\rule{3.33333pt}{0ex}}3$ LCC [19] |
---|---|---|---|---|---|

LUTs | 16,049 | 8914 | 5246 | 7377 | 5470 * |

Registers | 6362 | 3966 | 2729 | 3380 | 2230 * |

Frequency (MHz) | 166.7 | 166.7 | 166.7 | 134 | 149.5 |

Throughput (Gb/s) | 1.3 | 1.3 | 1.3 | 1.0 | 1.1 |

Latency (clock cycles) | 256 × 2 + 34 | 256 × 2 + 34 | 256 × 2 + 34 | 275 × 2 ${}^{\S}$ | 275 × 2 ${}^{\S}$ |

Coding gain (dBs@FER) | 0.60@${10}^{-6}$ | 0.52@${10}^{-6}$ | 0.45@${10}^{-6}$ | 0.37@${10}^{-6}$ | 0.37@${10}^{-6}$ |

Critical path | T${}_{*}$+ T${}_{+}$+ T${}_{\mathrm{x}}$ | T${}_{*}$+ T${}_{+}$+ T${}_{\mathrm{x}}$ | T${}_{*}$+ T${}_{+}$+ T${}_{\mathrm{x}}$ | T${}_{*}$+ T${}_{+}$+ T${}_{\mathrm{x}}$ | T${}_{*}$+ T${}_{+}$+ T${}_{\mathrm{x}}$ |

RS(255,239) | Ours Q6 | Ours Q5 | Ours $\mathit{\eta}\phantom{\rule{3.33333pt}{0ex}}=\phantom{\rule{3.33333pt}{0ex}}4$ LCC |
---|---|---|---|

LUTs | 13,343 | 7372 | 4227 |

Registers | 7223 | 4480 | 3083 |

Frequency (MHz) | 312.5 | 312.5 | 312.5 |

Throughput (Gb/s) | 2.5 | 2.5 | 2.5 |

© 2018 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).

## Share and Cite

**MDPI and ACS Style**

Torres, V.; Valls, J.; Canet, M.J.; García-Herrero, F.
Soft-Decision Low-Complexity Chase Decoders for the RS(255,239) Code. *Electronics* **2019**, *8*, 10.
https://doi.org/10.3390/electronics8010010

**AMA Style**

Torres V, Valls J, Canet MJ, García-Herrero F.
Soft-Decision Low-Complexity Chase Decoders for the RS(255,239) Code. *Electronics*. 2019; 8(1):10.
https://doi.org/10.3390/electronics8010010

**Chicago/Turabian Style**

Torres, Vicente, Javier Valls, Maria Jose Canet, and Francisco García-Herrero.
2019. "Soft-Decision Low-Complexity Chase Decoders for the RS(255,239) Code" *Electronics* 8, no. 1: 10.
https://doi.org/10.3390/electronics8010010