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Electronics 2018, 7(8), 139;

Area Efficient Dual-Fed CMOS Distributed Power Amplifier

Instituto Universitario de Microelectrónica Aplicada (IUMA), Universidad de Las Palmas de Gran Canaria (ULPGC), 35001 Las Palmas, Spain
Author to whom correspondence should be addressed.
Received: 19 July 2018 / Revised: 30 July 2018 / Accepted: 3 August 2018 / Published: 6 August 2018
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In this paper, an area-efficient 4-stage dual-fed distributed power amplifier (DPA) implemented in a 0.35 μm Complementary Metal Oxide Semiconductor (CMOS) process is presented. To effectively reduce the area of the circuit, techniques such as using multilevel inductors and closely-placing conventional spiral inductors are employed. Additionally, a novel technique based on stacking inductors one on top of others is implemented. Based on these techniques, a 32% area reduction is achieved compared to a conventional design without a noticeable performance degradation. This reduction could be further exploited as the number of stages of the dual-fed DPA increases. View Full-Text
Keywords: distributed power amplifier; dual-fed; stacked inductor; multilevel inductor; area reduction distributed power amplifier; dual-fed; stacked inductor; multilevel inductor; area reduction

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This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).

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Pino, J.D.; Khemchandani, S.L.; Mateos-Angulo, S.; Mayor-Duarte, D.; San-Miguel-Montesdeoca, M. Area Efficient Dual-Fed CMOS Distributed Power Amplifier. Electronics 2018, 7, 139.

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