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Electronics 2018, 7(8), 137; https://doi.org/10.3390/electronics7080137

A Pipelined FFT Processor Using an Optimal Hybrid Rotation Scheme for Complex Multiplication: Design, FPGA Implementation and Analysis

1
School of Computer Engineering and Information Technology, University of Ulsan, Ulsan 680-749, Korea
2
School of Electronics and Computer Engineering, Chonnam National University, Gwangju 501-757, Korea
*
Author to whom correspondence should be addressed.
Received: 7 July 2018 / Revised: 29 July 2018 / Accepted: 1 August 2018 / Published: 2 August 2018
(This article belongs to the Special Issue Hardware and Architecture)
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Abstract

The fast Fourier transform (FFT) is the most prevalent algorithm for the spectral analysis of acoustic emission signals acquired at ultra-high sampling rates to monitor the condition of rotary machines. The complexity and cost of the associated hardware limit the use of FFT in real-time applications. In this paper, an efficient hardware architecture for FFT implementation is proposed based on the radix-2 decimation in frequency algorithm (R2DIF) and a feedback pipelined technique (FB) that allows effective sharing of storage between the input and output data at each stage of the FFT process via shift registers. The proposed design uses an optimal hybrid rotation scheme by combining the modified coordinate rotation digital computer (m-CORDIC) algorithm and a binary encoding technique based on canonical signed digit (CSD) for replacing the complex multipliers in FFT. The m-CORDIC algorithm, with an adaptive iterative monitoring process, improves the convergence of computation, whereas the CSD algorithm optimizes the multiplication of constants using a simple shift-add method. Therefore, the proposed design does not require the large memory typically entailed by existing designs to carry out twiddle factor multiplication in large-point FFT implementations, thereby reducing its area on the chip. Moreover, the proposed pipelined FFT processor uses only distributed logic resources and does not require expensive dedicated functional blocks. Experimental results show that the proposed design outperforms existing state-of-the-art approaches in speed by about 49% and in resource utilization by around 51%, while delivering the same accuracy and utilizing less chip area. View Full-Text
Keywords: radix-2 decimation in frequency; fast Fourier transform; feedback; pipelined; modified coordinate rotation digital computer; field programmable gate arrays radix-2 decimation in frequency; fast Fourier transform; feedback; pipelined; modified coordinate rotation digital computer; field programmable gate arrays
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This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).
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Nguyen, H.N.; Khan, S.A.; Kim, C.-H.; Kim, J.-M. A Pipelined FFT Processor Using an Optimal Hybrid Rotation Scheme for Complex Multiplication: Design, FPGA Implementation and Analysis. Electronics 2018, 7, 137.

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