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All-in-One Wafer-Level Solution for MMIC Automatic Testing

School of Aeronautics and Astronautics, Zhejiang University, Hangzhou 310027, China
Author to whom correspondence should be addressed.
Electronics 2018, 7(5), 57;
Received: 7 April 2018 / Revised: 20 April 2018 / Accepted: 23 April 2018 / Published: 26 April 2018
PDF [10314 KB, uploaded 3 May 2018]


In this paper, we present an all-in-one wafer-level solution for MMIC (monolithic microwave integrated circuit) automatic testing. The OSL (open short load) two tier de-embedding, the calibration verification model, the accurate PAE (power added efficiency) testing, and the optimized vector cold source NF (noise figure) measurement techniques are integrated in this solution to improve the measurement accuracy. A dual-core topology formed by an IPC (industrial personal computer) and a VNA (vector network analyzer), and an automatic test software based on a three-level driver architecture, are applied to enhance the test efficiency. The benefit from this solution is that all the data of a MMIC can be achieved in only one contact, which shows state-of-the-art accuracy and efficiency. View Full-Text
Keywords: wafer-level; MMICs automatic test; OSL de-embedding; calibration verification model; dual-core topology wafer-level; MMICs automatic test; OSL de-embedding; calibration verification model; dual-core topology

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Ding, X.; Wang, Z.; Liu, J.; Zhou, M.; Chen, W.; Chen, H.; Mo, J.; Yu, F. All-in-One Wafer-Level Solution for MMIC Automatic Testing. Electronics 2018, 7, 57.

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