Emerging Applications of FPGAs and Reconfigurable Computing Systems

1. Introduction

Field-programmable gate arrays and reconfigurable computing have moved beyond their earlier role as convenient prototyping platforms. In modern computing systems, they are increasingly occupying a strategic position between the flexibility of software and the efficiency of fixed-function hardware [1,2]. This role has become especially important as many application areas are demanding combinations that are difficult to achieve with conventional architectures alone, including acceleration, deterministic low latency, high-throughput streaming, low energy consumption, and the ability of rapid adaptation to changing algorithms and standards [3,4]. Thus, FPGA and reconfigurable computing have become central not only to embedded and industrial systems, but also to edge AI, wireless communications, cryptographic processing, scientific instrumentation, and other data-intensive environments [3,4,5,6].

The evolution of these devices reflects that growing importance, incorporating richer memory hierarchies, abundant DSP resources, hardened interfaces, embedded processors, and, in some cases, direct-RF capabilities. It enables these devices to function as heterogeneous computing systems rather than as standalone logic fabrics [2,7].

At the same time, the field faces a number of persistent challenges. These include the trade-off between development productivity and hardware efficiency, the difficulty of mapping irregular or control-dominant workloads, the cost of data movement and synchronization, the need to balance area, throughput, latency, and power, and the increasing importance of resilience, security, and maintainability in critical deployments [8,9,10,11]. Emerging research trends address these issues through high-level synthesis and software–hardware co-design, custom arithmetic and approximation methods, more scalable multi-FPGA organizations, and design methodologies that better connect algorithmic intent with hardware implementations [2,10,12,13].

Against this background, the Special Issue “Emerging Applications of FPGAs and Reconfigurable Computing System” offers a timely cross-section of current directions in the field. The nine papers collected here reflect both the breadth of application domains and the diversity of abstraction levels at which innovation is taking place. Taken together, they show that progress in reconfigurable computing depends not only on faster devices, but also on advances in design flows, arithmetic structures, control architectures, resilient data processing, and hardware-aware machine learning. The contributions range from methodological and architectural studies to concrete deployments in power electronics, high-energy physics, spaceborne systems, wireless testbeds, and edge inference. Overall they illustrate the continuing expansion of reconfigurable solutions into technically demanding and scientifically relevant contexts.

2. Summary of the Contributions

The review by Kaur et al. broadens the perspective of the Special Issue by examining scheduling techniques for efficient deep learning computations on GPUs. Although its immediate focus is not FPGA implementation, the paper addresses a problem that is highly relevant across heterogeneous accelerator platforms: how to translate massive parallelism into effective throughput under constraints imposed by memory behavior, execution imbalance, and resource contention. By organizing the literature around strategies such as dynamic load balancing, workload partitioning, memory-access scheduling, prefetching, hybrid scheduling, or pipelined execution, the review provides a useful map of the accelerator-scheduling landscape. Its contribution to this Special Issue lies in situating reconfigurable computing within a larger systems context and in highlighting future directions—energy-aware operation, adaptive scheduling, interoperability, and fault tolerance—that are equally pertinent to FPGA-based platforms.

A closely related concern, addressed from the standpoint of hardware compilation, appears in the work of She et al., who tackle the long-standing limitations of static scheduling in High-Level Synthesis (HLS). Conventional HLS tools remain highly effective for regular, compute-dominant designs, but they are often very conservative when loops contain runtime-dependent control flow. In this work, the authors respond to this problem with a source-to-source compiler that converts untimed code into a Pseudo-Cycle-Accurate (PCA) model, exposing useful dynamism while remaining compatible with existing static HLS backends. This is a significant contribution because it seeks to preserve the mature optimizations of commercial tools—such as resource sharing and datapath optimization—without incurring in frequency and area penalties commonly associated with dynamic or tool-specific hybrid flows. The reported improvements in wall-clock time and in the overall area–frequency–latency balance make this work particularly relevant for broadening the practical reach of HLS in reconfigurable computing.

Where She et al. focus on compilation, Salauyou and Klimowicz draw attention to a lower, but no less important, layer of the design process: the HDL description of finite state machines. FSMs remain fundamental building blocks of digital systems, and their quality directly affects the efficiency of larger architectures. The paper shows that a careful use of default assignments in Verilog/SystemVerilog can substantially improve the synthesized implementation of FSM circuits. Rather than replacing established techniques such as state minimization or encoding, the proposed styles complement them by optimizing the coding stage itself. This practical emphasis is one of the paper’s strengths. Across benchmark studies, the most effective style yields strong reductions in area and clear performance gains, while also delivering measurable savings in another synthesis environment. The broader significance of the contribution is that it reminds designers that implementation quality is shaped not only by algorithms and architectures, but also by the descriptive discipline with which hardware intent is expressed.

At the arithmetic level, Magyari and Chen revisit modular reduction, a core operation in modern cryptographic and residue-based computation. Because modular reduction is both frequent and expensive, its hardware realization has direct implications for performance, power, and resource allocation in FPGA systems. The proposed Hardware-Optimized Modular Reduction (HOM-R) method replaces multiplier- and divider-dependent approaches with a structure based on calculated reduction cycles, addition, and configurable look-up tables. This matters because many emerging security-oriented workloads, including post-quantum cryptography and related modular-arithmetic applications, require implementations that are not only fast but also resource-conscious. The results show that HOM-R reduces power and logic costs relative to a conventional implementation while offering stronger timing margins. Particularly notable is its ability to condense a 256-bit input to a 4-bit base in a single 250 MHz cycle, illustrating how carefully specialized arithmetic can simultaneously reduce latency and free DSP resources for the rest of the design.

A different but equally important form of specialization is presented by Bonanno, who addresses the delay limitations of digital pulse-width modulation in power-electronics control. In such systems, phase delay can degrade closed-loop performance and restrict achievable bandwidth, making the problem both practical and technically significant. The proposed enhanced Digital PWM (eDPWM) architecture introduces zero phase delay, or a programmable derivative action, while retaining a structure suitable for commercial FPGA implementation. Its relevance lies in the way it combines control-theoretic benefit with implementation simplification: the architecture removes several sources of complexity present in earlier approaches, avoids burdensome fractional-slope counter structures, and inherently generates a synchronization signal useful for ADC triggering in power-electronics applications. This paper therefore exemplifies a recurring strength of reconfigurable computing: the capacity to embed refined control functionality in hardware structures that remain implementable, configurable, and efficient in real systems.

The contribution by Perticaroli et al. demonstrates the role of FPGAs in one of the most demanding real-time scientific environments: online event selection in high-energy physics. Their FPGA-RICH system is designed for the NA62 experiment and aims to bring part of the particle-identification capability of the Ring Imaging Cherenkov detector into the experiment’s low-level trigger chain. The challenge is severe, since meaningful classification must be performed under a throughput requirement of roughly 10 MHz and a latency on the order of 1 μs. The authors address this by combining a streaming preprocessing pipeline with a compact neural-network classifier developed through an HLS and hls4ml workflow. The result is an implementation that reaches sub-microsecond pipeline latency and throughput compatible with the trigger environment, while producing richer trigger primitives than the baseline scheme. Beyond the immediate application, the paper shows how machine learning can be integrated into tightly constrained firmware pipelines and points toward more elaborate detector-level inference in future trigger systems.

Reliability under harsh operating conditions is the central theme of the paper by Li, Zhou, and Zhu, who focus on the implementation of an RS(255,223) encoder for spaceborne storage systems. Here, the challenge is twofold: the encoder must meet increasing throughput demands imposed by modern storage interfaces, while also improving tolerance to radiation-induced faults. The authors respond with an interleaved pipelined architecture that embeds interleaving directly into the pipeline rather than treating it as a separate stage. This structural decision enables a 36-stage implementation that raises performance substantially while also dispersing upset patterns across sequences, thereby enhancing radiation resilience. Implemented on a Xilinx platform, the encoder reaches a throughput of 3.043 Gbps with an 8-bit symbol size. Equally important is the study’s attention to the fault recovery behavior and its discussion of future physical radiation testing, which place the work squarely at the intersection of high-performance design and dependable reconfigurable computing for space applications.

The paper by Gayanath et al. advances the discussion from single-device acceleration to scalable heterogeneous systems for RF and AI workloads. Their work addresses a problem of growing importance in next-generation wireless experimentation: how to combine direct-RF acquisition, large-scale digital signal processing, and higher-level AI functions within a unified and expandable framework. The proposed solution interconnects RF-SoC and downstream FPGA platforms through high-speed Aurora-based SerDes links, enabling sustained data rates of up to 50 Gbps per ADC–DAC channel and supporting real-time matrix–vector computation at the tera-MAC scale. The system is demonstrated in wireless-testbed configurations that perform beamforming and polyphase filterbanking over 1.0 GHz bandwidth, while also providing a path toward integration with external AI compute resources. This contribution is especially relevant because it illustrates how reconfigurable computing is evolving from isolated acceleration blocks into distributed, application-specific infrastructures for communications, sensing, and AI-native RF systems.

Finally, the article by Sadheerthan et al. turns to one of the most active frontiers in embedded intelligence: efficient on-device inference for large language models. In low-power neural processing units (NPU), softmax remains a costly component because transcendental operations are expensive and direct exponential support is often absent. The authors address this bottleneck with an attention distribution-aware approximation strategy that uses particle swarm optimization to derive non-uniform segmentation and variable polynomial degrees, while snapping the resulting boundaries to a 128-bin look-up structure for constant-time, branch-free access. The importance of the work lies in its careful balance between numerical fidelity and implementation efficiency. On TinyLlama, the method reduces the cycle cost of the exponential kernel relative to uniform baselines while preserving ranking fidelity and keeping end-to-end language-model quality nearly unchanged. This paper is a strong example of hardware-aware approximation design for edge AI and reflects the growing convergence of reconfigurable and accelerator-oriented thinking in practical inference systems.

3. Conclusions

The papers gathered in this Special Issue highlight several key directions in current FPGA and reconfigurable computing research. One is the continuing improvement of design productivity through better abstractions, coding practices, and compilation flows, as seen in the works on HLS scheduling and FSM description. A second is the refinement of domain-specific hardware structures (arithmetical, control-oriented, or approximate) that allow designers to achieve meaningful gains in latency, power, and area without sacrificing implementability. A third is the expansion of FPGA-based solutions into environments where real-time behavior, reliability, and system-level integration are crititcal, including particle-physics instrumentation, spaceborne data protection, high-bandwidth wireless testbeds, and edge AI inference. The review contribution further reinforces this picture by showing that performance is increasingly determined not by raw hardware capacity alone, but also by the quality of the scheduling and orchestration strategies that govern heterogeneous systems.

Overall, this Special Issue shows that the emerging applications of FPGAs are shaped by a capacity for co-optimization across multiple levels: algorithms, arithmetic, architecture, design flow, and deployment context. This capacity will remain central as future systems demand not only higher performance, but also stronger resilience, greater adaptability, and shorter development cycles. The contributions presented here provide a valuable snapshot of this evolution and, at the same time, point towards a future in which reconfigurable computing will continue to expand its role in both advanced research infrastructures and high-impact practical systems.