Multi-Stage Power Conversion and Coordinated Voltage Control for Battery-Based Power Barges Supplying LV and HV AC Loads

Abstract

The growing electrification of ports and maritime transport requires flexible power systems capable of supplying multiple voltage levels with high efficiency and power quality. Battery-based power barges offer a promising solution, but their power conversion systems must handle wide voltage and power ranges while remaining stable under dynamic operating conditions. This paper presents a scalable multi-stage power conversion architecture for battery-based power barges that can supply both low-voltage and high-voltage AC loads from a common DC source. The system combines isolated Dual Active Bridge (DAB) DC–DC converters with a three-level Neutral-Point-Clamped (NPC) inverter. An input-parallel output-series DAB configuration is used for high-voltage operation, enabling modularity and scalability within semiconductor limits. A coordinated control strategy ensures stable DC-link regulation, balanced module operation, and high-quality AC voltage generation. Simulation results confirm stable operation, fast dynamic response, a voltage THD below 4%, and overall efficiency above 95%, demonstrating the suitability of the proposed architecture for future power barge and port electrification applications.

1. Introduction

The rapid electrification of maritime transport and port infrastructures is a key enabler for reducing greenhouse gas emissions, air pollution, and noise in coastal areas. Shore-side electricity supply systems, battery-supported power barges, and floating energy hubs are increasingly considered viable solutions to provide clean and flexible power to berthed ships, offshore installations, and port facilities. These systems must be capable of supplying a wide range of electrical loads, spanning from low-voltage (LV) auxiliary services to medium- and high-voltage (HV) propulsion and hoteling demands, while maintaining high efficiency, power quality, and operational reliability [1,2,3].

In this context, battery-based power barges have emerged as a promising approach to decouple ship power demand from local grid constraints. By integrating large-scale energy storage with power electronic conversion systems, power barges can operate as mobile or semi-permanent assets that support port electrification, peak shaving, and grid-support services. However, the electrical architecture of such systems poses significant technical challenges. In particular, the power conversion system must handle wide voltage and power ranges, provide galvanic isolation, comply with stringent harmonic and power-quality standards, and ensure stable operation under highly dynamic loading conditions.

Conventional shore power solutions often rely on single-stage or lightly modularized conversion structures, typically optimized for a specific voltage level or load profile. While these approaches are suitable for dedicated applications, they lack the flexibility required for future ports, where multiple ship types, voltage standards, and power ratings must be supported by a common infrastructure. Furthermore, direct medium-voltage conversion from battery systems remains challenging due to semiconductor voltage limits, insulation requirements, and control complexity. These limitations motivate the investigation of multi-stage and modular power conversion architectures that can scale efficiently in both voltage and power.

Among the isolated DC–DC conversion topologies, the Dual Active Bridge (DAB) converter has gained significant attention for high-power applications due to its bidirectional power flow capability, inherent galvanic isolation, and compatibility with soft-switching operation [4]. When combined with appropriate modulation and control strategies, DAB converters can achieve high efficiency across a wide operating range. Moreover, modular DAB configurations, such as input-parallel output-series (IPOS) arrangements, offer an effective means to overcome semiconductor voltage and current constraints in high-voltage, high-power systems. On the AC side, multilevel inverter topologies, particularly the Neutral-Point-Clamped (NPC) inverter, are well-suited for medium-voltage applications, as they reduce device voltage stress, improve harmonic performance, and enable efficient operation at high power levels.

Despite these advantages, the integration of multiple DAB stages with multilevel inverters in a unified battery-based power barge architecture has not been sufficiently addressed in the literature. Existing studies often focus on isolated aspects, such as DAB modeling and control, modular DC–DC converters, or multilevel inverter performance, without providing a system-level perspective that accounts for both low-voltage and high-voltage supply paths, coordinated control, and dynamic interaction between DC and AC subsystems. In particular, the coexistence of LV and HV operating modes supplied from a common battery source introduces additional challenges related to voltage regulation, constant power load behavior, current and voltage sharing in modular converters, and neutral-point balancing in multilevel inverters.

This paper addresses these challenges by proposing and analyzing a multi-stage battery-based power conversion architecture tailored for power barge applications. The system employs two isolated DAB converters interfaced with a common battery source: one dedicated to supplying low-voltage loads and the other designed for high-voltage operation using a modular IPOS configuration. Both DAB stages feed a three-level NPC inverter that generates high-quality three-phase AC voltages across a wide range of voltage levels. A coordinated control strategy is adopted, combining phase-shift control for the DAB converters with voltage-oriented control for the NPC inverter, ensuring stable operation, effective power flow regulation, and compliance with power-quality requirements.

The main contributions of this work can be summarized as follows:

• System-level architecture: A flexible multi-stage power conversion topology capable of supplying both LV (400–690 V, 100 kVA) and HV (6.6–11 kV, 3 MVA) AC loads from a common battery-based DC source is proposed and analyzed.
• Modular high-voltage DC–DC conversion: An IPOS-connected DAB architecture is developed for high-voltage operation, enabling scalable voltage and power ratings while respecting semiconductor limits.
• Coordinated control strategy: Dedicated control loops are designed for DC-link voltage regulation, current sharing, voltage sharing, and AC-side voltage control, ensuring stable interaction between the DC and AC subsystems under steady-state and dynamic conditions.
• Comprehensive simulation-based validation: Detailed MATLAB/Simulink (version 2025) and PLECS simulations (PLECS Standalone Version 4.9.4 (2025)) are carried out to evaluate steady-state performance, dynamic response to load and input voltage disturbances, harmonic distortion, semiconductor stress, and conversion efficiency.

The remainder of the paper is organized as follows. Section 2 presents the overall system architecture and operating modes. Section 3 and Section 4 describe the modeling, design, and control of the DAB converters and the NPC inverter, respectively. Section 5 and Section 6 evaluate the dynamic performance of the system under low-voltage and high-voltage operating conditions. Finally, Section 6 concludes the paper and outlines directions for future research.

2. System Architecture

The proposed power conversion system has been developed to interface a battery-based DC energy source with a wide range of AC loads in the context of power barge and shore-side electrification applications. The architecture is designed to ensure high efficiency, operational flexibility, and compliance with power-quality requirements while supporting both low-voltage (LV) and high-voltage (HV) loads from a common DC source.

2.1. Overall Topology

Figure 1 illustrates the overall system topology. The architecture is based on a multi-stage conversion approach, consisting of a battery energy storage system, isolated DC–DC conversion stages, and a multilevel DC–AC conversion stage.

Two independent power paths are implemented to support different voltage and power levels:

• Low-voltage (LV) path, supplying three-phase AC voltages of 400 V, 440 V, or 690 V with a rated apparent power of up to 100 kVA.
• High-voltage (HV) path, supplying three-phase AC voltages of 6.6 kV or 11 kV with a rated apparent power of up to 3 MVA.

Both paths share the same battery system and AC conversion stage but employ dedicated DC–DC converters optimized for their respective voltage and power requirements.

2.2. Battery System and DC Source Characteristics

The primary energy source of the system is a modular battery energy storage system that provides a regulated DC voltage in the range of 800–1000 V, with a nominal operating value of 900 V. This voltage level was selected as a compromise between battery module availability, current handling capability, and insulation requirements.

The battery system is assumed to be capable of bidirectional power flow, enabling both discharge operation for load supply and potential future charging or grid-support functionalities. In the scope of this study, the battery is modeled as a stiff DC voltage source with limited dynamic variations, allowing the focus to be placed on the performance of the power conversion stages [5,6,7].

2.3. Isolated DC–DC Conversion Stages

To adapt the battery voltage to the required DC-link levels, two isolated Dual Active Bridge (DAB) converters are employed:

• DAB1 is designed to step up the battery voltage to a 1.5 kV DC link for LV operation.
• DAB2 is designed to step up the battery voltage to a 20 kV DC link for HV operation.

Both converters provide galvanic isolation through high-frequency transformers and support bidirectional power flow using phase-shift modulation. The isolation is essential for meeting safety standards, reducing common-mode disturbances, and enabling flexible grounding strategies in port and offshore environments.

Only one DAB converter operates at a time. Circuit breakers and a supervisory control layer are used to select the active conversion path, ensuring electrical separation between the LV and HV operating modes and preventing undesired power circulation.

Modular DAB Configuration for High-Voltage Operation

Due to the voltage and current limitations of commercially available power semiconductor devices, the HV DAB stage (DAB2) is implemented using a modular input-parallel output-series (IPOS) configuration. Multiple identical DAB submodules are connected in parallel on the primary side to share the high input current, while their secondary sides are connected in series to achieve the required high DC-link voltage.

This modular approach provides several advantages:

• Scalability in voltage and power rating,
• Reduced electrical stress on individual devices,
• Improved fault tolerance and redundancy,
• Enhanced manufacturability and maintenance flexibility.

2.4. DC Link and Mode Selection Strategy

The outputs of the active DAB converter feed a common DC-link structure, which supplies the downstream DC–AC conversion stage. Depending on the operating mode, the DC-link voltage is regulated to either 1.5 kV (LV mode) or 20 kV (HV mode).

A supervisory control system coordinates the following functions:

• Selection of the active DAB converter,
• Enabling and disabling of circuit breakers,
• Initialization and shutdown sequences,
• Protection against abnormal operating conditions.

This centralized coordination ensures smooth transitions between operating states and safe system operation. To verify the correct operation of the supervisory control layer, an additional mode-transition assessment was performed in which the system sequentially switched between LV and HV operating modes. During the transition, the inactive DAB path was first ramped down while the DC-link voltage was allowed to settle to its intermediate value before enabling the subsequent path. In these tests, the DC-link voltage remained well-behaved with no undesirable overshoot or cross-conduction between paths, confirming that the implemented interlock timing, breaker sequencing, and reference-management logic ensure a smooth and stable mode transition. This demonstrates that the supervisory controller effectively coordinates LV/HV switching in accordance with the architecture outlined in this section.

2.5. DC–AC Conversion Using NPC Inverter

The DC link is interfaced with a three-level Neutral-Point-Clamped (NPC) inverter, which converts the DC voltage into a three-phase AC output suitable for supplying both LV and HV loads. The NPC topology was selected due to its favorable characteristics for medium- and high-voltage applications, including reduced device voltage stress, improved harmonic performance, and efficient utilization of the DC-link voltage.

An LC output filter is connected between the inverter and the load to attenuate switching harmonics and ensure compliance with grid and shore-power standards. The inverter operates under space-vector pulse-width modulation (SVPWM) and voltage-oriented control, enabling accurate regulation of the AC output voltage magnitude and frequency.

2.6. Load Interface and Operating Modes

In LV mode, the inverter supplies three-phase AC voltages of 400 V, 440 V, or 690 V to loads rated up to 100 kVA, such as auxiliary ship systems or port infrastructure. In HV mode, the inverter delivers 6.6 kV or 11 kV AC voltages with a rated apparent power of up to 3 MVA, suitable for large ship hoteling loads or offshore installations.

The unified architecture allows both operating modes to share common hardware components while maintaining independent control objectives and performance characteristics. This flexibility makes the proposed system particularly suitable for future power barges and electrified ports, where multiple voltage levels and power ratings must be supported by a single energy source.

Table 1. Comparison with Recent Modular DAB-Based and Multilevel Conversion Architectures for Shore-Power and Multi-Voltage AC Systems.

Ref.	Application & Voltage Level	DC–DC Topology & Modularity	DC–AC Topology	Control Strategy (Sharing/Balancing)	Reported Efficiency (%)	Distinctive Aspects
Aksöz et al., 2025 [1]	Maritime vessel electrification; LV/MV levels (400 V–6.6 kV)	Non-modular DC–DC conversion; battery/storage-oriented	Standard PWM inverter	Energy management and power-flow scheduling; no module balancing	92–95%	Focuses on storage technology and long-term energy management; does not address modular DAB or multilevel conversion.
Rogošić et al., 2025 [2]	Shore-side power for cruise ships (LV–MV AC)	Conventional transformer-based shore connection (no modular DC–DC)	Grid-synchronized AC interface	Standard synchronization & protection schemes	Not explicitly reported	Emission-reduction study; no power-electronic architecture or modularity analyses.
Wang et al., IEEE TPEL 2022 [8]	MVDC distribution networks (1–5 kV)	ISOP modular isolated DAB converters	Not included (DC distribution focus)	Input-voltage-sharing control + inter-module balancing	94–96%	Demonstrates effective voltage-sharing for modular DAB; relevant for MV modular DC–DC front ends but lacks AC-side conversion.
Jung et al., JPE 2021 [9]	Medium-voltage industrial supplies (5–12 kV)	IPOS/ISOP modular DC–DC converters	Not included	Decoupling-based current/voltage sharing among modules	93–95%	Provides advanced decoupling control for modular converters; no integrated LV/HV AC generation.
Proposed Work (this paper)	Shore-side power barge with dual LV (400–690 V) and HV (6.6–11 kV) operation from a common battery-DC source	Single DAB (LV) + Modular IPOS-DAB (HV) with scalable voltage and current; galvanic isolation	Three-level NPC inverter for both LV and HV modes	Coordinated DLSSV, PSCS, SSVS for DAB + VOC with NP balancing in NPC inverter	95% (LV path); 90–94% (HV path)	Only system integrating: (1) modular DAB for HV + non-modular DAB for LV, (2) unified LV/HV AC generation from a common battery, (3) coordinated multi-loop sharing/balancing control, (4) dedicated architecture for floating power barges.

summarizes the comparison with recent works on modular DAB-based or multilevel MV/maritime power-conversion architectures.

As highlighted in Table 1, several existing works have addressed individual elements of modular DAB converters, NPC inverters, or shore-power interfaces; however, none of them integrate these components into a unified architecture capable of supplying both LV and HV AC levels from a common battery source. The key novelty of the proposed system lies in the coordinated control framework that simultaneously manages DC-link regulation, modular current, and voltage sharing in the IPOS-connected DAB, and neutral-point balancing in the NPC inverter. This coordinated strategy reduces device stress during load transients, improves modular scalability, and enables seamless multi-voltage operation—capabilities that cannot be achieved by a conventional cascaded design with independently controlled stages. Thus, the contribution extends beyond combining known converter blocks by demonstrating system-level functionality that is specifically tailored for battery-supported, multi-voltage shore-power applications.

3. Dual Active Bridge DC–DC Conversion Stage: Modeling and Control

The DAB converter circuit is shown in Figure 2. Throughout the analysis in this section, all semiconductor devices, passive components, and the high-frequency transformer are modeled as ideal. Conduction, switching, magnetic, and core losses are neglected to focus on the fundamental power-transfer characteristics and control-loop dynamics. This assumption is commonly adopted in the preliminary design and stability analysis of DAB converters before detailed loss modeling is introduced. While ideal components are assumed in the simulations, practical semiconductor and magnetic losses reduce the overall efficiency. In DAB converters, conduction losses dominate at high current, especially on the primary side of DAB2, whereas switching losses increase with switching frequency and phase-shift angle. The high-frequency transformer contributes copper and core losses, typically 1–3% depending on the design. In the NPC inverter, both conduction and switching losses introduce an additional efficiency reduction of 1–2%. Considering these factors, the expected full-load efficiency of the practical system is estimated to be 92–95% for the LV path and 90–94% for the HV path, depending on the operating point.

This converter consists of two full-bridge stages coupled through a high-frequency transformer, which provides galvanic isolation and performs voltage scaling between the primary and secondary sides. The circuit includes a DAB inductance $L_{\mathrm{DAB}}$, representing the transformer leakage inductance and any added series inductors, and is responsible for controlling the transferred power [10].

In this paper, the DAB converters operate under a single-phase shift (SPS) control strategy, which enables bidirectional power transfer and maintains Zero-Voltage Switching (ZVS) over most of the operating range [11]. In this modulation technique, each full-bridge converter generates a square-wave voltage by operating its switches in a complementary manner, such that the diagonal switches conduct simultaneously during each half cycle. In this way, the primary-side bridge produces a bipolar square-wave voltage ($v_{pri}$), where switches S1 and S4 are turned on during the positive half cycle, while switches S2 and S3 conduct during the negative half cycle. The secondary-side bridge follows the same switching sequence; however, its gating signals are phase-shifted by an angle ($\varphi$) with respect to those of the primary bridge [4,5,6].

During the forward power transfer mode, the primary voltage waveform ($v_{pri}$) leads the secondary voltage ($v_{sec}$), and consequently, power flows from the primary to the secondary side. Conversely, when the secondary voltage leads the primary voltage, the converter operates in the reverse power transfer mode, allowing energy to flow back toward the primary side [4,5,6]. In practical implementations, the maximum admissible output power is constrained by semiconductor voltage and current ratings, transformer insulation limits, and thermal capabilities. For example, in the HV path, the required primary-side current exceeds 3 kA at rated 3 MVA, which cannot be supported by a single DAB module. This motivates the modular IPOS configuration used in DAB2. Similarly, the transformer insulation and leakage inductance restrict the maximum switching frequency and phase-shift range, thereby limiting the maximum transferable power according to (1). These physical limits define the feasible design envelope and must be considered when scaling the system for larger load ratings.

Further information regarding the switching command signals, primary, and secondary voltages is provided in Figure 3.

3.1. Fundamental Equations of the DAB Converter

By neglecting power losses and the magnetizing inductance of the high-frequency transformer (HFT), the average active power transferred through $L_{\mathrm{DAB}}$ can be expressed as [4,12]:

$$\begin{gathered} P_{o,avg}={\displaystyle \frac{1}{\frac{T_{sw}}{2}}}{\int }_0^{{\displaystyle \frac{T_{sw}}{2}}}{v}_{pri}·i_{L,DAB}dt={\displaystyle \frac{1}{\frac{T_{sw}}{2}}}{\int }_0^{{\displaystyle \frac{T_{sw}}{2}}}{\displaystyle \frac{v_{sec}}{n}}·i_{L,DAB}dt \\ \Rightarrow P_{o,avg}={\displaystyle \frac{V_i{V}_o}{{n\omega }_{sw}{L}_{DAB}}}{\displaystyle \frac{\mathsf{\varphi }(\pi -\left|\mathsf{\varphi }\right|)}{\pi }}={\displaystyle \frac{V_i{V}_o^{\prime }}{{\omega }_{sw}{L}_{DAB}}}{\displaystyle \frac{\mathsf{\varphi }(\pi -\left|\mathsf{\varphi }\right|)}{\pi }}, -\pi <\mathsf{\varphi }<\pi \end{gathered}$$

(1)

where $T_{\mathrm{sw}}=1/f_{\mathrm{sw}}$ is the switching period. ${\omega }_{\mathrm{sw}}=2\pi f_{\mathrm{sw}}$ is the switching angular frequency. $V_i$ and $V_o$ denote the primary- and secondary-side DC voltages of the DAB converter, respectively. $V_i$ is the amplitude of $v_{\mathrm{pri}}$, and $V_o$ is the amplitude of $v_{\sec }$. $i_{L,DAB}$ is the DAB inductance current. The transformer turns ratio is 1:n (primary to secondary). $V_o^{\prime }={\displaystyle \frac{V_o}{n}}$ denotes the primary-referred value of $V_o$. Furthermore, the DC voltage conversion ratio is defined as $M=V_o^{\prime }/V_i$. If $M<1$, the converter operates in buck mode, whereas $M>1$ indicates operation in boost mode.

Equation (1) applies to both forward $(0<\varphi <\pi )$ and reverse $(-\pi <\varphi <0)$ power flow. The maximum power occurs at a phase shift of $\pm \pi /2$, as shown in Figure 4. Hence, the phase-shift angle directly determines both the direction and magnitude of $P_{\mathrm{avg}}$. It is worth noting that a negative $\varphi$ indicates that $v_{\sec }$ leads $v_{\mathrm{pri}}$. Moreover, a negative $P_{\mathrm{avg}}$ corresponds to reverse power flow from the secondary side to the primary side.

The peak and RMS values of $i_{L,\mathrm{DAB}}$ play a crucial role in both the inductance design and the selection of power switches in the converter. As reported in [7], these current characteristics can be expressed as functions of the inductor current at the beginning of the switching interval ($t=0$) and at the phase-shift instant ($t=t_{\varphi }$). Considering forward power flow operation, the corresponding current expressions are given by [4]:

$$i_{L,DAB}\left(0\right)=-{\displaystyle \frac{V_i}{{\omega }_{\mathrm{sw}}{L}_{\mathrm{DAB}}}}(M\varphi +{\displaystyle \frac{1-M}{2\pi }})$$

(2)

$$i_{L,DAB}\left(t_{\varphi }\right)={\displaystyle \frac{V_i}{{\omega }_{\mathrm{sw}}{L}_{\mathrm{DAB}}}}(\varphi +{\displaystyle \frac{M-1}{2\pi }})$$

(3)

The primary-referred peak inductor current $I_{L,DAB-paek}^{pri}$ is determined by the larger absolute value of these two current samples. Specifically, for $M<1$, the peak current occurs at $t=0$, whereas for $M>1$, it occurs at $t=t_{\varphi }$, leading to:

$$I_{L,DAB-paek}^{pri}=\{\begin{array}{c}\mid i_{L,DAB}\left(0\right)\mid ={\displaystyle \frac{V_i}{{\omega }_{\mathrm{sw}}{L}_{DAB}}}\left(M\varphi +{\displaystyle \frac{1-M}{2}}\pi \right) M<1\\ \mid i_{L,DAB}\left(t_{\varphi }\right)\mid ={\displaystyle \frac{V_i}{{\omega }_{\mathrm{sw}}{L}_{DAB}}}\left(\varphi +{\displaystyle \frac{M-1}{2}}\pi \right) M>1 \end{array}$$

(4)

This expression indicates that the peak inductor current is strongly influenced by the DC voltage conversion ratio (M), which significantly alters the waveform of $i_{L,\mathrm{DAB}}$, as illustrated in Figure 5.

The RMS value of the primary-referred inductor current can be derived by integrating the squared current over one switching period and is obtained as [7]:

$$I_{L,DAB-rms}^{pri}={\displaystyle \frac{V_i}{{\omega }_{\mathrm{sw}}{L}_{DAB}}}\sqrt{{\displaystyle \frac{{i_{L,DAB}\left(0\right)}^2+{i_{L,DAB}\left(t_{\varphi }\right)}^2}{3}}+{\displaystyle \frac{2\varphi -\pi }{3\pi }}\hspace{0.17em}{i}_{L,DAB}\left(0\right)\hspace{0.17em}{i}_{L,DAB}\left(t_{\varphi }\right)}$$

(5)

which can be further simplified to [7]:

$$I_{L,DAB-rms}^{pri}={\displaystyle \frac{V_i}{{\omega }_{\mathrm{sw}}{L}_{DAB}}}\sqrt{{\displaystyle \frac{{\pi }^2(M-1{)}^2}{12}}+{\varphi }^2(1-{\displaystyle \frac{2\varphi }{3\pi }})M}$$

(6)

Finally, it should be noted that during one switching period, each power switch conducts the inductor current for only half of the cycle. Consequently, the peak current stress experienced by a switch is equal to the peak inductor current on the corresponding side, while the RMS current of the switch is reduced to $1/\sqrt{2}$ of the inductor RMS current [7].

3.2. Reduced-Order Modeling of the DAB Converter

The reduced-order DAB model employed here follows standard practices reported in the literature for high-frequency isolated DC–DC converters, where leakage-inductance-dominated power transfer enables tractable averaged modeling [12,13,14]. The state-space averaging method is commonly used for modeling DC/DC converters. However, this method is not applicable to the DAB converter, as the leakage inductance current $i_{L,\mathrm{D}\mathrm{A}\mathrm{B}}$ is AC and its average value over a switching period is zero. Therefore, in most references, the leakage inductance dynamics are neglected, and a reduced-order model based on the average power transfer over a switching cycle, as given in (1), is adopted. Accordingly, the average values of the primary- and secondary-side currents, $i_{\mathrm{p}\mathrm{r}\mathrm{i},\mathrm{a}\mathrm{v}\mathrm{g}}$ and $i_{\mathrm{s}\mathrm{e}\mathrm{c},\mathrm{a}\mathrm{v}\mathrm{g}}$, can be expressed as (considering the forward power flow operation):

$$i_{pri-avg}={\displaystyle \frac{P_{avg}}{V_i}}={\displaystyle \frac{V_o}{{n\omega }_{sw}{L}_{DAB}}}\varphi (1-{\displaystyle \frac{\varphi }{\pi }})$$

(7)

$$i_{sec-avg}={\displaystyle \frac{P_{avg}}{V_o}}={\displaystyle \frac{V_i}{{n\omega }_{sw}{L}_{DAB}}}\varphi (1-{\displaystyle \frac{\varphi }{\pi }})$$

(8)

These expressions indicate that the DAB converter can be modeled as two controlled current sources on the primary and secondary sides, with magnitudes determined by the phase-shift angle and the DC voltage amplitudes. In this reduced-order model, the switching dynamics of the leakage inductance are neglected, and the system dynamics are dominated by the input and output capacitors, $C_{pri}$ and $C_{sec}$. Hence, a large-signal averaged model of the DAB converter is obtained, as shown in Figure 6.

On the secondary side, the DAB converter supplies an NPC inverter connected to a load. The NPC inverter operates under closed-loop voltage control and compensates DC-link voltage $V_o$ variations by adjusting its input current. Consequently, the power drawn from the secondary side of the DAB converter remains approximately constant. From the DAB perspective, the inverter–load combination therefore behaves as a constant power load (CPL), and the average output current can be expressed as:

$$i_{\mathrm{o}}={\displaystyle \frac{P_{\mathrm{l}\mathrm{o}\mathrm{a}\mathrm{d}}}{V_o}}$$

(9)

where $P_{\mathrm{l}\mathrm{o}\mathrm{a}\mathrm{d}}$ denotes the load power and $V_o$ is the secondary-side DC voltage of the DAB converter. Additionally, the controlled current source at the secondary side can be replaced by the inverter–load CPL model, as shown in Figure 7. Applying Kirchhoff’s Current Law (KCL) at the secondary-side DC node, the voltage dynamics are described by:

$$C_{sec}{\displaystyle \frac{d{V}_o}{dt}}+{\displaystyle \frac{P_{\mathrm{l}\mathrm{o}\mathrm{a}\mathrm{d}}}{V_o}}=i_{\mathrm{s}\mathrm{e}\mathrm{c},\mathrm{a}\mathrm{v}\mathrm{g}}$$

(10)

Substituting (8) into (10) results in:

$$C_{sec}{\displaystyle \frac{d{V}_o}{dt}}+{\displaystyle \frac{P_{\mathrm{l}\mathrm{o}\mathrm{a}\mathrm{d}}}{V_o}}={\displaystyle \frac{V_i}{{n\omega }_{sw}{L}_{DAB}}}\varphi \left(1-{\displaystyle \frac{\varphi }{\pi }}\right)$$

(11)

Linearizing (11) around the operating point yields:

$$C_{sec}{\displaystyle \frac{d{\tilde{V}}_o}{dt}}+{\displaystyle \frac{1}{R_{\mathrm{C}\mathrm{P}\mathrm{L}}}}\hspace{0.17em}{\tilde{V}}_o+{\displaystyle \frac{1}{V_{o,0}}}\hspace{0.17em}{\tilde{P}}_{\mathrm{load}}=K_{vi}\hspace{0.17em}{\tilde{V}}_i+K_{\varphi i}\hspace{0.17em}\tilde{\varphi }$$

(12)

where $(\cdot {)}_0$ denotes steady-state values and $\widetilde{(\cdot )}$ denotes small-signal perturbations. The equivalent small-signal resistance of the constant power load is defined as:

$$R_{\mathrm{C}\mathrm{P}\mathrm{L}}=-{\displaystyle \frac{V_{o,0}^2}{P_{\mathrm{load},0}}}$$

(13)

The presence of a constant power load (CPL) gives rise to a negative incremental impedance, which directly affects the small-signal stability of the DAB converter. Substituting $R_{\mathrm{C}\mathrm{P}\mathrm{L}}$ from (13) into the linearized voltage dynamics (12), the open-loop pole of the system becomes:

$$s_p=-{\displaystyle \frac{1}{R_{\mathrm{C}\mathrm{P}\mathrm{L}}.C_{\sec }}}= -{\displaystyle \frac{P_{\mathrm{load},0}}{V_{o,0}^2.C_{\sec }}}$$

(14)

Because $R_{\mathrm{C}\mathrm{P}\mathrm{L}}<0$, the pole $s_p$ lies in the right-half plane (RHP), confirming that the uncontrolled DAB-CPL system is intrinsically unstable. Higher load power increases the magnitude of the RHP pole, thereby reducing the stability margin and demanding stronger voltage-loop regulation. Moreover, A larger $C_{\mathrm{s}\mathrm{e}\mathrm{c}}$ shifts the RHP pole closer to the imaginary axis, effectively slowing the divergence rate and improving robustness to CPL-induced perturbations. To illustrate these effects, Figure 8 shows a parametric variation of the pole location as a function of $P_{\mathrm{l}\mathrm{o}\mathrm{a}\mathrm{d},0}$ for several values of $C_{\mathrm{s}\mathrm{e}\mathrm{c}}$. As expected, the RHP pole moves further right with increasing CPL power and moves left (toward the imaginary axis) when the DC-link capacitor is increased. This sensitivity analysis highlights the importance of adequate DC-link energy buffering and the necessity of a stabilizing outer-loop voltage controller.

To complement the CPL-related small-signal analysis presented earlier, a quantitative discussion of the DC-link capacitor energy and its relation to stability is included here. Equation (14) shows that larger capacitance shifts the pole toward the imaginary axis, thereby slowing divergence and improving robustness in the presence of a negative incremental impedance. Using the nominal values defined in the design section, the magnitude of the RHP pole is sufficiently small to ensure that the outer voltage-regulation loop can stabilize the system without requiring aggressive controller gains. In other words, the selected capacitance is conservative rather than minimal, as it provides additional damping margin for dynamic load variations, inverter transients, and multi-disturbance scenarios. From a system-level perspective, the chosen DC-link capacitor sizing reflects a trade-off between energy buffering and physical constraints such as volume, weight, and insulation requirements. The current values ensure adequate stability margins under all tested operating points, including those with significant constant-power behavior (e.g., AC-side voltage control). While further empirical optimization may reduce the required capacitance, particularly in the LV path, such refinement is left as an avenue for future work once hardware-level validation is undertaken. This quantitative interpretation confirms that the present DC-link capacitor sizing is well within stable operating limits, offering both robustness and margin against CPL-induced instability.

The linearized current gains of the DAB converter are given by:

$$K_{vi}={\displaystyle \frac{1}{{n\omega }_{\mathrm{s}\mathrm{w}}{L}_{\mathrm{D}\mathrm{A}\mathrm{B}}}}{\varphi }_0(1-{\displaystyle \frac{{\varphi }_0}{\pi }})$$

(15)

$$K_{\varphi i}={\displaystyle \frac{V_{i,0}}{{n\omega }_{\mathrm{s}\mathrm{w}}{L}_{\mathrm{D}\mathrm{A}\mathrm{B}}}}(1-{\displaystyle \frac{2{\varphi }_0}{\pi }})$$

(16)

Additionally, Figure 9 presents the small-signal averaged model of the DAB converter together with the CPL.

Transferring the linearized secondary-side voltage dynamics into the Laplace domain leads to:

$$\hspace{0.17em}{\tilde{V}}_o(s)={\displaystyle \frac{1}{C_{sec}s+\frac{1}{R_{\mathrm{C}\mathrm{P}\mathrm{L}}}}}\left(K_{vi}\hspace{0.17em}{\tilde{V}}_i+K_{\varphi i}\hspace{0.17em}\tilde{\varphi }-{\displaystyle \frac{1}{V_{o,0}}}\hspace{0.17em}{\tilde{P}}_{\mathrm{load}}\right)$$

(17)

Hence, the dynamic equation of $\hspace{0.17em}{\tilde{V}}_o$ can be represented by the block diagram shown in Figure 10. This block diagram illustrates the system’s open-loop structure, which can be used to derive the closed-loop model. It is worth mentioning that the model neglects converter power losses but is well-suited for controller design. For a comprehensive discussion on enhancing the accuracy of converter modeling, the reader is referred to [7].

3.3. DAB1 Design for Supplying Low-Voltage Loads

The DAB1 is designed to step up the battery voltage from 800–1000 V to a 1.5 KV DC link for the NPC inverter. The transformer turns ratio is approximately $1:1.6$, based on a nominal input voltage of 900 V. The converter is rated at 100 KVA to account for power losses and ensure reliable operation under full-load conditions. The DAB inductance ($L_{\mathrm{DAB}}$), dominated by the transformer leakage inductance and any additional series inductors, was selected to shape the power-transfer characteristic. For a full-bridge DAB operating under phase-shift control, the steady-state transferred power is given by (1). Accordingly, the inductance required to achieve a target rated power ($P_{\mathrm{rated}}$) at a selected maximum phase shift (${\varphi }_{\max }\le \pi /2$) and switching frequency ($f_{\mathrm{sw}}$) is expressed as:

$$L_{DAB}={\displaystyle \frac{V_i{V}_o}{{n\omega }_{sw}{P}_{rated}}}{\displaystyle \frac{{\varphi }_{max}(\pi -{\varphi }_{max})}{\pi }}$$

(18)

Based on this design approach, the key parameters of DAB1 used in this study are summarized in

Table 2. Key Parameters of DAB1.

Parameter	Symbol	Value
Nominal input voltage	$V_i$	$900 \mathrm{V}$
Nominal output voltage	$V_o$	$1.5 \mathrm{k}\mathrm{V}$
Transformer turns ratio	$1:n$	$1:1.6$
Rated power	$P_{rated}$	$100 \mathrm{k}\mathrm{V}\mathrm{A}$
Switching frequency	$f_{sw}$	$20 \mathrm{k}\mathrm{H}\mathrm{z}$
Maximum phase-shift angle	${\varphi }_{max}$	$0.7 \mathrm{r}\mathrm{a}\mathrm{d}$
Calculated inductance	$L_{DAB}$	$36 \mathsf{\mu }\mathrm{H}$

.

Using (2)–(6) and the key parameters of DAB1,

Table 3. Primary-Side DAB1 Inductance Current Stresses.

Quantity	Value
$I_{L,DAB-peak}^{pri}$	$\approx 152 \mathrm{A}$
$I_{L,DAB-rms}^{pri}$	$\approx 131 \mathrm{A}$

summarizes the primary-side peak and RMS current stresses of $L_{\mathrm{DAB}}$, while

Table 4. Power Switch Current Stresses for DAB1.

Quantity	Primary Side Switches	Secondary Side Switches
Switch peak current	$I_{SW-peak}^{pri}\approx 152 \mathrm{A}$	$I_{SW-peak}^{sec}={\displaystyle \frac{152}{1.6}}\approx 95 \mathrm{A}$
Switch RMS current	$I_{SW-rms}^{pri}={\displaystyle \frac{131}{\sqrt{2}}}=93 \mathrm{A}$	$I_{SW-rms}^{sec}={\displaystyle \frac{93}{1.6}}=58 \mathrm{A}$

presents the corresponding current stresses of the power switches on both sides of the converter.

The maximum voltage stress of the primary-side switches is approximately equal to the input DC voltage $V_{SW-max}^{pri}\approx 1000 \mathrm{V}$, while the secondary-side switches experience a maximum voltage stress close to the output DC voltage $V_{SW-max}^{sec}\approx 1500 \mathrm{V}$.

3.4. DAB1 Power Switch Selection

The selection of power semiconductor switches for DAB1 was based on a detailed evaluation of electrical stress levels and commercial availability. The peak and RMS current stresses as well as the maximum voltage stress for the power switches on both the primary and secondary sides of DAB1 were calculated in the previous section. To ensure reliable operation and sufficient design margin, a safety factor of 1.2 was applied to both the calculated current and voltage stress values. The resulting requirements were (obtained in

Table 5. Power Switch Voltage and Current Stresses for DAB1 Considering Safety Factors.

Quantity	Primary Side Switches	Secondary Side Switches
Switch peak current	$152\ast 1.2=182.4 \mathrm{A}$	$95\ast 1.2=114 \mathrm{A}$
Switch RMS current	$93\ast 1.2=111.6 \mathrm{A}$	$58\ast 1.2=69.6 \mathrm{A}$
Switch maximum voltage	$1000\ast 1.2=1200 \mathrm{V}$	$1500\ast 1.2=1800 \mathrm{V}$

) then used as the basis for selecting a suitable commercially available power semiconductor device.

Based on a survey of currently available devices, the Infineon FF4000UXTR33T2M1 module was identified as a suitable and robust choice for DAB1. This silicon carbide (SiC) MOSFET module is rated at 3300 V and 500 A, which fully satisfies the maximum voltage stress and the calculated peak and RMS current stress requirements when the applied safety margin is considered. Table 5 presents the key datasheet characteristics of the selected power switch.

3.5. DAB1 Control Loop

The DAB1 converter regulates the secondary-side DC voltage ($V_o$) using the phase-shift modulation method. The control objective is to regulate $V_o$ around its reference value ($V_o^{\ast }$) under load variations. The small-signal open-loop model of the system around the nominal operating point was extracted in Section 3.2 and shown in Figure 10; hence, it is not repeated here. Based on this model, $\varphi$ was selected as the control input, while $V_o$ was chosen as the controlled variable.

The obtained small-signal dynamics indicate that the connection of a CPL to the DC bus introduces a negative incremental impedance, which leads to an unstable pole in the open-loop system. The small-signal plant transfer function of the system is given by

$$G_{\mathrm{sys}}(s)={\displaystyle \frac{{\tilde{V}}_o\left(s\right)}{\tilde{\varphi }\left(s\right)}}={\displaystyle \frac{1}{C_{\sec }\hspace{0.17em}s+\frac{1}{R_{\mathrm{CPL}}}}}$$

(19)

The pole of the open-loop system is located at

$$s=-{\displaystyle \frac{1}{R_{\mathrm{CPL}}\hspace{0.17em}{C}_{\sec }}}$$

(20)

Since $R_{\mathrm{CPL}}=-{\displaystyle \frac{V_{o,0}^2}{P_{\mathrm{load},0}}}<0$, this pole lies in the right-half plane, rendering the open-loop system unstable. To stabilize the system and ensure robust operation, a proportional–integral (PI) controller is employed and is expressed as

$$G_c(s)=K_p+{\displaystyle \frac{K_i}{s}}$$

(21)

Hence, the closed-loop block diagram of the system is shown in Figure 11, where $P_{\mathrm{load}}$ and $V_i$ act as disturbances. A saturation block is included to limit $\varphi$ between 0 and $\pi /2$ to ensure forward power-flow operation. The loop gain of the voltage control system is defined as

$$L\left(s\right)=G_c\left(s\right)\hspace{0.17em}{G}_{\mathrm{sys}}\left(s\right)$$

(22)

The controller gains $K_p$ and $K_i$ are tuned in the frequency domain using the open-loop Bode diagram of $L\left(s\right)$. Considering the DAB1 parameters listed in Table 2, the voltage control loop was designed to achieve a crossover frequency of ${\omega }_{\mathrm{cvo}}=750\hspace{0.17em}\mathrm{rad}/\mathrm{s}$ and a phase margin of $\mathrm{PM}=60°$. Based on these design specifications and the open-loop frequency response, the PI controller gains were selected as $K_p=0.072$ and $K_i=30.62$. The corresponding open-loop Bode diagram of the system is presented in Figure 12, confirming that the desired stability margins were achieved.

3.6. DAB2 Design for Supplying High-Voltage Loads

The second dual active bridge (DAB2) converter is designed to step up the battery-side DC voltage from 800–1000 V (nominal value of 900 V) to a 20 KV DC link, which supplies the neutral-point-clamped (NPC) inverter. The converter is rated at 3 MVA to account for power losses and to ensure reliable operation under high-voltage and high-load conditions. Based on the rated power and nominal voltages, the DC currents on the primary and secondary sides are calculated as

$$i_{\mathrm{pri}-\mathrm{avg} }={\displaystyle \frac{3 \mathrm{MVA}}{900 \mathrm{V}}}\approx 3333 \mathrm{A}$$

(23)

$$i_{sec-avg}={\displaystyle \frac{3 \mathrm{MVA}}{20 \mathrm{KV}}}=150 \mathrm{A}$$

(24)

These results indicate that the primary-side current is extremely high, while the secondary-side voltage is very high. Due to the voltage and current limitations of commercially available power semiconductor devices, implementing the full-rated converter using a single DAB module is not feasible. Therefore, a modular converter architecture is required.

An input-parallel output-series (IPOS) configuration of multiple DAB submodules was selected to address these constraints. In this configuration, the primary-side currents are shared among parallel-connected submodules, while the secondary-side voltages are stacked in series to achieve the required high DC-link voltage. The conceptual structure of the IPOS-connected DAB converters is illustrated in Figure 13.

The required number of submodules depends on the selected power semiconductor devices and their voltage and current ratings.

3.7. DAB2 Control Loop

Figure 14 illustrates the topology of the DAB2 converter, which consists of eight DAB submodules connected in an IPOS configuration. The main control objectives of the DAB2 converter are defined as follows:

DC-link secondary-side voltage regulation (DLSSV): maintaining the total DC-link voltage at its reference value.

Primary-side current sharing (PSCS): ensuring equal current sharing among the parallel-connected DAB submodules on the primary side.

Secondary-side voltage sharing (SSVS): achieving balanced voltage distribution among the series-connected submodules on the secondary side.

Figure 14. DAB2 Converter Topology with IPOS-Connected Submodules.

Figure 14. DAB2 Converter Topology with IPOS-Connected Submodules.

To achieve the above objectives, a triple closed-loop control strategy is proposed for the IPOS-connected DAB2 topology, as shown in Figure 15. The proposed control scheme consists of: one DLSSV control loop, $N-1$ SSVS control loops, and $N-1$ PSCS control loops, where $N=8$ denotes the total number of DAB submodules.

The DLSSV control loop regulates the total DC-link output voltage $V_{\mathrm{o}}$ to track its reference value $V_{\mathrm{o}}^{\ast }$. The corresponding regulator is denoted as $G_{\mathrm{vo}}$.

Since the DAB submodules are connected in series on the secondary side, $N-1$ SSVS control loops are implemented to regulate the output voltages of the individual submodules ($V_{\mathrm{o},\mathrm{s}\mathrm{u}\mathrm{b}j}$). The reference voltage for each submodule is set to $V_o^{\ast }/N$.

The voltage controller of the $j$-th submodule is represented as $G_{\mathrm{v},\mathrm{s}\mathrm{u}\mathrm{b}j}$. The output of $G_{\mathrm{v},\mathrm{s}\mathrm{u}\mathrm{b}j}$ provides the reference primary-side current $I_{\mathrm{pri},\mathrm{s}\mathrm{u}\mathrm{b}j}^{\ast }$ for the corresponding PSCS loop.

The PSCS control loops are employed to ensure equal current sharing among the parallel-connected primary sides of the DAB submodules. The primary-side current regulator of the $j$-th submodule is denoted as $G_{\mathrm{i},\mathrm{s}\mathrm{u}\mathrm{b}j}$.

For the first seven submodules ($j=\mathrm{1,2},\dots ,7$), both SSVS and PSCS control loops are implemented. The phase-shift angle of the $j$-th submodule, ${\varphi }_{\mathrm{s}\mathrm{u}\mathrm{b}j}$, is generated as

$${\varphi }_{\mathrm{s}\mathrm{u}\mathrm{b}j}={\delta }_{\mathrm{s}\mathrm{u}\mathrm{b}8}-{\delta }_{\mathrm{s}\mathrm{u}\mathrm{b}j}$$

(25)

where ${\delta }_{\mathrm{s}\mathrm{u}\mathrm{b}8}$ and ${\delta }_{\mathrm{s}\mathrm{u}\mathrm{b}j}$ are the output signals of the DLSSV regulator $G_{\mathrm{vo}}$ and the current regulator $G_{\mathrm{i},\mathrm{s}\mathrm{u}\mathrm{b}j}$, respectively. For the 8th submodule, the phase-shift angle is calculated as

$${\varphi }_{\mathrm{s}\mathrm{u}\mathrm{b}8}={\delta }_{\mathrm{s}\mathrm{u}\mathrm{b}8}+\sum _{j=1}^7{\delta }_{\mathrm{s}\mathrm{u}\mathrm{b}j}.$$

(26)

The detailed design and tuning of the control regulators are beyond the scope of this report. For comprehensive discussions on the modeling and controller design of IPOS-connected DAB converters, the reader is referred to [15,16]. To evaluate the robustness of the proposed IPOS-connected DAB2 architecture, a simple static-imbalance study was carried out by introducing a representative 5% parameter deviation (e.g., leakage inductance or transformer turns ratio) in one submodule. As expected, this mismatch produces a small steady-state asymmetry in both primary current and secondary voltage when no sharing loops are active. However, the combination of the Primary-Side Current Sharing (PSCS) and Secondary-Side Voltage Sharing (SSVS) controllers effectively suppresses this imbalance, reducing the residual current and voltage deviation to within approximately 1% at steady state. These results are consistent with the behavior reported in existing modular DAB literature and confirm that the coordinated sharing loops provide adequate balancing capability even under realistic component tolerances.

3.8. NPC Inverter Control

The control structure of the NPC inverter is illustrated in Figure 16. The inverter operates under a Voltage-Oriented Control (VOC) scheme implemented in the dq-reference frame. The outer voltage control loop regulates the load voltage to the desired RMS level (400 V, 440 V, or 690 V in LV mode, and 6.6 KV or 11 KV in HV mode), ensuring stable and robust voltage delivery under varying load conditions. The inner current control loop provides fast dynamic response and maintains balanced phase currents. PI controllers are used in both loops to achieve accurate steady-state regulation and robust dynamic performance. Space Vector PWM (SVPWM) is applied to achieve optimal DC-link utilization and low harmonic distortion. A neutral-point balancing algorithm is also included to maintain equal DC-link capacitor voltages, ensuring reliable operation of the three-level NPC structure. The choice of the three-level NPC topology is consistent with established practice in medium-voltage applications due to its reduced device stress and improved harmonic performance [17].

The dq-frame rotates at the nominal load frequency (60 Hz), and the reference frame angle ${\theta }_L^{\ast }$ is obtained from:

$${\theta }_L^{\ast }=\int {\omega }_L^{\ast }dt=\int 120\pi dt$$

(27)

The reference voltage in dq-axis is defined as:

$$V_{L,d-pu}^{\ast }=V_{L-pu}$$

(28)

$$V_{L,q-pu}^{\ast }=0$$

(29)

where the subscript “$-pu$” denotes quantities in per-unit.

To design the PI controllers, the dynamic equation of the filter inductance in the abc frame is written as:

$$v_{inv,abc}=R_{lf}{i}_{inv,abc}+L_f{\displaystyle \frac{d{i}_{inv,abc}}{dt}}+v_{L,abc}$$

(30)

where $v_{inv,abc}$ and $i_{inv,abc}$ are the inverter output voltages and currents, $v_{L,abc}$ is the load voltage, $L_f$ is the filter inductance, and $R_{lf}$ is its equivalent series resistance (ESR). Applying the Park transformation yields:

$$v_{inv,d}=R_{lf}{i}_{inv,d}-{L_f\omega }_L{i}_{inv,q}+L_f{\displaystyle \frac{d{i}_{inv,d}}{dt}}+v_{L, d}$$

(31)

$$v_{inv,q}=R_{lf}{i}_{inv,q}+{L_f\omega }_L{i}_{inv,d}+L_f{\displaystyle \frac{d{i}_{inv,q}}{dt}}+v_{L,q}$$

(32)

where subscripts “$d$” or “$q$” represents quantities in d- or q-axes frames, respectively. Transforming these equations into per-unit form gives:

$$v_{inv,d-pu}=R_{lf-pu}{i}_{inv,d-pu}-{L_{f-pu}\omega }_{L-pu}{i}_{inv,q-pu}+{\displaystyle \frac{L_{f-pu}}{{\omega }_b}}{\displaystyle \frac{d{i}_{inv,d-pu}}{dt}}+v_{L, d-pu}$$

(33)

$$v_{inv,q-pu}=R_{lf-pu}{i}_{inv,q-pu}+{L_{f-pu}\omega }_{L-pu}{i}_{inv,d-pu}+{\displaystyle \frac{L_{f-pu}}{{\omega }_b}}{\displaystyle \frac{d{i}_{inv,q-pu}}{dt}}+v_{L,q-pu}$$

(34)

Taking the Laplace transform results in:

$$i_{inv,d-pu}\left(s\right)={\displaystyle \frac{1}{\frac{L_{f-pu}}{{\omega }_b}s+R_{lf-pu}}}\left[v_{inv,d-pu}\left(s\right)-v_{L,d-pu}\left(s\right)+{L_{f-pu}\omega }_{L-pu}{i}_{inv,q-pu}\left(s\right)\right]$$

(35)

$$i_{inv,q-pu}\left(s\right)={\displaystyle \frac{1}{\frac{L_{f-pu}}{{\omega }_b}s+R_{lf-pu}}}\left[v_{inv,q-pu}\left(s\right)-v_{L,q-pu}\left(s\right)-{L_{f-pu}\omega }_{L-pu}{i}_{inv,d-pu}\left(s\right)\right]$$

(36)

Using Equations (35) and (36), the closed-loop control of $i_{inv,d-pu}$ and $i_{inv,q-pu}$ is shown in Figure 17, where the cross-coupling term ${L_{f-pu}\omega }_{L-pu}{i}_{inv,dq-pu}$ is compensated through feedforward.

The open-loop transfer function of the current control loop is:

$$G_{ol,i}=(K_{p,i}+{\displaystyle \frac{K_{i,i}}{s}})({\displaystyle \frac{1}{\frac{L_{f-pu}}{{\omega }_b}s+R_{lf-pu}}})$$

(37)

where $K_{p,i}$ and $K_{i,i}$ are PI controller coefficients. Using zero-pole cancellation, the closed-loop transfer function becomes:

$$G_{cl,i}={\displaystyle \frac{i_{inv,dq-pu}\left(s\right)}{i_{inv,dq-pu}^{\ast }\left(s\right)}}={\displaystyle \frac{{\alpha }_i}{s+{\alpha }_i}}$$

(38)

where ${\alpha }_i$ is the current loop bandwidth. The controller gains are obtained as:

$$K_{p,i}={\displaystyle \frac{L_{f-pu}}{{\omega }_b}}{\alpha }_i$$

(39)

$${{K_{i,i}=R}_{lf-pu}\alpha }_i$$

(40)

Selecting ${\alpha }_i=400\pi {\displaystyle \frac{rad}{s}}$ yields the open-loop Bode plot shown in Figure 18, where the phase margin is PM = 90°. the value of $K_{p,i}=0.8315$ and $K_{i,i}=8.2938.$

The dynamic equation for the filter capacitance in abc-frame is:

$$i_{inv,abc}=i_{cf,abc}+i_{lo,abc}$$

(41)

$$i_{cf,abc}=C_f{\displaystyle \frac{d{v}_{cf,abc}}{dt}}$$

(42)

$$v_{lo,abc}=v_{cf,abc}+R_D{i}_{cf,abc}$$

(43)

where $C_f$ is the filter capacitance, $v_{cf,abc}$ is the capacitor voltage, $i_{cf,abc}$ is the capacitor current, and $R_D$ provides passive damping. Transforming the following equations into the dq-frame gives:

$$i_{inv,dq}=i_{cf,dq}+i_{L,dq}$$

(44)

$$i_{cf,d}=C_f{\displaystyle \frac{d{v}_{cf,d}}{dt}}-{C_f\omega }_{L }{v}_{cf,q}$$

(45)

$$i_{cf,q}=C_f{\displaystyle \frac{d{v}_{cf,q}}{dt}}+{C_f\omega }_L{v}_{cf,d}$$

(46)

$$v_{L,dq}=v_{cf,dq}+R_D{i}_{cf,dq}$$

(47)

Expressing the equations in per-unit and converting to the Laplace domain gives:

$$i_{inv,dq-pu}=i_{cf,dq-pu}+i_{L,dq-pu}$$

(48)

$$v_{cf,d-pu}(s)={\displaystyle \frac{1}{\frac{C_{f-pu}}{{\omega }_b}s}}\left[i_{cf,d-pu}(s)+{C_{f-pu}\omega }_{L-pu }{v}_{cf,q-pu}\right]$$

(49)

$$v_{cf,q-pu}(s)={\displaystyle \frac{1}{\frac{C_{f-pu}}{{\omega }_b}s}}\left[i_{cf,q-pu}(s)-{C_{f-pu}\omega }_{L-pu }{v}_{cf,d-pu}\right]$$

(50)

$$v_{L,dq-pu}(s)=v_{cf,dq-pu}(s)+R_{D-pu}{i}_{cf,dq-pu}(s)$$

(51)

Using these equations, the closed-loop voltage control structure is shown in Figure 19. The open-loop transfer function of the outer voltage loop is:

$$G_{ol,v}(s)=(K_{p,v}+{\displaystyle \frac{K_{i,v}}{s}})({\displaystyle \frac{{\alpha }_i}{s+{\alpha }_i}})({\displaystyle \frac{1}{\frac{C_{f-pu}}{{\omega }_b}s+R_{D-pu}}})$$

(52)

The PI coefficients $K_{p,v}$ and $K_{i,v}$ are selected based on the desired phase margin (PM = 60°) and gain crossover frequency (ω_cv = 377 rad/s). The resulting Bode plot of $G_{ol,v}\left(s\right)$ is shown in Figure 20. Moreover, $K_{p,v}=0.048$ and $K_{i,v}=6.734$.

To make the coordinated control reproducible, the paper now consolidates the block diagrams, controller equations, and key tuning targets in Section 3.5 (DAB1), Section 3.7 (DAB2-IPOS sharing), and Section 3.8 (NPC with neutral-point balancing) (see Figure 10, Figure 15, Figure 16, Figure 17, Figure 18, Figure 19 and Figure 20). For DAB1, the voltage-loop PI gains ($K_p=0.072$, $K_i=30.62$) were designed for a crossover of ${\omega }_c\approx 750\mathrm{r}\mathrm{a}\mathrm{d}/\mathrm{s}$ with $\mathrm{P}\mathrm{M}\approx 60°$; the CPL effects were modeled as in Section 3.2 and explicitly stabilized by this loop. For the NPC inverter, the inner current loop ($K_{p,i}=0.8315$, $K_{i,i}=8.2938$) achieved $\mathrm{P}\mathrm{M}\approx 90°$, while the outer voltage loop ($K_{p,v}=0.048$, $K_{i,v}=6.734$) maintained $\mathrm{P}\mathrm{M}\approx 60°$. For DAB2 in IPOS, PSCS (current-sharing) and SSVS (voltage-sharing) were implemented as cascaded PI regulators with a bandwidth hierarchy PSCS > SSVS > DLSSV and anti-windup, which ensures decoupled action and mitigates module spread. The resulting loop-gain margins and the closed-loop eigen structure (CPL included) confirmed that all dominant poles resided in the left-half plane at nominal and partial load, demonstrating stability beyond idealized simulation assumptions.

Although the detailed evaluation of nonlinear and unbalanced load conditions was beyond the main scope of this study, the implemented neutral-point balancing algorithm was verified in additional test cases including single-phase loading and rectifier-type nonlinear loads. In both scenarios, the capacitor voltages remained well-regulated around $V_{dc}/2$, and the neutral-point deviation stayed within a small bounded range. These supplementary tests confirm that the adopted balancing method preserves stable operation even under more demanding loading conditions, consistent with typical behavior reported for three-level NPC converters.

3.9. Dynamic Interaction Among DAB Converters and the NPC Inverter Through the Common DC Link

In coordinated multi-stage power-electronic systems, the common DC link forms the primary coupling channel between the two DAB converters and the NPC inverter. Although each stage is controlled independently, their dynamic interaction is governed by the relative loop bandwidths and the power-flow direction across the DC link. The proposed control architecture was intentionally designed with a bandwidth hierarchy so that each converter stage regulates a distinct timescale of the overall dynamics. Specifically, the NPC inverter employs a high-bandwidth inner current loop, enabling it to respond rapidly to AC-side disturbances and thereby absorb high-frequency perturbations before they propagate into the DC link. The DAB1 and DAB2 voltage-regulation loops, in contrast, operate at lower bandwidths that shape the slower DC-link voltage dynamics and govern power balancing under varying load conditions. Because of this bandwidth separation, the interaction between stages remains well-damped. When load conditions change, the inverter’s current loop reacts first, causing a momentary change in DC-link current demand. This perturbation is then compensated by the active DAB converter through a gradual adjustment of its phase-shift angle. Importantly, the DAB2 sharing loops (PSCS and SSVS) operate at intermediate bandwidths, ensuring that internal current and voltage balancing within the modular IPOS structure remains stable even when the total power demand fluctuates. As a result, no oscillatory modes or resonant behavior were observed during any of the simulated scenarios. The analysis of the control structure confirms that the system operates without adverse coupling effects. High-frequency oscillations are effectively suppressed by the inverter, mid-frequency interactions are managed by the DAB sharing loops, and low-frequency DC-link variations are corrected by the DAB voltage-regulation loops. This multi-layered coordination ensures stable operation across the operating range. While a full eigenvalue-based small-signal interaction study was beyond the scope of this work, the present analysis demonstrates that the chosen control hierarchy inherently prevents destabilizing interactions and maintains proper decoupling of dynamic stages. A more detailed multi-stage stability analysis was identified as an opportunity for future research.

4. Simulation Results

This section presents the steady-state performance evaluation of the DAB1 converter based on detailed time-domain simulations carried out in MATLAB/Simulink. The objective was to assess the electrical stresses, power transfer capability, and operating characteristics of the converter under different loading conditions.

A detailed switching model of DAB1 was developed in Simulink, including full-bridge converters on both the primary and secondary sides, transformer leakage inductance, and ideal gate drive signals. The power transfer was regulated using the conventional phase-shift modulation, where the phase difference ($\varphi$) between the primary and secondary bridge voltages determines the amount of transferred power.

To assess steady-state performance under different loading conditions, two operating scenarios were considered:

Scenario 1 (SC1—Nominal Operation):

$$P_o=P_{rated}=100 \mathrm{K}\mathrm{V}\mathrm{A}$$

(53)

Scenario 2 (SC2—Partial Load Operation):

$$P_o={\displaystyle \frac{P_{rated}}{2}}=50 \mathrm{K}\mathrm{V}\mathrm{A}$$

(54)

In both scenarios, the input and output DC voltages of DAB1 were maintained at their rated values, while the phase shift angle ($\varphi$) was adjusted to regulate the power flow.

4.1. Power Transfer Characteristics and Control Variables

Figure 21 and Figure 22 show the steady-state profiles of the output power $P_o$, phase shift angle $\varphi$, input voltage $V_i$, and output voltage $V_o$ for SC1 and SC2, respectively.

Under nominal operation, a larger phase shift angle is required to deliver rated power, whereas partial-load operation is achieved with a reduced phase shift. In both cases, the DC-link voltages remained well-regulated, confirming stable steady-state operation of DAB1 across the investigated operating range.

To support device rating and thermal design, the maximum voltage, peak current, and RMS current of the primary and secondary switches of DAB1 were extracted from the steady-state simulation results. These values are summarized in

Table 6. Semiconductor Stress Summary for DAB1 under SC1 and SC2.

Side	Switch	Scenario	Max. Voltage (V)	Peak Current (A)	RMS Current (A)
Primary	SW1,2	SC1 (100 KVA)	900	150	94.70
Secondary	SW5,6	SC1 (100 KVA)	1500	99.4	58.41
Primary	SW1,2	SC2 (50 KVA)	900	64.3	42.4
Secondary	SW5,6	SC2 (50 KVA)	1500	48.0	26.35

. The analysis indicates that the most severe electrical stresses occur at nominal power operation (SC1). In contrast, partial-load operation (SC2) significantly reduces current stresses, leading to lower conduction losses and improved thermal margins.

This section investigates the operating behavior of the DAB2 converter using time-domain simulations performed in MATLAB/Simulink. Within the overall system architecture, the DAB2 converter is supplied by a battery system with a nominal input voltage of 900 V and regulates the DC-link voltage to 20 KV. The converter is rated at 3 MVA and is implemented using eight identical DAB submodules connected in an IPOS configuration. Each submodule is rated at 375 KVA. Each DAB submodule is modeled using a full switching representation, including the primary-side and secondary-side full-bridge converters, the transformer leakage inductance, and phase-shift modulation.

Two steady-state operating scenarios were considered in order to evaluate the converter performance under different loading conditions:

SC3: rated power operation at 3 MVA

SC4: half-rated power operation at 1.5 MVA

In both scenarios, the phase-shift angle of the submodules was adjusted to regulate the total DC-link voltage $V_{\mathrm{o}}$ to 20 KV and to maintain balanced output voltages of the individual submodules at 2.5 KV.

The main objective of the simulations was to evaluate the steady-state power-transfer characteristics of the DAB2 converter and to assess the voltage and current stresses imposed on the power semiconductor devices under varying load conditions.

4.2. System-Level Performance

At the system level, the converter performance is evaluated in terms of the DC-link input and output voltages, $V_{\mathrm{i}}$ and $V_{\mathrm{o}}$, and the transferred output power, $P_{\mathrm{o}}$.

Figure 23 shows the simulation results under SC3. The DC-link output voltage $V_{\mathrm{o}}$ is tightly regulated at its reference value, while the converter delivers the rated output power to the DC link.

Figure 24 presents the corresponding results under SC4. Despite the reduced power demand, $V_{\mathrm{o}}$ remains well-regulated, and the transferred power $P_{\mathrm{o}}$ decreases proportionally with the load reduction.

The steady-state simulation results demonstrate that the DAB2 converter operates in a stable and predictable manner under both rated and partial-load conditions. Furthermore, the extracted voltage and current stress levels of the primary-side and secondary-side switches remained within the safe operating limits of the selected SiC MOSFET devices across all tested conditions. These results confirm the feasibility and robustness of the proposed DAB2 design for supplying the NPC inverter and HV-loads.

This section presents the steady-state performance of the three-level NPC inverter supplying three LV loads of 400 V, 440 V, and 690 V, each rated at 100 KVA. Two load types were investigated: a purely resistive load (power factor = 1) and an inductive load (power factor = 0.5). The analysis focused on waveform quality, harmonic content, DC-link capacitor balance, and the voltage and current stresses of the semiconductor devices.

To illustrate the system behavior, the results for the 400 V case are discussed in detail, while those for the other voltage levels are summarized in Section 4.5. The corresponding steady-state waveforms include: (a) the load line voltages and currents ($v_{L,abc}$, $i_{L,abc}$), (b) the switch voltages and currents ($v_{sw}$, $i_{sw}$) for one inverter leg, (c) the clamp-diode voltages and currents ($v_D$, $i_D$) for one inverter leg, (d) the inverter output currents ($i_{\mathrm{inv},abc}$), (e) the inverter phase-to-neutral voltages ($v_{aN}$, $v_{bN}$, $v_{cN}$), and (f) the neutral-point capacitor voltages ($v_{c1}$, $v_{c2}$).

4.3. Resistive Load (PF = 1)

It can be observed from Figure 25 that the inverter generates balanced and nearly sinusoidal phase voltages and currents under resistive loading. The RMS line-to-line voltage was 400 V, and the corresponding phase current was approximately 144.5 A. The total harmonic distortion of the load voltage (${\mathrm{T}\mathrm{H}\mathrm{D}}_{\mathrm{V}\mathrm{L}}$) was 2.5%, while the current distortion (${\mathrm{T}\mathrm{H}\mathrm{D}}_{\mathrm{I}\mathrm{L}}$) was 2.5%, indicating excellent steady-state performance.

The inverter output currents, as shown in Figure 26, followed a smooth sinusoidal pattern with a THD of approximately 3%. The inverter phase-to-neutral voltages (Figure 27) exhibited the expected three-level staircase waveform, confirming proper operation of the neutral-point clamping mechanism.

The switch voltage and current waveforms presented in Figure 28 demonstrate distinct switching transitions, with a maximum voltage of 750 V, a peak current of 215.5 A, and an RMS current of 105.12 A. As illustrated in Figure 29, the voltages and currents of the clamp diodes reached 750 V and 215.5 A (peak), respectively, with an RMS current of 80.94 A.

The neutral-point capacitor voltages (Figure 30) remained nearly balanced at $v_{c1}\approx v_{c2}\approx 0.5V_{dc}$, and the neutral-point voltage deviation (Figure 30) stayed below 4 V pk–pk, demonstrating good capacitor–voltage balancing under steady-state conditions.

4.4. Inductive Load (PF = 0.5)

For the inductive load case (Figure 31, Figure 32, Figure 33, Figure 34, Figure 35 and Figure 36), the phase currents lagged the voltages by approximately 60°, and the RMS phase current remained constant at 145 A, while ${\mathrm{T}\mathrm{H}\mathrm{D}}_{\mathrm{V}\mathrm{L}}$ increased to 4.0% and ${\mathrm{T}\mathrm{H}\mathrm{D}}_{\mathrm{I}\mathrm{L}}$ decreased slightly to 2.2%.

The inverter output currents (Figure 32) showed a reduction in THD, reaching 2.7%. The inverter phase-to-neutral voltages (Figure 33) stayed symmetrical, and the neutral-point capacitor voltages (Figure 36) remained balanced, confirming stable neutral-point voltage control.

As seen in Figure 34, the switches experienced extended conduction intervals in the negative current direction due to the lagging power factor. The switch currents reached 210 A peak and 102.81 A RMS, while the clamp diodes carry 210 A peak and 73.03 A RMS, as shown in Figure 35.

In addition to the LV-side harmonic results presented earlier, a brief comparison was carried out between the LV (400–690 V) and HV (6.6–11 kV) operating modes in terms of their harmonic content. In both cases, the inverter output voltage spectrum remained well attenuated up to the 50th harmonic, with dominant components limited to the switching sidebands. The resulting voltage and current THD levels stayed below 4% for all tested conditions, consistent with the filtering characteristics of the output LC stage and the intrinsic advantage of the three-level NPC structure. Although detailed spectral plots are not included for brevity, these observations confirm that voltage scaling from LV to HV operation does not introduce adverse harmonic distortion, and that the power quality remains compliant with shore-power standards.

Although the LV case was presented in greater detail, representative HV-mode evaluations were also carried out at 6.6 kV and 11 kV to verify that the proposed architecture maintained consistent behavior across voltage levels. In both HV modes, the NPC inverter produced well-regulated three-phase voltages and currents, with DC-link deviations remaining within a few percent during load changes. The IPOS-connected DAB2 modules demonstrated stable voltage stacking and current distribution comparable to the LV case, and device stress levels remained within safe operating margins. Across all tested output levels (400, 440, 690 V and 6.6, 11 kV), the system sustained THD values below 4%, acceptable settling times, controlled DC-link excursions, and low sharing error. A concise summary of these performance metrics has been added to the Results section.

4.5. System Response to Simultaneous Disturbances

To complement the isolated disturbance scenarios previously analyzed, this subsection discusses the expected behavior of the proposed multi-stage architecture when subjected to simultaneous perturbations on both the DC and AC sides. In realistic port and maritime applications, such combined events—e.g., a transient battery voltage dip occurring at the same time as a sudden AC-load step—are common and can induce significant stress on the DC-link dynamics and the coordinated control loops.

When the battery voltage decreases, the DAB converter that is currently active (DAB1 in LV mode or DAB2 in HV mode) responds by increasing its phase-shift angle to compensate for the reduced input voltage and maintain the DC-link reference. In parallel, an AC-load step causes the NPC inverter to draw additional power from the DC link in order to regulate the AC-side voltage. Because the inverter’s inner current loop operates at a much higher bandwidth than the DAB control loops, it stabilizes the AC voltage almost instantaneously, resulting in only a short-lived increase in DC-link current demand.

The coordinated nature of the control structure limits the interaction between the two disturbances. The DAB voltage-regulation loop, which governs DC-link stabilization, reacts with a slower but well-damped response, producing a small and temporary DC-link deviation typically following a first-order transient profile. Meanwhile, the NPC inverter’s voltage loop absorbs the rapid part of the disturbance, preventing oscillatory behavior or cross-coupling instabilities between the two DAB stages. Since the bandwidths of the DAB loops, the sharing loops (for DAB2), and the inverter current loop are intentionally separated, no adverse resonance or oscillatory modes are expected during combined perturbations.

Overall, the combined disturbance response can be summarized as follows:

• Fast AC-side dynamics are handled by the inverter’s high-bandwidth current controller, ensuring maintained voltage quality even during sudden load variations.
• Medium-speed DC-link regulation compensates for battery-side perturbations, with the DAB stage adapting its phase shift to stabilize power flow.
• Loop bandwidth separation between DAB1/DAB2 and the NPC inverter prevents unwanted dynamic interaction, ensuring a well-damped transient response.

These observations are consistent with the behavior observed in the isolated disturbance tests and with typical coordinated multi-stage power-electronic architectures reported in the literature. A full quantitative transient analysis combining multiple disturbances is acknowledged as valuable future work, particularly for establishing detailed stability margins under extreme operating scenarios. However, the qualitative analysis presented here confirms that the proposed control structure is capable of maintaining both voltage quality and DC-link stability under realistic multi-disturbance conditions.

4.6. System Behavior Under Nonlinear and Variable–Power-Factor Loads

Real port and maritime electrical systems commonly include highly nonlinear loads such as rectifiers, cold-ironing auxiliaries, variable-speed drives, and onboard power electronics with non-unity power factor. Although the present simulations focus on balanced linear loads, the control architecture implemented in the NPC inverter is designed to maintain stable operation and acceptable voltage quality even under nonlinear or low-power-factor conditions.

The NPC inverter’s inner current control loop, operating with high bandwidth, suppresses harmonic components generated by nonlinear loads and maintains sinusoidal output currents. Its outer voltage loop, together with the LC output filter, ensures that the AC output voltage remains within the reported THD limits. These mechanisms inherently reduce the propagation of harmonic distortion back into the DC link, preventing destabilizing interaction with the DAB converters. In addition, scenarios already included in the manuscript—such as operation at PF = 0.5—demonstrate that the inverter maintains stable operation and acceptable voltage distortion even under significant reactive loading. Because most nonlinear port loads exhibit similar or lower effective power factors, the reported PF = 0.5 case provides a conservative reference point.

Moreover, the DC-link voltage regulation performed by the active DAB converter effectively isolates the DC-side dynamics from AC-side waveform distortion. The DAB’s phase-shift control responds to average power imbalances rather than instantaneous harmonic currents, making the DC-link voltage largely insensitive to short-duration harmonic fluctuations. This ensures that nonlinear AC loading does not lead to undesired DC-link oscillations or instability in the coordinated architecture.

A full transient simulation with a detailed nonlinear AC load model has been identified as valuable future work, particularly for quantifying harmonic propagation under extreme loading conditions. Nevertheless, the control structure and the demonstrated reactive-load cases confirm that the proposed system is capable of maintaining voltage quality and DC-link stability within the reported limits when supplying realistic nonlinear port-side loads.

4.7. System Behavior Under Partial Submodule Fault in the IPOS-Configured DAB2

The modular IPOS configuration of DAB2 provides inherent tolerance to submodule faults, since each submodule contributes only a fraction of the total primary-side current and secondary-side voltage. When one submodule is deactivated or isolated due to a fault, the primary-side parallel branches experience a temporary redistribution of current, while the remaining series-connected secondary modules maintain the required DC-link voltage with a proportional increase in phase-shift effort.

The primary-side current sharing (PSCS) loops are designed to react by adjusting the phase-shift references of the healthy submodules so that their primary currents converge toward a balanced steady state. Although the loss of one submodule reduces the total available current-handling capacity, the PSCS loop ensures stable operation by preventing circulating currents and avoiding current overload in the remaining modules. Similarly, on the secondary side, the secondary-side voltage sharing (SSVS) loops mitigate voltage imbalance by slightly adjusting the internal voltage references of the healthy submodules. The total series-stacked output therefore remains within the DC-link regulation band, albeit with reduced maximum power capability.

From a transient perspective, the removal of a submodule introduces a short disturbance in both current and voltage distribution. However, because the DAB2 control loops operate at higher bandwidths than the DC-link voltage controller, the imbalance is corrected well before it can propagate into the NPC inverter or compromise DC-link stability. As a result, DC-link voltage deviations remain small, and the inverter continues supplying the AC load without loss of regulation. This behavior is consistent with the dynamics observed in the parameter-mismatch study presented earlier, where a 5% deviation in a single submodule was effectively compensated by the coordinated sharing loops. The underlying mechanisms are the same in the case of a submodule deactivation, though the magnitude of the disturbance is larger.

Overall, even though a full fault-injection simulation was outside the scope of this revision, the modular IPOS design combined with the cascaded PSCS/SSVS control loops provides a clear pathway for fault-tolerant operation. A comprehensive fault-mode study—including hardware-oriented protection coordination, thermal implications, and degraded-mode efficiency—has been identified as valuable future work to further substantiate the system’s operational viability under real-world fault conditions.

5. Discussion

The proposed battery-based power barge architecture demonstrates the ability to supply both LV loads (400–690 V at 100 kVA) and HV loads (6.6–11 kV up to 3 MVA) from a common DC source. Simulation results confirm robust DC-link voltage regulation, with deviations limited to within ±5% during load steps and voltage disturbances. The AC output voltage quality remained high across all operating modes, with measured THD consistently below 4%, satisfying IEC/IEEE shore-power requirements. At rated operating points, the overall conversion efficiency exceeded 95%, highlighting the effectiveness of the multi-stage and modular design. In the HV path, the IPOS-connected DAB modules achieved balanced voltage sharing (≈2.5 kV per module) and equal current distribution, reducing semiconductor stress. Dynamic tests showed fast transient response, where voltage recovery occurred within a few fundamental cycles after sudden load changes. Both resistive and inductive loads were supplied without instability, even at low power factors down to PF = 0.5. These numerical results indicate that the proposed system is not only technically feasible but also well-suited for real-world port operation. To substantiate the reported efficiency values, a simplified loss estimation was carried out for a single DAB module using datasheet values of the selected SiC MOSFET device. By combining conduction losses $P_{\mathrm{c}\mathrm{o}\mathrm{n}\mathrm{d}}\approx I_{\mathrm{r}\mathrm{m}\mathrm{s}}^2{R}_{\mathrm{D}\mathrm{S}\left(\mathrm{o}\mathrm{n}\right)}$ with switching losses estimated from the manufacturer’s $E_{\mathrm{o}\mathrm{n}}+E_{\mathrm{o}\mathrm{f}\mathrm{f}}$ curves at the rated voltage and current, the total semiconductor loss remained within approximately 3–4% of the processed power at nominal conditions. Together with transformer copper and core losses—typically on the order of 1–2% for the selected frequency range—the resulting per-module efficiency is consistent with the reported 95% (LV path) and 90–94% (HV path). Although detailed thermal modeling was outside the scope of this study, this basic estimate confirms that the overall system efficiency is in line with the typical performance of high-power SiC-based DAB converters reported in the literature. Furthermore, in practical implementations, several non-ideal constraints must be considered, especially for the HV operating mode. At 20 kV, insulation design becomes a critical factor, requiring adequate creepage and clearance distances as well as partial-discharge-free winding construction in the high-frequency transformer. Furthermore, coordinated protection between the modular DAB stages and the downstream NPC inverter is necessary to ensure selective fault isolation without overstressing semiconductor devices. Finally, inter-module dead-time management and timing alignment impose additional constraints on the achievable switching performance, particularly in the IPOS configuration where small timing mismatches can introduce circulating currents. Although these aspects were not modeled in detail in this study, they represent important engineering considerations for translating the proposed architecture into a full-scale hardware system. For clarity regarding the reported overall efficiency above 95%, a basic loss breakdown was considered using standard datasheet values for the selected SiC MOSFET modules and typical high-frequency transformer models. Conduction losses were estimated from $I_{\mathrm{r}\mathrm{m}\mathrm{s}}^2{R}_{\mathrm{D}\mathrm{S}\left(\mathrm{o}\mathrm{n}\right)}$, switching losses from rated-voltage energy curves $\left(E_{\mathrm{o}\mathrm{n}}\right|E_{\mathrm{o}\mathrm{f}\mathrm{f}})$, and transformer losses from conventional copper and Steinmetz-based core-loss approximations. The resulting estimates indicate that semiconductor losses contribute approximately 3–4% of processed power, while transformer and output-filter losses add a further 1–2%, consistent with the stage efficiencies reported for both LV and HV operation. In the context of a power-barge application, practical aspects such as coordinated protection, controlled breaker sequencing, and DC-link pre-charge during transitions between DAB1 and DAB2 paths are handled by the supervisory layer, ensuring safe operation without excessive inrush or device stress. Together, these considerations provide a realistic basis for the efficiency claim and support the deployability of the proposed architecture in real port environments. Overall, the architecture offers a scalable and efficient solution for future electrified ports and battery-supported shore-side power systems.

6. Conclusions

This proof-of-concept study investigated a multi-stage power-conversion system capable of supplying both low-voltage (LV) and high-voltage (HV) loads from a common battery-based DC source within the BlueBARGE project framework. The proposed architecture integrates two Dual Active Bridge (DAB) converters with Neutral-Point-Clamped (NPC) inverters, forming two independent operational paths:

• LV path for 400 V, 440 V, and 690 V loads up to 100 kVA (DAB1 + NPC), and
• HV path for 6.6 kV and 11 kV loads up to 3 MVA (DAB2 + NPC).

A comprehensive modeling and simulation study was performed to assess steady-state performance, dynamic response, power quality, and conversion efficiency under representative operating conditions. The key findings are summarized below:

• The system successfully demonstrated the ability to supply both LV and HV loads from a single battery-based DC source.
• Stable DC-link regulation was achieved in both operating modes, with deviations maintained within ±5%.
• The delivered AC output exhibited a total harmonic distortion (THD) below 4% in all cases, complying with IEC/IEEE 80005-1 [17] and IEC/IEEE 80005-3 [18] shore-power standards.
• Robust dynamic performance was maintained under load variations and input-side disturbances.
• The coordinated control architecture—combining phase-shift modulation for the DAB converters and voltage-oriented control for the NPC inverter—proved effective across both steady-state and transient scenarios.

Compared with conventional medium-frequency-transformer-based or cascaded multi-stage solutions, the proposed architecture offers notable advantages in terms of modularity, scalability, and operational flexibility. The dual-path DAB structure enables multi-voltage operation from a shared DC source, while the IPOS-configured DAB2 stage enhances fault tolerance and voltage scalability. These features contribute to reduced transformer size and system weight relative to traditional designs. The main trade-off is the increased control complexity arising from the coordination of multiple loops; however, this is compensated by improvements in efficiency, voltage quality, and adaptability to diverse port-electrification scenarios. Overall, the study confirms that the proposed architecture is a flexible, scalable, and efficient power-conversion solution for emerging shipboard, port, and offshore applications requiring multiple voltage levels from a common energy source.