Design of Fast Leading-Edge Narrow Pulse Circuit Based on Avalanche Transistor Series Structure

Abstract

Avalanche transistors are critical devices for generating fast leading-edge narrow pulses. However, the currently employed base-triggering method limits the output pulse amplitude of the series structure to the bias voltage. To overcome these limitations, this paper presents a novel circuit design based on the series structure of avalanche transistors. By utilizing the base-emitter short contact generation method, the output pulse voltage can be adjusted by varying the input voltage. Furthermore, it is demonstrated that placing a picofarad (pF)-level capacitor in parallel with the avalanche transistor reduces the conduction time, thereby decreasing the falling edge of the output pulse and increasing its slope. Experimental results from a series test involving four avalanche transistors, as constructed in this study, indicate that with an input voltage ranging from 200 to 500 V, the output voltage amplitude is adjustable from 1020 V to 1270 V. When a 15 pF capacitor is added in parallel, the amplitude increases from 1270 V to 1320 V, while the falling edge decreases from 1.27 ns to 1.00 ns. Consequently, the slope rises from 1.00 kV/ns to 1.32 kV/ns. Additionally, the circuit was enhanced, and the fast leading-edge pulse of the output served as the trigger pulse for testing a 500 V withstand voltage FID, yielding an output pulse amplitude of 965 V and a falling edge of 320 ps.

1. Introduction

Pulse power technology [1] finds broad applications in various advanced technological domains, including ultra-wideband radar (UWB) [2,3], biomedicine [4,5], and plasma physics [6,7]. With the continuous expansion and deepening of application scenarios, higher voltage, faster leading edge, and narrower pulse width are crucial parameters, with the pulse power semiconductor switch being a pivotal device in this regard.

Currently, semiconductor switches capable of generating fast, narrow leading pulses include gas switches, drift step recovery diode (DSRD), semiconductor opening switch (SOS), fast ionization dynistors (FID), and photoconductive semiconductor switch (PCSS) [8,9,10,11]. However, the high internal pressure of gas switches imposes geometric limitations, which may result in impedance mismatches during energy transmission. Additionally, DSRD, SOS, and FID are challenging to manufacture, expensive, and infrequently utilized in practice. Notably, FID has relatively stringent triggering requirements. Domestically and internationally, the output from the fast front pulse circuit of the step recovery diode is predominantly employed as the trigger pulse for FID, and the associated trigger circuit is relatively straightforward. The lifespan of PCSS is constrained by the effects of current filamentation and electrode degradation. In recent years, avalanche transistors have garnered significant attention in the pulse power domain due to their low cost and rapid conduction speed.

Due to the relatively low breakdown voltage of individual avalanche transistors, high-voltage pulses can be generated by connecting these transistors in series or by employing avalanche-type Marx circuits to achieve the necessary high amplitude and power. Aimin Zou et al. from Jilin University [12] conducted a series experiment with four avalanche transistors, yielding an output pulse amplitude of 666 V, a rising edge of 3 ns, and a pulse width of 3 ns. Jianwen Tan et al. from Chongqing Medical University [13] developed a circuit comprising 22 avalanche transistors arranged in series to produce square wave pulses with an amplitude of 2.5 kV, a rise time of 2.5 ns, and a pulse width of 12.5 ns. Li Chengxiang et al. from Chongqing University [14] developed a 14-stage avalanche Marx generator based on microstrip transmission theory. By utilizing this theory to mitigate reflection and incorporating series inductors to enhance the output waveform, they achieved an output amplitude of 1015 V and a pulse width of 620 ps. Yu Liang et al. from Chongqing University [15] proposed an improved avalanche Marx circuit. By integrating a protection resistor in series with the second-stage transistor, they effectively suppressed the passive boost voltage, resulting in a 20-stage avalanche Marx that produced a high-voltage pulse with a rising edge of 230 ps and an amplitude of 1.65 kV.

The current triggering method for avalanche transistors primarily relies on base triggering. In the avalanche Marx circuit, the first stage employs base triggering for the avalanche transistor. For subsequent avalanche transistors, the base and emitter are short-circuited. This configuration results in a potential change that generates a pulse exceeding the avalanche breakdown voltage, thereby triggering conduction in the avalanche transistor. Multiple sharpening stages are utilized to produce a fast front edge pulse output. However, the base triggering in the first stage results in a relatively slow conduction speed, typically ranging from tens of nanoseconds to several tens of nanoseconds. This slow response not only leads to passive voltage boosting, which increases the risk of damage to the second-stage avalanche transistor, but also necessitates multi-stage compression to achieve a rapid leading edge. The circuit structure is illustrated in Figure 1a. In the series configuration of avalanche transistors, all but the last one, which is triggered by the base, have their base and emitter terminals shorted and connected to the collector of the subsequent transistor. Once the last transistor triggers conduction, surpassing the breakdown voltage of the other transistors in the series, the entire structure conducts. This triggering mechanism confines the output pulse amplitude to the bias voltage, corresponding to the charging voltage of the energy storage capacitor. However, the presence of internal resistance in the avalanche diode array post-conduction ensures that the final output pulse amplitude will be lower than the bias voltage. The circuit structure is illustrated in Figure 1b. Although the output magnitude can be fine-tuned by adjusting the bias voltage, the range for such adjustments is limited to ensure successful conduction of the avalanche transistor series. Furthermore, reducing the bias voltage can impact the leading edge of the output pulse. These challenges are also present in the avalanche Marx circuit.

To overcome the limitations associated with bias voltage, this paper presents a novel avalanche transistor series structure circuit. The final avalanche transistor employs a configuration that short-circuits the base and emitter. When a bias voltage is applied, a negative pulse is introduced at the short-circuit point to activate the avalanche transistor series structure. By incorporating an additional DC power supply to regulate the amplitude of the negative pulse voltage, the output pulse amplitude can be adjusted accordingly. Additionally, a series test platform involving four avalanche transistors was established to facilitate experimental validation. To achieve a faster leading edge, pF-level capacitors were connected in parallel across the transistor, followed by experimental verification. The designed circuit is capable of generating output pulses with a relatively high slope, exceeding 1 kV/ns, which aligns with the theoretical calculated value for silicon-based avalanche devices. This fast front pulse can serve as a trigger pulse for silicon-based avalanche devices. Additionally, the enhanced circuit is utilized to provide the trigger pulse for silicon-based fast ionization transistors (FID) in test experiments. and the output fast front pulse was employed as the trigger pulse for test experiments involving the silicon-based fast ionization transistor (FID).

2. Design of Avalanche Transistor Series Circuit

The voltage tolerance of a single avalanche collective transistor is relatively low, generally in the range of several hundred volts. Consequently, it is necessary to connect multiple transistors in series to achieve a higher output voltage. The operational principle of the series pulse circuit, which relies on the brief contact between the base and emitter of the avalanche transistor, is illustrated in Figure 2a.

In this configuration, V_CC represents the bias voltage DC power supply for the series structure of the avalanche transistors, V_DC serves as the trigger pulse DC power supply, R₁ functions as the charging resistor, and R_Q1–R_Qn are the voltage equalizing resistors. Additionally, C₀ and C₁ are the respective energy storage capacitors, Q₀ denotes the MOSFET, Q₁–Q_n are the series avalanche transistors, and R_L is the load resistor.

The charging process circuit is illustrated in Figure 2b. In this configuration, the MOSFET remains in a non-conductive state. The DC power supply V_DC charges the energy storage capacitor C₀ via the D₁-C₀-D₂ circuit. Concurrently, the DC power supply V_CC charges capacitor C₁ through the R₁-C₁-R_L circuit, while also providing bias power for the avalanche transistor series structure. However, this arrangement does not suffice to activate the avalanche transistor series structure. The discharge process circuit is depicted in Figure 2c. Here, the MOSFET is triggered to conduct, allowing the energy storage capacitor C₀ to discharge through Q₀. When the voltage across Q₀ is disregarded, the upper potential of capacitor C₀ is clamped to 0, and the lower potential is clamped to −V_DC. Consequently, the voltage across the avalanche transistor series structure becomes V_CC + V_DC, initiating the avalanche conduction of the avalanche transistor series structure. Ignoring the residual voltage of the avalanche transistor series structure, the upper potential of C₁, which corresponds to the collector potential of the first avalanche transistor is rapidly clamped to:

$${\mathrm{V}}_{\mathrm{UP}}=-{\mathrm{V}}_{\mathrm{DC}}$$

(1)

Since the voltage across the capacitor cannot change abruptly, the lower potential of C₁ is rapidly clamped to:

$${\mathrm{V}}_{\mathrm{DOWN}}=-{\mathrm{V}}_{\mathrm{DC}}-{\mathrm{V}}_{\mathrm{CC}}$$

(2)

C₁ discharges through the illustrated circuit, thereby generating a fast falling-edge negative pulse amplitude on the load R_L as follows:

$${\mathrm{V}}_{\mathrm{p}\mathrm{u}\mathrm{l}\mathrm{s}\mathrm{e}}={\mathrm{V}}_{\mathrm{CC}}+{\mathrm{V}}_{\mathrm{DC}}$$

(3)

Due to the internal resistance of the avalanche transistor after conduction, the simplified circuit model after conduction is shown in Figure 3a. The pulse amplitude on the load is as follows:

$${\mathrm{V}}_{\mathrm{out}}={\displaystyle \frac{{\mathrm{R}}_{\mathrm{L}}}{{\mathrm{R}}_{\mathrm{L}}+\mathrm{n}\mathrm{r}}}\left({\mathrm{V}}_{\mathrm{CC}}+{\mathrm{V}}_{\mathrm{DC}}\right)$$

(4)

which is generally valued at 2–3 Ω, and n is the number of series connections of the avalanche transistor.

Under identical conditions regarding the number of avalanche transistors, bias voltage, and load, the simplified circuit model of the base-triggered avalanche transistor series structure after conduction is shown in Figure 3b, and the pulse amplitude on the load is as follows:

$${\mathrm{V}}_{\mathrm{out}}={\displaystyle \frac{{\mathrm{R}}_{\mathrm{L}}}{{\mathrm{R}}_{\mathrm{L}}+\mathrm{n}\mathrm{r}}}{\mathrm{V}}_{\mathrm{CC}}$$

(5)

Principle analysis reveals that, unlike the traditional base-triggered avalanche transistor series circuit, the final avalanche transistor in this configuration employs a short-circuiting method between the base and the emitter. A negative pulse is applied at the short-circuiting point to initiate conduction in the series structure. Because the DC power supply regulating the amplitude of the negative pulse operates independently of the biased DC power supply, this approach introduces an additional adjustable input voltage, V_DC. Consequently, the output pulse can be modulated by varying this supplementary input voltage V_DC while maintaining a larger bias voltage, thereby overcoming the limitations imposed by the bias voltage.

3. Circuit Optimization and Expansion

3.1. Optimized Design of pF-Level Capacitors in Parallel

The avalanche breakdown effect of the avalanche transistor can be harnessed to generate a narrow pulse with a rapid leading edge, thereby achieving a relatively steep slope. However, current experimental evidence indicates that the residual voltage of the avalanche transistor post-conduction is notably high, and both the amplitude and falling edge of the output pulse are influenced by the parasitic parameters present in the circuit loop. To attain a higher slope, this paper proposes connecting pF-level capacitors of identical capacitance in parallel with the avalanche transistor, as illustrated in Figure 4.

During the charging process, the voltage that each pF-level capacitor connected in parallel with the avalanche transistor can attain is as follows:

$${\mathrm{V}}_{\mathrm{CQ}}={\displaystyle \frac{{\mathrm{V}}_{\mathrm{CC}}}{\mathrm{n}}}$$

(6)

Then the charge stored on the parallel capacitor is:

$$\mathrm{Q}={\displaystyle \frac{{\mathrm{V}}_{\mathrm{CC}}}{\mathrm{n}}}{\mathrm{C}}_{\mathrm{p}}$$

(7)

where C_p is the capacitance value of the parallel capacitor.

The speed of conduction in the avalanche transistor primarily depends on the rate at which charge is removed from the collector-emitter (C–E) depletion region. The capacitors C_Q1–C_Qn, connected in parallel with the avalanche transistor, serve as a high-speed charge reservoir during the conduction process. The charge stored in these capacitors discharges rapidly through the low on-resistance created by the avalanche transistor itself. The discharge current is expressed as:

$${\mathrm{I}}_{\mathrm{cp}}(\mathrm{t})\approx {\displaystyle \frac{{\mathrm{V}}_{\mathrm{CC}}}{{\mathrm{n}\mathrm{R}}_{\mathrm{on}}}}\cdot {\mathrm{e}}^{-{\displaystyle \frac{\mathrm{t}}{({\mathrm{R}}_{\mathrm{on}}{\mathrm{C}}_{\mathrm{p}})}}}$$

(8)

where R_on denotes the resistance during the conduction phase of the avalanche transistor. This additional current enhances the extraction of charge from the depletion region within the avalanche transistor, facilitating a quicker transition from the blocked state to the fully conducting state. Consequently, this reduces the conduction time, which is reflected in a decrease in the falling edge of the output pulse.

As the capacitance of the parallel pF-level capacitor increases within a specific range, the acceleration effect on the conduction process becomes more pronounced. However, with further increases in capacitance, another time scale emerges as significant: the discharge time constant. The discharge time constant of a parallel capacitor through the on-resistance of an avalanche transistor is as follows:

$$\mathsf{\tau }={\mathrm{R}}_{\mathrm{on}}\cdot {\mathrm{C}}_{\mathrm{p}}$$

(9)

When C_p is large, the discharge time constant becomes considerable, indicating that the discharge process will prolong and extend the overall conduction time.

3.2. Extended Circuit for Fast Ionization Transistor (FID) Testing

FID is a fast-conducting switch device, capable of achieving conduction times ranging from tens to hundreds of picoseconds. It generates high-voltage pulses characterized by ultrafast pulse fronts, ultra-narrow pulse widths, and ultra-high repetition frequencies. However, the criteria for triggering the FID to conduct are exceedingly stringent. Currently, both domestically and internationally, the fast pulse produced by the step recovery diode is predominantly employed as the trigger pulse, and the associated circuitry remains relatively straightforward.

The avalanche transistor series circuit presented in this paper is capable of generating a narrow pulse with a rapid leading edge, achieving a pulse slope that can exceed 1 kV/ns. This value represents the theoretically calculated trigger pulse slope necessary for the conduction of silicon-based avalanche devices, thereby enabling its application in triggering the conduction of FID.

Based on the designed avalanche transistor series circuit, improvements were made to the circuit, as illustrated in Figure 5. The load of the original circuit was modified to incorporate a series configuration of the load R_L and FID, with a diode D_L connected in parallel across both ends. During the charging phase of the energy storage capacitor C₁, diode D_L effectively short-circuits R_L and FID. Once the avalanche transistor series structure becomes conductive, a rapid front pulse is applied across the FID to initiate its conduction.

4. Result

4.1. Avalanche Transistor Series Test Experiment

To achieve a rapid leading pulse, the avalanche transistor FMMT415 (DIODES, SOT23 package) was chosen for the series test experiment involving four avalanche transistors. The printed circuit board (PCB) utilized for this experiment is depicted in Figure 6. A 10 kΩ surface mount resistor was selected as the charging resistor R₁. The voltage equalizing resistors R_Q1–R_Q4 were chosen as 2.2 MΩ surface mount resistors, while the energy storage capacitor C₀ was selected as a 100 nF surface mount ceramic capacitor. Due to the inherent delay between the application of the trigger pulse and the complete conduction of the avalanche transistor series structure, capacitor C₀ will discharge into the entire circuit. Consequently, a capacitor with a larger capacitance is required. The energy storage capacitor C₁ was selected as a surface mount ceramic capacitor with a capacitance of 100 pF, and the load resistance R_L is set at 50 Ω. The high-voltage test platform constructed for this study is illustrated in Figure 7. The bias voltage V_CC is maintained at 1200 V, while the input voltage V_DC ranges from 200 V to 500 V. The output pulse voltage waveform is presented in Figure 8, and the corresponding output voltage amplitudes are summarized in

Table 1. Output pulse amplitudes of the load under different input voltages.

Input Voltage	Output Pulse Amplitude
200 V	1020 V
300 V	1130 V
400 V	1210 V
500 V	1270 V

. When the input voltage is set to 500 V, the voltage waveform across the avalanche transistor series structure is shown in Figure 9. Based on the circuit principle analysis discussed previously, it is evident that the series structure of the avalanche transistor successfully conducts.

The output waveform indicates that the output pulse amplitude of the series circuit involving four avalanche transistors can be adjusted between 1020 and 1270 V. This finding confirms that the circuit design presented in this paper can achieve an adjustable output pulse amplitude by varying the input pulse voltage, thereby surpassing the bias voltage limit. Additionally, to assess circuit performance, a repetition frequency experiment was conducted. The circuit consistently outputs 1260 V at a frequency of 10 kHz with minimal jitter. The waveform diagram of the repetition frequency experiment is shown in Figure 10. Continuing to increase the repetition rate will cause the overall circuit to overheat and result in random damage to avalanche transistors.

4.2. Optimization Design Experiment of Capacitor in Parallel

The preceding analysis indicates that an increase in the capacitance value of parallel capacitors within a specific range can enhance the conduction speed of the avalanche transistor. To confirm that parallel pF-level capacitors connected across the avalanche transistor can indeed improve its conduction speed and to identify the optimal range of capacitance values, the series experiments was conducted involving four avalanche transistors.

The bias voltage is set at 1200 V, while the input voltage is 500 V. Surface mount ceramic capacitors with capacitance values of 2 pF, 4.7 pF, 10 pF, 15 pF, 20 pF, 33 pF, and 47 pF were connected in parallel across the terminals of avalanche transistors Q₁ to Q₄. The resulting output pulse waveform, particularly the falling edge, is illustrated in Figure 11, while the corresponding pulse amplitude, falling edge characteristics, and slope are summarized in

Table 2. The amplitude, falling edge and slope of the load output pulse when various pF-level capacitors are connected in parallel with the avalanche transistor.

Capacitance Value	Amplitude	Falling Edge	Slope
No paralleled capacitor	1270 V	1.27 ns	1.000 kV/ns
2 pF	1290 V	1.24 ns	1.040 kV/ns
4.7 pF	1310 V	1.20 ns	1.092 kV/ns
10 pF	1314 V	1.10 ns	1.194 kV/ns
15 pF	1320 V	1.00 ns	1.320 kV/ns
20 pF	1315 V	1.11 ns	1.185 kV/ns
33 pF	1308 V	1.30 ns	1.006 kV/ns
47 pF	1292 V	1.58 ns	0.818 kV/ns

.

The experimental results indicate that when the capacitance of the parallel capacitor is less than 15 pF, an increase in capacitance corresponds to a decrease in the falling edge and an increase in the conduction speed of the avalanche transistor series structure. However, as the capacitance continues to rise beyond this threshold, the falling edge begins to increase, indicating that the discharge time constant becomes predominant, resulting in a reduction in conduction speed. Furthermore, with further increases in capacitance, the tail of the output waveform starts to distort. Specifically, when a 15 pF capacitor is connected in parallel with the avalanche transistor, the output pulse amplitude rises from 1270 V to 1320 V, the falling edge decreases from 1.27 ns to 1.00 ns, and the slope increases from 1.00 kV/ns to 1.32 kV/ns, representing a 32% increase.

These experiments demonstrate that the parallel connection of pF-level capacitors across the avalanche transistor enhances conduction speed, with an optimal capacitance value identified. Furthermore, a longer discharge time implies that more energy is dissipated across the on-resistance of the transistor during the conduction period, potentially leading to an increase in junction temperature and adversely affecting the device’s switching characteristics.

4.3. FID Extended Circuit Experiment

To confirm that the output pulse of the designed avalanche transistor series circuit is suitable for triggering the FID, an experimental test with the FID test expansion circuit was conducted. The bias voltage was set at 1200 V, while the input voltage was maintained at 400 V. The resulting output waveform is depicted in Figure 12, with the falling edge illustrated in Figure 13. Due to the delayed avalanche breakdown effect of the FID, a narrow picosecond leading edge pulse was generated, exhibiting a rise time of approximately 320 ps and an amplitude of 965 V across a 50 Ω load.

The experimental results indicate that the rapid front pulse generated by the avalanche transistor series circuit developed in this study can effectively trigger conduction in silicon-based avalanche devices, such as FID. Additionally, these results validate the feasibility of the enhanced FID test circuit derived from the original configuration.

5. Discussion

This paper presents the design of a fast-leading narrow pulse circuit utilizing a series configuration of avalanche collective transistors. The conduction of the avalanche transistor is initiated by applying a negative pulse to the base-emitter short junction. The amplitude of the output pulse can be adjusted by varying the input voltage of the trigger pulse. Additionally, a pF-level capacitor is connected in parallel with the avalanche transistor, which increases the current during the conduction phase. This enhancement accelerates the conduction speed, reduces the falling edge of the output pulse, and significantly increases the slope. This circuit can serve as a test trigger pulse for silicon-based avalanche devices.

This paper was verified through a series test experiment of four avalanche transistors. The experimental results are as follows:

• The bias voltage is set at 1200 V, while the input voltage ranges from 200 V to 500 V. The output pulse amplitude is adjustable between 1020 V and 1270 V.
• With a maintained bias voltage of 1200 V and an input voltage of 500 V, a 15 pF capacitor is connected in parallel. Under these conditions, the falling edge decreases from 1.27 ns to 1.00 ns, the amplitude increases from 1270 V to 1320 V, and the slope rises from 1.00 kV/ns to 1.32 kV/ns, representing a 32% increase.
• Additionally, circuit expansion design is conducted, utilizing the aforementioned fast leading-edge pulse as the test trigger pulse for the 500 V withstand voltage FID. The falling edge of the output pulse measures approximately 320 ps, with an amplitude of 965 V.

Currently, all avalanche transistor series structures and avalanche Marx types utilize base triggering. This paper introduces an innovative method for generating a base-emitter short contact, which overcomes the limitations of bias voltage and enables adjustable pulse amplitude under high bias conditions. The output parameters of the circuit designed in this paper are compared with those of the traditional base triggering as shown in

Table 3. Comparison of pulse output parameters.

First Author	Amplitude	Leading Edge	Repetition Rate	Circuit Structure
Zhou, A.	666 V	3 ns	10 kHz	4 transistors in series
Tan, J.	2500 V	3 ns	10 kHz	22 transistors in series
Li, C.	1015 V	150 ps	10 kHz	14-stage avalanche Marx
Yu, L.	1650 V	230 ps	100 kHz	20-stage avalanche Marx
Zhou, Z.	1320 V	1 ns	10 kHz	4 transistors in series

. Furthermore, this study proposes the parallelled connection of capacitors across the avalanche transistor to enhance conduction speed and presents a novel test circuit for FID.

However, the on-resistance of avalanche transistors, once activated, results in a relatively high residual voltage when the number of avalanche transistors connected in series is increased. This configuration may also lead to saturation issues with the output amplitude. Additionally, while the capacitance value of parallel capacitors can enhance conduction speed within a limited range, further increases may adversely affect both the conduction speed and the amplitude of the output pulse.

After confirming the feasibility of the circuit design, the subsequent task involves employing the avalanche transistor series structure as the basic unit of the avalanche Marx generator to produce the picosecond front high-voltage pulse source and investigating the impact of the first-stage parallelled pF-level capacitor on the output of the multi-stage avalanche Marx.