Coordinated Power Control Strategy for PEDF Systems Based on Consensus Protocol

Abstract

Photovoltaic-storage direct current (DC) flexible (PEDF) systems are susceptible to DC bus voltage disturbances, with the constant power load (CPL) characteristics further exacerbating the risk of system instability. To address these challenges, a collaborative control scheme integrating distributed consensus and demand-side response (DSR) based on a consensus protocol is proposed in this study. A fully distributed control architecture is constructed, wherein the upper layer achieves power coordination through voltage deviation of parallel DC/DC converters and neighborhood interaction, whilst the lower layer dynamically optimizes inter-unit power allocation via the DSR mechanism. Distributed state estimation (DSE) is incorporated to enhance voltage control accuracy. Simulations conducted in the MATLAB (R2022a)/Simulink environment demonstrate that the proposed strategy enables rapid stabilization of bus voltage under load step changes and photovoltaic fluctuation scenarios, with system disturbance rejection capability being effectively enhanced. The effectiveness of the approach in maintaining stable system operation and optimizing power distribution is validated. The results indicate that the voltage deviation of the PEDF system remains below 2% under compound disturbances, with the steady-state error being controlled within 2%. The proposed control strategy, through the integration of the power DSR mechanism, effectively improves the system’s anti-disturbance capability. Compared with conventional droop control methods, which typically result in voltage deviations of 3–5%, the proposed strategy achieves a reduction in voltage deviation of over 50%, demonstrating superior voltage regulation performance.

1. Introduction

The current phase represents a critical period for China to achieve its carbon peaking target, during which renewable energy development has exceeded expectations, presenting unprecedented challenges for power grid planning [1,2,3,4]. The photovoltaic-storage DC flexible (PEDF) system has emerged as a promising solution for efficient integration of photovoltaic generation and energy storage [5]. However, the negative impedance characteristics of constant power loads (CPLs) in DC microgrids are prone to inducing bus voltage oscillations, posing significant stability risks. Furthermore, traditional centralized control approaches suffer from single-point-of-failure risks and poor scalability [6].

Distributed control, achieving coordination through local information exchange, has gradually emerged as a research focus, with consensus algorithm-based strategies demonstrating favorable scalability and robustness [7]. In Reference [8], a distributed battery power equalization method based on superimposed frequency was proposed; however, additional hardware increases system complexity. Reference [9] designed a frequency-domain-based power flow tracking strategy, though computational complexity limits real-time applicability. Reference [10] proposed a flexible voltage control strategy requiring only local information without communication, but convergence speed is consequently slower. References [11,12] achieved power regulation through voltage signals; nevertheless, voltage-based signaling involves trade-offs between sharing accuracy and regulation quality. Reference [13] proposed a DC microgrid scheme capable of stable operation under disturbances, but provided only qualitative descriptions without quantitative metrics. Reference [14] presented a proportional load sharing optimization scheme with fixed parameters that cannot adapt to dynamic conditions. References [15,16] employed consensus algorithms for economic dispatch in microgrid clusters; however, voltage stability under CPL disturbances was not explicitly addressed. Reference [17] transformed power sharing into current sharing to mitigate line resistance effects, though strict proportional power sharing remains unachievable under varying voltages [18].

Recent studies have further advanced DC microgrid control. Reference [19] proposed a CEEMDAN-PE and BiLSTM-based photovoltaic prediction method, whilst References [20,21,22] developed cooperative control for battery storage, partition-based voltage coordination, and multi-stakeholder scheduling, respectively; nevertheless, these approaches either neglected demand-side interactions or were designed for alternating current (AC) systems. Event-triggered mechanisms have emerged as promising solutions for communication efficiency. References [23,24] proposed adaptive event-triggered control for multi-agent systems and DC microgrid clusters, significantly reducing communication burden; however, integration with demand-side response remains unexplored. Cyber-security has also received increasing attention; References [25,26] proposed fault-tolerant control under False Data Injection (FDI) attacks and resilient control for AC/DC microgrids, underscoring the necessity of incorporating security considerations into distributed control frameworks.

The main contributions of this paper are summarized as follows:

• A collaborative control scheme integrating distributed consensus control and demand-side response (DSR) is proposed, achieving fully distributed voltage regulation without central controllers, thereby eliminating single-point-of-failure risks.
• A dynamic weight allocation mechanism considering both topological priority and system stress level is designed, enabling adaptive power distribution based on real-time capabilities and network positions.
• An active damping mechanism for flexible loads is developed to counteract the negative impedance effect of CPLs, effectively enhancing DC bus voltage stability.
• A partial mesh communication topology is adopted and validated, providing faster consensus convergence and higher reliability compared with conventional ring topologies.

Based on the above discussion, a collaborative control method integrating distributed consensus control and DSR is proposed. A voltage-power hierarchical control architecture is constructed, wherein global awareness and dynamic allocation of power deficits are achieved through distributed average estimation at the upper layer, whilst flexible load proportional regulation is introduced at the lower layer to suppress the negative impedance effect of CPLs, thereby realizing fully distributed stable control of DC bus voltage.

2. PEDF System

In traditional power systems comprising fossil fuels and hydropower, the regulation mode predominantly adopts the logic of “generation following load”: when fluctuations occur on the load side, real-time adjustments on the generation side are required to maintain system balance, whilst support is provided by the substantial rotational inertia inherent in the rotor systems of generator units. Photovoltaic (PV) generation, owing to its compatibility with local energy consumption requirements, has gradually become a core component of building-integrated distributed energy systems. However, its output power is susceptible to significant fluctuations caused by weather conditions, including variations in solar irradiance and cloud cover [18].

To fully exploit the utilization potential of PV generation and achieve flexible coordinated operation with building DC microgrids, PEDF distribution systems have emerged as a key technical pathway for addressing this challenge. With a DC power supply architecture at its core, this system primarily employs distributed PV installations and energy storage devices as energy supply carriers, whilst dynamic equilibrium between loads and energy is achieved through flexible load regulation mechanisms. During operation, energy from distributed PV and energy storage systems (ESSs) is prioritized for dispatch. On this basis, flexible control of adjustable loads is implemented through the integration of virtual energy storage resources, ultimately achieving the objectives of low-carbon and flexible electricity consumption [11].

The typical PEDF system topology is illustrated in Figure 1. The system is established upon a common DC bus, to which various distributed power sources and loads are connected in a fully parallel configuration. The system components can be categorized into the source side and the load side. On the source side, the system primarily comprises PV arrays and ESSs. The PV arrays are connected to the bus through dedicated DC/DC converters, whilst the ESSs are interfaced via bidirectional DC/DC converters. This bidirectional design is implemented to support bidirectional energy flow, thereby enabling both charging and discharging functions of the energy storage. On the load side, three typical load types are integrated into the system, namely CPLs, flexible loads (FLs), and alternating current (AC) loads. These loads are connected in parallel to the bus through their respective interface converters, with AC loads being supplied through DC/AC inverters. Particular attention should be directed to the impacts of different load types on the system. CPLs exhibit negative impedance characteristics, which constitute the primary challenge leading to bus instability. FLs represent dispatchable demand-side resources and serve as the key actuating units in the collaborative control strategy proposed in this paper.

3. Partial Mesh Topology

The implementation of distributed collaborative control requires the definition of an information exchange network among controllers, namely the communication topology. In Reference [20], conditions for communication topology among battery units were established, based on which the control law for battery units was designed. Building upon this foundation, the DC microgrid communication topology of the PEDF system illustrated in Figure 2 is adopted in this paper. The dashed lines with bidirectional arrows here indicate that the communication between agents will be fed back to the line for information transmission, while the dashed lines represent the information transmission among various agents. It can be intuitively observed that converters, serving as nodes, enable information exchange between various loads and the DC bus, as well as among the loads themselves.

In this paper, each converter serves as a network node $\upsilon$, with the communication links between them constituting the edge set $\epsilon$, thereby forming a communication graph $\delta =(\upsilon ,\epsilon )$. The structure of this graph is of critical importance for ensuring the effectiveness and reliability of the distributed control framework. To overcome the inherent deficiencies of traditional centralized control, particularly the single-point-of-failure risk in star topologies where central hub failure leads to complete network paralysis, a partial mesh topology is adopted in this paper. This represents a fully peer-to-peer (P2P) network configuration in which no centralized nodes exist, thereby exhibiting a high degree of architectural compatibility with the core principles of fully distributed control.

As presented in

Table 1. Comparison of topological structures.

Characteristics	Ring Topology	Partial Mesh Topology
Communication Delay	Hop-by-hop forwarding; max. N/2 nodes traversed	Multiple paths between nodes; shorter average path length; faster propagation.
Reliability	Link failure can be bypassed; node failure causes ring disruption.	Multiple redundant paths available; single or multiple failures minimally affect connectivity.

, with respect to specific communication performance, the partial mesh topology exhibits superior characteristics compared with the equally decentralized ring topology.

Owing to the availability of more abundant alternative communication paths, information transmission between nodes is no longer constrained to a single ring, resulting in a significant reduction in the average transmission distance. This structural advantage directly enhances the convergence speed of distributed algorithms. For the system, this implies a more agile response to bus voltage fluctuations and timely suppression of the adverse effects induced by CPLs. The selection of this topology effectively balances the two critical objectives of low communication delay and high network robustness. Each converter node is only required to exchange information with its neighbors, and the addition or removal of nodes necessitates only local connection reconfiguration, thereby endowing the system with excellent modular scalability that accommodates the plug-and-play requirements of microgrids. This is fully consistent with the distributed consensus control framework proposed in this paper at the theoretical level, constituting an ideal physical foundation for achieving high-performance and high-reliability distributed control. Therefore, to ensure the decentralization and high reliability of the control framework in both theory and practice, a ring communication topology is adopted in this paper as the basis for research and validation. The two adjacency matrices of this topology are as follows:

$$A=\left[\begin{array}{c}{a}_{ij}\end{array}\right]$$

(1)

$$\begin{array}{c}deg(i)={\displaystyle \sum _{j=1}^n}{a}_{ij}\\ D=diag\left(deg(1),\dots ,deg(6)\right)\end{array}$$

(2)

where $a_{ij}$ represents each node in the PEDF system. In matrix $A$, $deg(i)$ denotes the degree of communication graph node i, namely the number of its directly connected neighbors, and diag denotes the operation of constructing a diagonal matrix from the degree values deg(i). The adjacency matrix $A=\left[\begin{array}{c}{a}_{ij}\end{array}\right]$ is defined such that $a_{ij}$ = 1 if a communication link exists between nodes i and j, and $a_{ij}$ = 0 otherwise.

The 6-node mesh topology based on the PEDF system is illustrated in Figure 3. In the figure, BDC1 (BDC: Bidirectional DC-DC Converter; UDC: Unidirectional DC-DC Converter) represents the PV system node, BDC2 represents the ESS node, UDC1 and UDC2 represent two FL nodes, respectively, UDC3 represents the CPL node, and DC/AC represents the AC load node.

4. Model Construction Based on Consensus Protocol Algorithm

The proposed collaborative control scheme integrates two complementary mechanisms to address the stability challenges posed by CPLs in PEDF systems. Distributed Consensus Control operates as the power coordination layer, enabling system-wide power deficit estimation through neighborhood information exchange without centralized supervision. This mechanism ensures rapid and proportional power allocation among source-side units (PV and ESS) according to their real-time available capacities and topological positions within the communication network. Demand-Side Response (DSR) Mechanism serves as the active damping layer, whereby flexible loads dynamically adjust their power consumption in response to DC bus voltage deviations. Through the injection of positive virtual admittance, the DSR mechanism directly counteracts the destabilizing negative impedance characteristics of CPLs.

The consensus protocol is responsible for steady-state power sharing at the system level, whilst DSR provides transient damping at the load side. The synergistic operation of these two mechanisms achieves comprehensive voltage stability enhancement that neither could accomplish independently.

4.1. Power Balance Modeling of Islanded PEDF Systems

In the DC bus, the dynamic characteristics are represented by the bus capacitance $C_{bus}$. The stability of bus voltage $V_{dc}$ constitutes the foundation for normal operation of the entire system, with power flow in the system governed by Kirchhoff’s laws. Neglecting converter losses, the power balance relationship on the DC bus side can be described by the following equation:

$$\sum _{i=1}^N{p}_i-p_{\mathit{load}}=C_{\mathit{bus}}{V}_{\mathit{dc}}{\displaystyle \frac{{\mathit{dV}}_{\mathit{dc}}}{\mathit{dt}}}$$

(3)

$$p_{\mathit{load}}=p_{\mathit{FL}}+p_{\mathit{CPL}}+p_{\mathit{abc}}$$

(4)

where $p_i$ denotes the i-th distributed generation unit, $p_{pv}$ and $p_{Bat}$ represent the power injected into the bus, and N is the total number of power sources. $p_{load}$ represents the total system load power. The model of CPLs can be expressed as $i_{cpl}={\displaystyle \frac{p_{cpl}}{u_{dc}}}$, which exhibits an equivalent negative impedance of $-{\displaystyle \frac{p_{cpl}}{{(u_{dc})}^2}}$ under small-signal perturbations, constituting the primary factor inducing voltage oscillations.

To facilitate a unified understanding of the subsequent equations, conventions are established for the positive and negative directions of power, the normalization of topology degree, and the direction of voltage error:

$${\delta }_i={\displaystyle \frac{deg(i)}{maxdeg(j)}}\in (0,1]$$

(5)

where ${\delta }_i$ denotes the degree normalization coefficient. For core nodes with the highest number of connections in the network, such as the ESS node BDC2 and the FL node UDC1, this value approaches 1.

The voltage deviation is explicitly defined as $e=V_{ref}-V_{bus}$, where $V_{ref}=750 \mathrm{V}$ is the rated DC bus voltage. This deviation serves as the primary feedback signal for both the PI-based power deficit calculation Equation (9) and the dynamic weight allocation mechanism Equation (13), thereby quantitatively linking bus voltage regulation to distributed power coordination.

In this section, a mathematical model of DC microgrids based on the consensus protocol algorithm is established, drawing upon graph theory of topological structures and distributed control theory. Through local information exchange and neighborhood consensus mechanisms, the algorithm achieves the collaborative control objectives of bus voltage stabilization and rational power distribution.

Under islanded operation mode, the power balance relationship of the DC bus is determined by the energy conservation of the bus capacitance. By differentiating the bus capacitance energy $E_c={\displaystyle \frac{1}{2}}{C}_{bus}{V}_{dc}^2$, the following is obtained:

$$C_{bus}{V}_{dc}{\dot{V}}_{dc}=P_{in}-P_{out}$$

(6)

In PEDF systems, the dynamics of DC bus voltage are determined by the internal power balance of the system. Considering that the system comprises PV, ESS, FLs, CPLs, and AC loads supplied through inverters, the following power balance relationship is established:

$$C_{bus}{V}_{dc}{\dot{V}}_{dc}=\sum _{i\in S_b}{P}_i+P_{PV}-P_{FL}-P_{CPL}-P_{abc}$$

(7)

where $C_{bus}$ denotes the equivalent capacitance of the DC bus; $V_{dc}$ denotes the DC bus voltage; $S_b$ represents the set of units with bidirectional power regulation capability in the system, such as BDC2; $P_i$ denotes the power injected into the bus by the i-th adjustable unit; $P_{PV},P_{FL},P_{CPL}$ represent the actual power of PV, FLs, and CPLs, respectively; and $P_{abc}$ denotes the equivalent power consumption on the DC side of AC loads through the inverter. In cases where only the AC-side load power can be measured, the DC-side equivalent power can be approximately converted through the inverter efficiency as $P_{abc}\approx P_{ac}/{\eta }_{inv}$, where $P_{ac}$ represents the AC active power and ${\eta }_{inv}$ denotes the inverter efficiency.

CPLs maintain a constant power consumption level through their local power control loops, constituting exogenous constraint conditions of the system:

$$p_{CPL}=p_{CPL}^{\ast }$$

(8)

where $p_{CPL}^{\ast }$ denotes the rated power setpoint of the CPL.

To achieve voltage stability control, the bus voltage deviation is required to be transformed into power domain regulation commands, thereby constructing the total power deficit. Based on the power balance relationship in Equation (1), the uncontrollable exogenous power terms are transposed to one side of the equation, with the remaining terms representing the net power deficit that is required to be collaboratively undertaken by controllable units. Subsequently, a proportional-integral (PI) controller is introduced, through which the bus voltage error $e=V_{dc}-V_{ref}$ is mapped to the power regulation quantity. This is then combined with the exogenous power terms to form the total power deficit reference:

$$p_{\mathsf{\Sigma }}^{\ast }(t)=p_{CPL}^{\ast }+p_{abc}-p_{PV}+\left(-k_{p}e-k_i\int edt\right)$$

(9)

where $k_p$ and $k_i$ denote the proportional and integral gains of the outer-loop PI controller, respectively; $p_{\mathsf{\Sigma }}^{\ast }$ represents the net injection power that is required to be collectively provided by controllable units, with positive values indicating additional injection requirements and negative values indicating additional absorption requirements.

$$k_p>0,k_i>0,|p_{\mathsf{\Sigma }}^{\ast }(t)|\le p_{\mathsf{\Sigma }}^{max}$$

(10)

where $p_{\mathsf{\Sigma }}^{max}$ denotes the upper limit of the reference command, which is determined according to the total regulation capacity of controllable units in the system.

4.2. Distributed Consensus Estimation Design for Power Deficit

In a truly fully distributed system, not every node is capable of directly calculating this global value. The total power deficit $p_{\mathsf{\Sigma }}^{\ast }$ is typically computed only by a limited number of core nodes, as information such as AC load power $p_{abc}$ and PV power $p_{PV}$ may only be measured or aggregated by certain nodes. To enable all nodes to operate collaboratively, a unified cognition of the global objective $p_{\mathsf{\Sigma }}^{\ast }$ is required to be formed among them. This constitutes the purpose of distributed consensus estimation. The algorithm comprises a consensus coupling term between neighbors and a deviation correction term for reference nodes, through which network-wide reference diffusion is achieved via local information exchange:

$${\widehat{p}}_i=-\kappa ({\displaystyle {\sum }_{j\in {\mathcal{N}}_i}(p_i-p_j)}+b_i(p_i-p_{\mathsf{\Sigma }}^{\ast })$$

(11)

where ${\widehat{p}}_i$ denotes the local estimate of the total power deficit by node $i$; $\kappa$ represents the consensus convergence rate gain; ${\mathcal{N}}_i$ denotes the neighbor set of node $i$; $b_i\in \{0,1\}$ indicates whether node $i$ has direct access, with $b_i=1$ signifying that node $i$ can directly obtain the reference value $p_{\mathsf{\Sigma }}^{\ast }$, i.e., Equation (4). Through this formulation, the system-level reference from the preceding equation is diffused via local communication to achieve a consensus value $p_{\mathsf{\Sigma }}$. The convergence of the consensus estimation algorithm is contingent upon the following fundamental conditions:

$${\lambda }_2(L)>0,\sum _{i=1}^N{b}_i\ge 1,\kappa \in [{\kappa }_{min},{\kappa }_{max}]$$

(12)

where A denotes the algebraic connectivity of the communication graph Laplacian matrix, with its value being greater than zero guaranteeing the connectivity of the graph; κ min and κ_max represent the engineering selection interval for the gain, which requires balancing convergence speed and noise suppression. The condition λ₂(L) > 0 essentially expresses the necessary and sufficient condition for communication graph connectivity in terms of a computable algebraic quantity. Under the partial mesh topology adopted in this paper, high-degree nodes such as BDC2 and UDC1 enhance the overall connectivity strength, with λ₂(L) typically being increased. This directly improves the convergence speed and robustness of the consensus estimation corresponding to Equation (6), enabling the estimates of each node pair to converge more rapidly towards consensus and to remain stable under disturbances.

Remark: The distributed consensus estimation algorithm proposed in Equation (11) employs periodic communication with a fixed refresh period. While this ensures consistent information exchange, it may result in redundant data transmission during steady-state operation when system states remain relatively unchanged.

Such mechanisms can potentially reduce communication frequency by 40–70% while maintaining comparable control performance, as demonstrated in recent multi-agent system literature [23,24]. However, their integration into the proposed PEDF control framework requires additional considerations including: (1) co-design of triggering thresholds with consensus convergence rate κ; (2) exclusion of Zeno behavior to ensure practical implementability; and (3) stability analysis under combined event-triggered communication and CPL disturbances. These extensions constitute important directions for future research.

4.3. Perception-Based Dynamic Weight Design

In partial mesh communication topologies, different nodes possess distinct network positions and regulation capabilities. To enable nodes of greater importance and capability to undertake increased regulation responsibilities during system disturbances, a dynamic weight function integrating topology priority and system stress level is designed:

$$w_i(e)=\left(w_i^0+k_w|e|\right){\delta }_i$$

(13)

where $w_i^0$ denotes the baseline weight of the node, reflecting its inherent attributes such as capacity and state of charge (SoC); the sensitivity coefficient to voltage deviation is represented; ${\delta }_i$ denotes the degree normalization coefficient, which introduces topology priority into the weight calculation. It should be noted that $w_i^0$ > 0 represents the baseline formed by factors such as capacity and lifespan, whilst $k_w$ ≥ 0 causes nodes with greater capability or higher connectivity to bear increased responsibility when voltage stress intensifies, i.e., nodes with larger δ_i undertake a greater share of the regulation burden (0 < ${\delta }_i$ ≤ 1). Finally, the value of the dynamic weight is required to satisfy ${\displaystyle \sum _{i\in {\mathcal{S}}_b}}{w}_i\left(e\right)>0$.

Following the acquisition of a consensus estimate of the total power deficit, rational distribution among controllable units is required, after which collaborative allocation of source-side power is conducted. The distribution principle dictates that the share undertaken by each unit is proportional to its dynamic weight, and the sum of allocated shares must equal the original deficit:

$$p_i^{ref}={\displaystyle \frac{w_i(e)}{{\mathsf{\Sigma }}_{j\in S_b}{w}_j(e)}}{\widehat{p}}_{\mathsf{\Sigma }}$$

(14)

where $p_i^{ref}$ denotes the power reference command allocated to unit i; ${\widehat{p}}_{\mathsf{\Sigma }}$ represents the estimated value of each node following consensus convergence. The actual power allocation must consider the physical capability constraints of each unit, ensuring that the power allocated to each unit remains within its physical capability range: $p_i^{min}\le p_i^{ref}\le p_i^{max}$, where $p_i^{min}$ and $p_i^{max}$ denote the minimum and maximum output power of unit i, respectively. Following adjustment for physical constraints, the sum of power allocation across all units must still equal the system demand ${\displaystyle \sum _{i\in {\mathcal{S}}_b}}{p}_i^{ref}={\widehat{p}}_{\mathsf{\Sigma }}$, which constitutes a fundamental requirement for power balance. The total demand cannot remain unsatisfied due to the constraints imposed on any individual unit.

4.4. Active Damping Mechanism Design for Flexible Loads

CPLs exhibit negative impedance characteristics in small-signal analysis, which reduces system damping and may induce oscillations. To counteract this adverse effect, FLs are designed to perform power regulation based on bus voltage deviation, equivalently injecting positive admittance into the bus:

$$p_{FL}^{ref}=sat\left(p_{FL}^0+k_f\cdot \left[p_{FL}^{min},p_{FL}^{max}\right]\right)$$

(15)

where $p_{FL}^0$ denotes the baseline operating power of FLs; $k_f$ represents the active damping coefficient, $k_f>0$ represents the active damping coefficient. This behavior is contrary to that of CPLs (which increase current when voltage drops), thus injecting positive damping into the system.; and $\left[p_{FL}^{min},p_{FL}^{max}\right]$ denotes the permissible range for power regulation. To protect user experience and equipment lifespan, constraints are imposed on the regulation of FLs:

$$\left|{\displaystyle \frac{d}{dt}}{p}_{FL}^{ref}\right|\le r_{FL}^{max},\hspace{1em}{\int }_t^{t+T}\left|p_{FL}^{ref}-p_{FL}^0\right|dt\le E_{FL}^{max}$$

(16)

where $r_{FL}^{max}$ denotes the maximum permissible power rate of change; $E_{FL}^{max}$ represents the cumulative deviation energy permitted within the time window T.

4.5. Execution Layer Control Implementation

The power reference generated by the upper-layer consensus algorithm is required to be realized through the three-level control architecture at the converter’s lower layer. This architecture employs a power-current decoupling design, enhancing robustness against bus voltage fluctuations through the current inner loop. Switching signals are ultimately generated by the pulse width modulation (PWM) module, ensuring complete equivalence and plug-and-play capability among all units. To translate the power reference into an executable current loop, the middle layer first converts the power reference into a current reference, which is utilized to enhance system robustness:

$$i_i^{ref}={\displaystyle \frac{p_i^{ref}}{V_{dc}}}$$

(17)

where $i_i^{ref}$ denotes the current reference command of converter i; $p_i^{ref}$ represents the power reference allocated by the upper layer; and $V_{dc}$ denotes the real-time bus voltage.

Within the current loop of each individual unit, the current tracking error is obtained by subtracting the actual inductor current feedback value from the current reference value. The current tracking error is then processed by a discrete PI regulator, which outputs the equivalent inductor voltage command in preparation for the lower-layer PWM:

$$e_i[k]=i_i^{ref}[k]-i_{L,i}[k]$$

(18)

where $i_{L,i}[k]$ denotes the inductor current feedback.

The standard continuous-time PI controller is expressed as:

$$u(t)=K_p\cdot e(t)+K_i\cdot \int e(t)dt$$

(19)

Through the application of the rectangular integration method, this can be transformed into a discrete PI controller, which is formulated as:

$$u[k]=u[k-l]+K_p\cdot (e[k]-e[k-l])+K_i\cdot Ts\cdot e[k]$$

(20)

Substituting the control algorithm proposed in this paper yields:

$$u_i[k]=u_i[k-1]+K_p(e_i[k]-e_i[k-1])+K_i{T}_s{e}_i[k]$$

(21)

where $u_i[k]$ denotes the equivalent inductor voltage command output by the PI controller; $e_i[k]$ represents the current tracking error at the k-th time instant; $K_p$ and $K_i$ denote the inner-loop PI gains; and $T_s$ represents the sampling period. The error quantity requiring correction is calculated through Equation (18), whilst Equation (21) determines the PI controller output value to achieve convergence based on the magnitude of this result. This PI controller provides continuous control quantities for the lower-layer PWM module, realizing the transition from discrete digital control to continuous analog control.

In the current control of converters, if only PI feedback control is employed, fluctuations in bus voltage $V_{dc}$ directly affect the control performance of the inductor current. Therefore, a feedforward compensation mechanism is introduced at this stage to predictively counteract the effects of known disturbances, rather than correcting them through feedback after the disturbances have already affected the output:

$$u_{i,f}[k]=\alpha V_{dc}[k],\alpha \in [0,1]$$

(22)

$$u_{i,out}[k]=u_i[k]+u_{i,f}[k]$$

(23)

where $u_{i,f}[k]$ denotes the feedforward compensation term; $\alpha$ represents the feedforward coefficient; and $u_{i,out}[k]$ denotes the final control quantity. The function of incorporating feedforward compensation is to predictively counteract the effects of bus voltage variations on current control, thereby enhancing the dynamic response performance of the system.

Following processing through the preceding two stages, a continuous control quantity $u_{i,out}[k]$ expressed in voltage dimensions is obtained. However, the actual actuator of power converters is based on PWM switching devices, which necessitates the conversion of continuous control quantities into duty cycle signals. The core function of the PWM module is to establish the mapping relationship between control quantities and the conduction time ratio of switching devices (implemented via MATLAB (R2022a) program code). The calculation method for the duty cycle varies according to different DC/DC converter topologies:

$$D_i[k]=\left\{\begin{array}{l}sat\left({\displaystyle \frac{u_{i,ctl}[k]}{v_{in,i}[k]}},D_{min},D_{max}\right),Buck\\ sat\left(1-{\displaystyle \frac{v_{in,i}-u_{i,ctl}[k]}{v_{dc}}},D_{min},D_{max}\right),Boost\\ sat\left({\displaystyle \frac{u_{i,ctl}[k]}{2V_{dc,bi}}}+{\displaystyle \frac{1}{2}},D_{min},D_{max}\right),Bi-directional\end{array}\right.$$

(24)

where $D_i[k]$ denotes the duty cycle of the i-th converter at the k-th time instant; $v_{in,i}[k]$ represents the input voltage of the i-th converter; $v_{dc}$ denotes the DC bus voltage; and $V_{dc,bi}$ represents the bridge arm voltage of the bidirectional DC/DC converter.

The saturation function, also referred to as the limiting function, is a fundamental tool in control engineering for constraining variable ranges. Its core function is to limit the input value x within the interval $[x_{min},x_{max}]$. In this paper, the saturation function is utilized to embody the practical constraint conditions that must be considered during the transformation from theoretical algorithms to engineering implementation:

$$sat(x,D_{min},D_{max})\left\{\begin{array}{l}{D}_{max},x>D_{max}\\ x,D_{min}\le x\le D_{max}\\ D_{min},x<D_{min}\end{array}\right.$$

(25)

where $D_{min}$ and $D_{max}$ denote the physical constraints on the duty cycle, which are determined by the minimum conduction time, dead time, and limitations inherent to the converter components. For Buck converters, the condition 0 < $D_{min}$ < $D_{max}$ < 1 is satisfied; for Boost converters, $D_{max}\in [0.85,0.9]$ is satisfied to avoid the maximum duty cycle limitation imposed by the effects of right-half-plane zeros; for bidirectional converters, a bipolar PWM strategy is adopted.

In this paper, the implementation of the communication network is of considerable importance. Bandwidth separation is utilized to endow different control layers with significantly different response speeds, thereby avoiding instability caused by inter-layer dynamic coupling. If bandwidth separation is not implemented, when the consensus protocol computes power allocation, the lower-layer current dynamics may not have stabilized, leading to contamination of the consensus estimate p_i by rapid current disturbances. The voltage error e in the weight function $w_i(e)$ would contain high-frequency noise, ultimately resulting in the destruction of convergence properties of the entire distributed algorithm. The dynamic weight $w_i(e)$ in Equation (10) is only effective when the voltage error e represents a low-frequency, meaningful deviation. If e contains high-frequency switching ripple, the weight would fluctuate frequently, rendering the “topology-aware” function meaningless. Therefore, the entire execution layer is required to satisfy both physical constraints and bandwidth separation requirements:

$$\begin{array}{c}0\le D_i[k]\le 1\\ {\omega }_{voltage}\ll {\omega }_{consensus}\ll {\omega }_{current}\end{array}$$

(26)

where ${\omega }_{current}$ denotes the current loop bandwidth; ${\omega }_{consensus}$ represents the consensus algorithm bandwidth; and ${\omega }_{voltage}$ denotes the outer voltage loop bandwidth. The typical bandwidth separation requirement stipulates that adjacent layers should differ by a factor of 5–10 or more, ensuring decoupling between inner and outer loop control and avoiding system instability caused by inter-loop coupling.

Simultaneously, to achieve bandwidth separation, the sampling time of each control layer is required to satisfy hierarchical constraints, ensuring that the fast inner loop appears to complete essentially instantaneously from the perspective of the slow outer loop. The hierarchical constraints on sampling time are as follows:

$$T_{current}\ll T_{consensus}\ll T_{common}$$

(27)

$$\left\{\begin{array}{c}{T}_{current}\in [10,50],\mathsf{\mu }\mathrm{s}\\ T_{consensus}\in [0.5,2],\mathrm{ms}\\ T_{common}\in [2,5],\mathrm{ms}\end{array}\right.$$

(28)

where $T_{current}$ denotes the sampling and control period of the current inner loop, which is utilized for rapid tracking of current references and suppression of high-frequency ripple and CPL disturbances; $T_{consensus}$ represents the execution period of the power outer loop and consensus algorithm, which is utilized for dynamic adjustment of power allocation to accommodate bus voltage variations; and $T_{common}$ denotes the refresh period of inter-node communication data, which synchronizes global information and supports the consistency of distributed consensus. The control flowchart based on the distributed consensus protocol algorithm is illustrated in Figure 4.

5. Results

To validate the effectiveness of the proposed partial mesh topology and distributed consensus algorithm under dynamic operating conditions, a simulation model of the PEDF system is constructed in MATLAB (R2022a)/Simulink in this section. Experiments are conducted for typical operating conditions including PV power step changes and load fluctuations, with analysis of the dynamic response characteristics of system power allocation and bus voltage.

5.1. Simulation Parameters and Operating Condition Design

System parameters: the rated DC bus voltage $V_{\mathrm{ref}}$ = 750 V, the bus capacitance $C_{bus}$ = 1000 μF; the rated PV power is 20 kW, the ESS capacity is 50 kWh with a charging/discharging efficiency of 90%; the total regulation range of FLs UDC1 to UDC3 is 0–10 kW, and the CPL power is 5 kW. Control parameters: the current loop sampling period $T_{current}$ = 50 μs, the consensus algorithm period $T_{consensus}$ = 1 ms, and the communication refresh period $T_{common}$ = 2 ms, which are consistent with the timing design in Equation (27).

Dynamic simulation operating conditions:

At t = 0.3 s, a power deficit of 10 kW is simulated with FL connection: PV power undergoes a step decrease from 20 kW to 10 kW, whilst FL power simultaneously undergoes a step increase of 2.5 kW;

At t = 0.6 s, FL disconnection is simulated: PV power recovers to 20 kW, whilst total load power simultaneously undergoes a step decrease of 2.5 kW.

The parameter settings of the aforementioned PEDF system are presented in

Table 2. PEDF System Parameters.

Parameter	Symbol	Title 3
Rated DC bus voltage	Vref/V	750
Bus capacitance	Cbus/μF	1000
Rated PV power	PPV/kW	20
ESS capacity	EBat/kWh	50
Charging/discharging efficiency	ƞ/%	90
FL power regulation range	PEL/kW	0–10
CPL power	PCPL/kW	5

.

Remark: It should be noted that ideal communication conditions are assumed without packet loss or cyber-attacks, and CPLs are modeled with ideal constant power characteristics. For large-scale systems exceeding 20 nodes, hierarchical control architectures may be required to maintain acceptable consensus convergence time. Extension to different voltage levels or system scales would require parameter re-tuning and additional stability verification.

5.2. Communication Topology Verification

A 6-node partial mesh communication topology is adopted, in which the ESS node BDC2 serves as the anchor node responsible for calculating the global power deficit. The consensus estimator convergence rate κ is set to 5, and the outer-loop voltage PI controller parameters are $K_p$ = 0.5 and $K_i$ = 10.

The dynamic weight distribution of each node under elevated bus voltage scenarios is presented. According to Equation (13), the node weight is composed of three components: the baseline weight, the voltage deviation response term, and the degree normalization coefficient. As illustrated in the figure, BDC2 possesses the highest regulation priority during system disturbances due to its high network degree (δ = 1) and substantial baseline weight.

Considering that closed-loop control is implemented within power conversion devices, the instantaneous power remains constant, which is characterized as exhibiting negative impedance characteristics. However, negative impedance characteristics reduce system stability and may even induce resonance phenomena in the DC bus voltage. When CPLs are present, the equivalent negative impedance reduces the effective damping of the system, potentially violating stability criteria and resulting in voltage oscillations or sustained resonance on the DC bus. Therefore, a comparative analysis of DC bus voltage oscillations with and without FLs is discussed in this paper.

As shown in Figure 5, the active damping mechanism for FLs proposed in this paper effectively suppresses bus voltage oscillations induced by CPL negative impedance through DSR, reducing voltage recovery time by more than 60% and decreasing overshoot by 70%.

The damping ratio enhancement index employed in the simulation is increased from 0.2 to 0.8, satisfying the FL power regulation range specified in Equation (13). The saturation limiting function in Equation (16) ensures compliance with user comfort constraints, thereby achieving dual optimization of grid stability and user experience.

As illustrated in Figure 6, the partial mesh topology demonstrates superior convergence performance compared to ring topology, with consensus estimates converging within 0.05 s. As shown in Figure 7, the anchor node leads all nodes in estimating the power deficit. The convergence speed exhibits a distinct pattern: nodes with higher network degrees demonstrate faster convergence.

At t = 0.3 s, a CPL step disturbance is introduced. The system responds rapidly, with the estimates completing reconvergence within the period from 0.3 to 0.32 s. At this point, the steady-state error of the system is controlled to within 0.1%. This test result validates the performance of the consensus protocol, demonstrating that the protocol not only exhibits rapid response speed but also possesses strong disturbance rejection capability.

5.3. Coordinated Control and Power Verification

The actual operational performance of the system is illustrated in Figure 8. In this scenario, the CPL is subjected to a step increase from 2000 W to 3000 W at t = 0.3 s, representing a step magnitude of 50%, to examine the system’s response capability under large disturbances.

Following the disturbance, the bus voltage drops rapidly from 750 V to 312.36 V. Subsequently, under the combined action of source-side power injection and FL damping, the voltage gradually recovers, entering the ±2% error band after approximately 1.141 s and ultimately stabilizing at 735.33 V. The steady-state error of 1.956% satisfies the engineering voltage quality requirement of ±5%.

During the transient process, the voltage overshoot reaches 30.44%, with a peak value of 978.30 V. This is primarily attributable to the negative resistance characteristics of CPLs and the relatively small bus capacitance (2 mF). The system recovery time of 0.114 s is significantly superior to the 0.2–0.3 s typical of conventional droop control.

Simultaneously, the distributed consensus estimator responds rapidly, with power estimates from all nodes completing network-wide convergence within 0.05 s. The ESS converter BDC2, serving as the primary buffer unit, exhibits a rapid increase in discharge power to approximately 3 kW, effectively compensating for the 1 kW power deficit. The PV converter BDC1 and ESS converter BDC2 adjust their outputs according to dynamic weight coefficients, with nodes of higher connectivity undertaking greater regulation tasks.

Following the conclusion of the dynamic process, the total source-side power precisely matches the total load-side power, with power imbalance converging to zero. The 1 kW power deficit is collaboratively compensated through three components: ESS discharge of approximately 0.65 kW, FL load reduction of approximately 0.3 kW, and PV power increase of approximately 0.05 kW. This validates the effectiveness of the source-load coordinated control strategy.

The simulation results demonstrate that the consensus estimator accurately identifies the power deficit, whilst the PI controller effectively eliminates the steady-state error of the bus voltage. At the power allocation level, the coordination strategy based on the consensus algorithm enables multiple power sources to achieve load balancing, thereby avoiding overloading of any single power source. FLs on the demand side counteract the negative resistance effect of CPLs through active power regulation, enhancing the disturbance rejection capability of the system.

5.4. Simulation Result Analysis

5.4.1. Dynamic Characteristics of Power Allocation

Figure 9 illustrates the power allocation simulation curves of the PEDF system, with the entire simulation process divided into three stages.

Steady-state stage (t < 0.3 s): The PV output power is 20 kW, FL1 consumes 4.9 kW, FL2 is not connected, the AC load consumes 2.6 kW, the ESS BDC2 charges at 7.5 kW, and the CPL maintains 5 kW. The power of each node satisfies the balance relationships in Equations (7) and (9), with the system operating in a stable state.

PV power insufficiency stage (0.3 s < t < 0.6 s): PV output drops abruptly by 10 kW, whereupon the consensus algorithm is immediately activated. To test the regulation capability, the upper limit of ESS BDC2 discharge power is set to 3 kW, and FL2 is connected at t = 0.3 s. Weights are allocated according to node connectivity: ${\delta }_i$ = 0.17 for UDC1 at this point, undertaking 1 kW; ${\delta }_i$ = 0.32 for UDC2, undertaking 2.5 kW; and ${\delta }_i$ = 0.75 for UDC3, undertaking 5 kW. As a high-connectivity node, the ESS responds with priority, with discharge power rising to 2.7 kW. Following FL2 connection, it consumes 2.5 kW. FL1, in accordance with the active damping strategy in Equation (15), reduces its power from 4.9 kW to 1 kW within 0.02 s. CPL power remains unchanged at 5 kW. The simulation results conform to the design expectations of Equations (17)–(25), validating the hierarchical regulation mechanism dominated by ESS with FL assistance.

Compound disturbance stage (t > 0.6 s): Following PV recovery, ESS BDC2 ceases discharging and restores to the 7.5 kW charging state within 0.02 s. Load power is reallocated according to Equation (13): ${\delta }_i$ = 0.75 for UDC1 at this point, undertaking 5 kW; ${\delta }_i$ = 0 for UDC2, undertaking no load; and ${\delta }_i$ = 0.75 for UDC3, undertaking 5 kW. The CPL maintains 5 kW. The system achieves a smooth transition without overshoot, demonstrating the collaborative regulation capability of the distributed consensus algorithm.

5.4.2. Bus Voltage Stability Verification

As illustrated in Figure 10, the black line represents the bus voltage response under the conventional droop control strategy, whilst the red line represents the response results of the control strategy proposed in this paper.

At t = 0.3 s when PV power drops abruptly, the bus voltage under droop control falls to 742 V (deviation of −1.3%), whereas the proposed strategy results in a fall to only 746 V (deviation of −0.52%). Through rapid ESS BDC2 discharge and the convergence characteristics of the consensus algorithm, the voltage recovers to within 750 V ± 0.12% in 0.08 s.

At t = 0.6 s during the compound disturbance, the voltage under droop control rises to 756 V (deviation of +0.8%), whilst the proposed strategy maintains it at approximately 754 V with a deviation of +0.51%. FLs UDC1 and UDC2 increase power absorption through. The obtained results are summarized in

Table 3. Degree Normalization Coefficients for Two Operating Conditions.

Node	Grid Division (t = 0.3 s)	Grid Division (t = 0.6 s)
BDC1 (PV)	0.5	0.3
BDC2 (Bat)	0.75	1
UDC1 (FL1)	0.75	0.17
UDC2 (FL2)	0	0.32
UDC3 (CPL)	0.75	0.75
DC/AC	0.5	0.5

.

The active damping coefficient, enabling voltage restoration to steady state within 0.06 s, with overshoot below the ±5% engineering threshold. This demonstrates that FLs can effectively suppress the negative resistance effect of CPLs.

6. Discussion

The results of this study demonstrate that a collaborative control scheme integrating distributed consensus algorithms with DSR can effectively address voltage stability challenges in PEDF systems. Compared with conventional methods, significant improvements are achieved in both steady-state error (<2%) and recovery time (<0.1 s). In contrast to existing DC microgrid schemes in the literature that provide only qualitative descriptions of stable operation under load fluctuations, specific quantitative performance metrics are presented in this study, thereby establishing benchmarks for subsequent comparative analyses.

At the communication topology level, the simulation results validate the superiority of partial mesh topology over the ring topology commonly employed in conventional distributed control schemes. As predicted by algebraic connectivity analysis, the reduction in average path length and enhancement in redundancy are directly translated into faster consensus convergence (approximately 0.05 s for network-wide agreement). Furthermore, the dynamic weight allocation mechanism proposed herein departs from the fixed-weight paradigm prevalent in earlier research by comprehensively considering both topological priority and system stress levels.

To further validate the effectiveness of the proposed method, a comprehensive comparison with existing control strategies reported in the literature is presented in

Table 4. Performance comparison with existing methods.

Method	Architecture	Voltage Deviation	Recovery Time	CPL Damping	Ref.
Conventional Droop	Decentralized	3–5%	0.2–0.3 s	No	[10,11]
Centralized MPC	Centralized	1–2%	0.1–0.15 s	No	[5,6]
Distributed Consensus	Distributed	2–3%	0.15–0.2 s	No	[12,13]
Adaptive Droop	Decentralized	2–4%	0.15–0.25 s	Partial	[14]
Proposed Method	Fully Distributed	<2%	<0.1 s	Yes

.

As shown in Table 4, the proposed method achieves voltage deviation below 2% and recovery time less than 0.1 s, outperforming conventional droop control by over 50% in both metrics. Compared with centralized approaches, the proposed method achieves comparable voltage regulation performance while eliminating single-point-of-failure risks and maintaining scalability. Most significantly, the integration of the DSR mechanism enables active CPL damping capability, which is absent in most existing distributed control schemes. This unique feature addresses the critical challenge of negative impedance-induced voltage oscillations in DC microgrids with high CPL penetration.

The limitations of this study are acknowledged. The PI controller gains, consensus convergence rate, and active damping coefficients were primarily selected based on engineering experience rather than formal optimization procedures. Additionally, the model assumes ideal communication conditions without packet loss or cyber-attacks. Whilst the 6-node configuration demonstrates proof-of-concept feasibility, further validation on large-scale systems remains necessary.

Remark: This study focuses on DC bus voltage stability and power coordination. For comprehensive power quality assessment, additional indicators such as Total Harmonic Distortion (THD) and voltage harmonics at the DC/AC interface warrant further analysis. Extending the proposed framework to incorporate AC-side power quality optimization represents a valuable direction for future work.

7. Conclusions

This paper proposes a collaborative control scheme integrating distributed consensus control and demand-side response (DSR) based on a consensus protocol for PEDF systems. The partial mesh topology achieves rapid power deficit allocation through dynamic weight design with priority regulation by high-connectivity nodes (BDC2, UDC1).

The key performance metrics of the proposed control strategy are summarized as follows:

(a).

Consensus convergence: Network-wide power deficit estimation converges within 0.05 s, with steady-state error controlled within 0.1%.

(b).

Voltage regulation: Bus voltage deviation remains below 2% under compound disturbances, compared to 3–5% for conventional droop control.

(c).

Dynamic response: Voltage recovery time is less than 0.1 s, representing a 50–70% improvement over conventional methods (0.2–0.3 s).

(d).

Damping enhancement: The FL active damping mechanism increases the system damping ratio from 0.2 to 0.8, reducing voltage overshoot by 70%.

(e).

Power allocation: The distributed consensus algorithm achieves accurate power sharing with allocation errors converging to zero within 0.05 s.

Based on the aforementioned simulation results, it can be concluded that the proposed collaborative control scheme is capable of achieving system stability within 1.141 s when subjected to CPL step disturbances of 50% magnitude, with steady-state error controlled to within 2%. The distributed consensus algorithm successfully realizes decentralized power coordination and allocation, whilst the FL active damping mechanism effectively improves the dynamic response characteristics of the system.

It should be noted that the voltage fluctuation amplitude during transient processes is relatively large, which is primarily attributable to limitations in bus capacitance and the strong nonlinear characteristics inherent to CPLs. Through subsequent parameter optimization—including increasing PI gains, enlarging bus capacitance, adjusting the consensus convergence rate—and hardware improvements such as the introduction of supercapacitor buffer units, the disturbance rejection capability and voltage quality of the system can be further enhanced.

Future Work: This study opens up several avenues for further exploration. The integration of event-triggered communication mechanisms offers a promising approach to reducing bandwidth consumption whilst preserving control performance—a direction well-supported by recent advances in adaptive event-triggered control for multi-agent systems. As demonstrated in relevant literature for DC microgrid clusters, event-triggered average consensus can achieve output-constrained distributed cooperative control with significantly reduced communication overhead. The extension of such mechanisms to the proposed PEDF control framework warrants further investigation.

Of equal importance is the need to address security and robustness under adversarial conditions. As noted in recent fault-tolerant control literature [25], distributed architectures remain inherently susceptible to cybersecurity threats, particularly FDI attacks in which malicious agents corrupt communication data to destabilize the system. Key priori-ties for future research include: (1) adaptive fault-tolerant mechanisms for detecting and compensating sensor/actuator failures; (2) secure consensus protocols robust against stochastic FDI attacks; (3) output-constrained strategies ensuring that bus voltage and power remain within safe limits under attack; (4) hardware-in-the-loop testing and physical prototype deployment to validate practical feasibility under real-world conditions; and (5) comprehensive power quality analysis including THD at the DC/AC inverter interface and other indicators such as voltage flicker and harmonic content.

In summary, the proposed topology and algorithm can effectively address dynamic variations in PV and load conditions, providing a feasible scheme for collaborative control of distributed DC systems. The simulation validates the effectiveness, robustness, and engineering feasibility of the proposed scheme, offering theoretical support and practical guidance for the optimized operation of PEDF building power distribution systems.