High-Throughput Control-Data Acquisition for Multicore MCU-Based Real-Time Control Systems Using Double Buffering over Ethernet

Abstract

For the design, implementation, performance optimization, and predictive maintenance of high-speed real-time control systems with sub-millisecond control periods, the capability to acquire large volumes of high-rate control data in real time is required without interfering with normal control operation that is repeatedly executed in each extremely short control cycle. In this study, we propose a control-data acquisition method for high-speed real-time control systems with sub-millisecond control periods, in which control data are transferred to an external host device via Ethernet in real time. To enable the transmission of high-rate control data without disturbing the real-time control operation, a multicore microcontroller unit (MCU) is adopted, where the control task and the data transmission task are executed on separately assigned central processing unit (CPU) cores. Furthermore, by applying a double-buffering algorithm, continuous Ethernet communication without intermediate waiting time is achieved, resulting in a substantial improvement in transmission throughput. Using a control card based on TI’s multicore MCU TMS320F28388D, which consists of dual digital signal processor cores and one connectivity manager (CM) core, the proposed control-data acquisition method is implemented and an actual experimental environment is constructed. Experimental results show that the double-buffering transmission achieves a maximum throughput of 94.2 Mbps on a 100 Mbps Fast Ethernet link, providing a 38.5% improvement over the single-buffering case and verifying the high performance and efficiency of the proposed data acquisition method.

1. Introduction

The demand for high-speed real-time control systems with sub-millisecond control periods has been increasing in many modern applications, such as ac servo motor drives, precision motion stages, electric vehicle traction inverters, machine tools, and robotics [1,2,3]. In the development stage of such control systems, it is necessary to measure and monitor substantial volumes of control data in real time, which are generated at high frequencies with control cycles on the order of tens of microseconds. Therefore, precise, high-rate measurement and monitoring of these data are indispensable for the design, implementation, and performance tuning of control algorithms [4,5,6].

Once the control systems have been developed and deployed, it is also necessary to acquire large volumes of control data during the field operation stage for fault detection and diagnostic purposes, which likewise requires precise, high-rate measurement and monitoring of control data [7,8,9,10]. However, such real-time and high-rate measurements inevitably result in high-rate generation of large data volumes, which in turn demand a high-speed data acquisition capability in the control systems.

In addition, the adoption of machine learning approaches in control systems has attracted considerable interest in recent years. Machine learning algorithms have demonstrated strong potential for enhancing control performance and increasing overall efficiency [7,8,9]. To harness the power of machine learning, however, a substantial amount of control data must be collected. Such data form the basis for training and refining the algorithms, allowing them to perform informed decision-making and effectively optimize control operations. Moreover, the performance of machine learning algorithms generally improves with more accurate and higher-rate sampling of control data, which further elevates the data acquisition requirements of control systems.

In modern industrial environments, Ethernet-based industrial networks have been widely adopted owing to their high bandwidth, excellent real-time capability, favorable cost–performance characteristics, and rich diagnostic and monitoring functions [11,12,13]. In addition, many recent industrial multicore microcontroller units (MCUs) provide a dedicated communication core to offload Ethernet communication processing and peripheral management from the main control core [14,15].

Motivated by this trend, in this study we develop a control-data acquisition method in which high-rate control data are transmitted in real time over Ethernet to an external host device, where the data are stored and analyzed. The developed method fully exploits the multicore MCU architecture by assigning the high-speed Ethernet-processing task and the short-period control task to separate cores, thereby enabling high-speed real-time transmission of control data without degrading the performance of the high-speed control loop. Furthermore, by employing a double-buffering algorithm for the Ethernet buffer, the proposed method eliminates potential data loss caused by the Ethernet processing speed being lower than the memory-access speed and optimizes the utilization of the control core, the communication core, and the Ethernet interface, thus achieving a near-maximal Ethernet transmission throughput.

The proposed control-data acquisition method is implemented on a control card based on TI’s TMS320F28388D multicore MCU, which integrates two DSP cores and a dedicated communication core and supports 100 Mbps Fast Ethernet. Ethernet transmission experiments to an external PC are carried out for both single- and double-buffering Ethernet-buffer configurations under a 62.5 µs control period executed on one DSP core. In the double-buffering case, a maximum net payload throughput of 94.2 Mbps is achieved; this value does not include protocol overhead, so the gross throughput is even higher and very close to the nominal physical-layer rate of Fast Ethernet. In addition, the throughput in the double-buffering case is increased by 38.5% compared with the single-buffering case. These results validate the effectiveness and superior performance of the proposed control-data acquisition method.

The remainder of this paper is organized as follows. Section 2 reviews related research on data acquisition and double-buffering algorithms. Section 3 explains the basic operating principles of the single- and double-buffering algorithms. Section 4 describes the design of the proposed control-data acquisition methods based on these algorithms. Section 5 presents the experimental setup and results used to verify the operation and performance of the proposed methods. Finally, the concluding remarks are presented in Section 6.

2. Related Works

Published research results on data acquisition systems for high-speed real-time control systems with sub-millisecond control periods is relatively limited, and six studies have addressed this topic [16,17,18,19,20,21]. In [16], a control and data acquisition method for a stellarator experiment was proposed for distributed computer systems over Ethernet. In [17,18,19], data acquisition systems were presented for AC servo motor drives that require high data transmission rates, while in [20,21], data acquisition solutions for more general applications were considered without emphasizing transmission speed.

In [16], an Ethernet-based real-time control-data bus was proposed for a stellarator-type fusion device experiment, where many distributed controllers and diagnostics exchange control-relevant data on a millisecond time scale. Switched Ethernet or a software-token protocol was used to achieve reliable, hard real-time data transport suitable for control and data acquisition on a millisecond time scale, and a total net data rate of 38 Mbps was achieved.

In [17], a data-monitoring method for PWM-based digital motor controllers employing a micro secure digital card (MSDC) was presented, achieving a data rate of 1.53 Mbps while concurrently monitoring ten 16-bit variables at a sampling frequency of 10 kHz. However, further improvement in performance is limited, since the inherent limitation of the MSDC, i.e., its relatively long write time, was not addressed.

In [18], a combined hardware–software data acquisition solution was presented for induction motor control, providing high data throughput of up to several Mbps to satisfy the requirements of artificial-neural-network-based adaptive control. However, the approach relies on an additional extension module to transmit all acquired data to an external computer for storage and processing, resulting in increased cost and space requirements.

In [19], a real-time data acquisition approach was presented for storing high-frequency motor control data in an AC servo motor drive using MSDC storage. The inherent limitation of the MSDC, specifically its long write latency, was alleviated through the application of a double-buffering scheme and by distributing the MSDC write operations across the multicore architecture of the MCU. As a result, the proposed method achieved an MSDC write throughput of approximately 2.44 Mbps.

In [20], a data-logging system employing multiple MSDCs was introduced to store large volumes of data obtained from analog signal measurements over extended durations. The central concept of this system is a round-robin storage scheme using two MSDCs; however, the considered logging rate is limited to 1 Hz, which is significantly lower than the typical 10 kHz control frequency of AC servo motor drives.

In [21], a dual-MCU architecture was proposed to address system freeze issues that arise when a data-logging process on the primary MCU becomes unresponsive due to errors. The approach primarily utilizes a secondary MCU to reset the failed main MCU and resume the interrupted logging operation, while issues related to high-speed data transmission and enhanced data-throughput capability are not considered.

The double-buffering algorithm has been widely applied to enhance data-transmission throughput in image-processing applications [22,23,24,25]. In this work, the same general algorithm is combined with the multicore architecture of an MCU and an Ethernet interface to realize high-speed, real-time data acquisition suitable for high-performance control systems with stringent control-data-rate requirements.

3. Single- and Double-Buffering Algorithms

In this section, we describe the fundamental concepts of single- and double-buffering algorithms and discusses their respective advantages and limitations [19]. In general, data handling in computing systems proceeds as follows: an input device first puts data into a buffer, and after the data have been fully written, the processor retrieves the data from the buffer and performs the required processing. The conventional single-buffering approach employs a single buffer for data handling, and its operation is depicted in the timing diagram shown in Figure 1a. In this diagram, “P₀” and “W₀” represent the input device actions of putting a data packet into Buffer₀ and writing the packet to Buffer₀, respectively; “DR₀” denotes that the data packet is ready for retrieval; and “G₀” and “Pr₀” indicate the processor actions of obtaining the data packet from Buffer₀ and processing it, respectively.

As illustrated in Figure 1a, a single data-processing cycle of the single-buffering algorithm operates as follows: the input device puts data into the buffer, and once the data are fully written and available, the processor retrieves and processes them. Consider a scenario in which the data-generation rate of the input device exceeds the memory-processing capability, causing the write operation to require more time than the data-putting operation. This condition is depicted in Figure 1a, where the putting and writing operations take one and two time units, respectively. Under these circumstances, data packets are lost during every alternate placement operation because no empty buffer space is available to accommodate new data. In addition, processor idle periods occur, as the processor must wait for the completion of the write operation before new data become available. As a result, the single-buffering algorithm experiences both data loss and processor idle time, which significantly degrades processor utilization and overall processing performance.

The major limitations of the single-buffering algorithm can be effectively mitigated through the use of a double-buffering algorithm. Unlike the single-buffering approach, double buffering allows parallel operations, thereby preventing data loss and reducing processor waiting time. The operational principle of the double-buffering algorithm is illustrated in Figure 1b, where “P₀” and “P₁” represent the input device putting operations into Buffer₀ and Buffer₁, respectively. The same notation applies to the “W”, “DR”, “G”, and “Pr” operations, with the subscripts 0 and 1 indicating actions associated with Buffer₀ and Buffer₁, respectively. As shown in Figure 1b, the input device alternates between the two buffers in the double-buffering scheme, which eliminates data loss and substantially decreases processor idle time. As a result, the double-buffering algorithm improves processor utilization without incurring data loss and enhances overall data-processing performance.

4. Data Acquisition Method Design

4.1. Overall Structure and Operation

First, several key terms required to explain the operating principles of real-time control systems are defined as follows. The control cycle denotes a single execution instance of the real-time control algorithm, during which sensing, computation, and actuation are sequentially performed. The control period is the fixed time interval between the start of two consecutive control cycles and determines the execution frequency of the real-time control loop. The control operation refers to the execution of control-related tasks that occur during part or all of a control cycle, including sensing, computation, actuation, and auxiliary processing, depending on the system configuration and implementation. The control data refer to the set of variables generated, processed, or updated within each control cycle, including sensor measurements, estimated states, reference commands, controller outputs, and internal control variables required for real-time control operation.

As the hardware platform for the high-speed real-time control system in which both the control algorithm and the proposed control-data acquisition method are executed, we consider a multicore MCU integrating at least two CPU cores. One core, denoted by CPU1, executes the control algorithm and writes the generated control data to a shared-memory region that is accessible by another core, denoted by the connectivity-manager (CM) core, which performs Ethernet transmission to an external PC. The overall structure of the proposed hardware platform is illustrated in Figure 2.

Even when Ethernet data transmission is supported by a DMA engine as shown in Figure 2, non-negligible software processing is still required for Ethernet-based communication. This includes Ethernet frame construction and parsing, DMA descriptor management, buffer management, interrupt handling, and frame scheduling, which necessitates the use of the dedicated CM core to avoid disturbing the periodic and deterministic execution of the real-time control operation.

To facilitate the subsequent design procedure, we define several design and system parameters. The control period is denoted by $T_{\mathrm{s}}$; the execution time of the control algorithm on CPU1 by $T_{\mathrm{ctrl}}$; and the time required for CPU1 to write the control data by $T_{\mathrm{w}}$. Thus, it holds that $T_{\mathrm{s}}=T_{\mathrm{ctrl}}+T_{\mathrm{w}}$. In addition, the maximum amount of data that can be transmitted over Ethernet during one control period $T_{\mathrm{s}}$ is defined as the maximum payload $P_{max}$. This quantity can be measured in advance for each application system and is treated as a known system parameter. Because the Ethernet-processing throughput is commonly lower than the shared-memory write throughput of CPU1, the size of the control data that CPU1 writes to the shared-memory buffer in each control period must be configured to be less than or equal to $P_{max}$ bytes in order to avoid data loss.

The fundamental operating principle of the proposed control-data acquisition method is summarized as follows. In each control cycle, CPU1 executes the control algorithm during $T_{\mathrm{ctrl}}$ and then writes the generated control data to a shared-memory region accessible by the CM core during $T_{\mathrm{w}}$. This shared memory serves as the Ethernet transmission buffer. After CPU1 completes the write operation, the CM core, synchronized with this completion, reads the stored control data and transmits it over Ethernet to the external PC. The size of the shared memory buffer is assumed to be selected as sufficiently large to store the maximum amount of control data that CPU1 can write to the shared memory buffer during the writing time interval $T_{\mathrm{w}}$. The proposed control-data acquisition method is designed to be independent of specific control-data parameters, such as the physical meaning or numerical values of the control variables.

In this system structure, CPU1 acts as the “data input device” in the buffering algorithms by generating and writing control data into the buffer in every control cycle, as illustrated in Figure 1. The CM core acts as the “data processing device” by reading the buffered control data and transmitting it to the external PC via Ethernet. Synchronization between the completion of the CPU1 write operation and the Ethernet transmission operation of the CM core is achieved using the inter-processor communication (IPC) module provided by the multicore MCU.

The IPC module provides hardware-supported intercore synchronization mechanisms, specifically intercore interrupts combined with shared status flags in shared memory. These mechanisms are used to signal buffer ownership and buffer readiness, thereby ensuring data integrity when accessing the shared memory buffers. However, the proposed control-data acquisition method itself is not tied to a specific synchronization primitive, and the choice of a specific primitive does not affect the fundamental operation or effectiveness of the proposed method, as long as correct buffer ownership and data consistency are maintained.

4.2. Using Single-Buffering Algorithm

In this section, two control-data acquisition methods based on the single-buffering algorithm are developed to illustrate the inherent limitations of single buffering. The timing diagram of the first method is shown in Figure 3. In the first control cycle, CPU1 executes the control algorithm during the initial $T_{\mathrm{ctrl}}$ interval of the control period $T_{\mathrm{s}}$, and then it writes the generated control data to the shared-memory buffer during the remaining $T_{\mathrm{w}}$ interval of the same period. In the second control cycle, CPU1 again executes the control algorithm for $T_{\mathrm{ctrl}}$, while the CM core simultaneously transfers, via Ethernet, the control data stored during the first cycle to the PC. After $T_{\mathrm{ctrl}}$ elapses in the second cycle, CPU1 performs another shared-memory write operation for $T_{\mathrm{w}}$, thereby completing the cycle. All subsequent control cycles repeat this same sequence of operations.

When the operation of the second control cycle is examined in detail, a potential race condition becomes evident. If from the beginning of the second control cycle until the end of the interval $T_{\mathrm{ctrl}}$ the CM core has not yet completed the Ethernet transmission of the control data, CPU1 initiates the shared-memory write operation while the CM core is still reading from the same shared-memory address space. This concurrent write–read access to the same memory region can cause a race condition, resulting in data corruption. To avoid this race condition, the amount of control data stored in each control cycle must be set considerably smaller than $P_{max}$. However, this constraint increases the idle time of both the CM core and the Ethernet interface, reduces their utilization, and consequently prevents the system from achieving the maximum attainable Ethernet transmission rate.

To completely eliminate the race condition, a second control-data acquisition method is designed, and its timing diagram is shown in Figure 4. In this method, the CM core is deliberately configured to transmit only one set of control data via Ethernet over two control cycles. As illustrated in Figure 4, this method results in a 50% loss of control data, and because the CM core and Ethernet interface remain idle for more than half of the operation time, the achievable transmission throughput is limited to 50% of the maximum possible rate. This degraded performance also arises from the inherent limitations of the single-buffering algorithm.

Therefore, when a conventional single-buffering algorithm is employed, race conditions, data loss, and reduced utilization of the CM core and Ethernet interface can occur, ultimately leading to severe degradation of the control-data transmission performance.

4.3. Using Double-Buffering Algorithm

In this section, a third control-data acquisition method is developed that addresses the key limitations of the single-buffering algorithm by adopting a double-buffering scheme. The corresponding timing diagram is presented in Figure 5, in which CPU1 alternately stores the control data generated in consecutive control cycles into Buffer₀ and Buffer₁. Specifically, after completing a write operation to Buffer₀, CPU1 switches the write target to Buffer₁ and issues an IPC event to the CM core. In response, the CM core transmits the control data stored in Buffer₀ to the PC via Ethernet, while CPU1 writes the next set of control data into Buffer₁. After the CM core completes the Ethernet transmission from Buffer₀ to the PC, CPU1 switches the write buffer back to Buffer₀ and again triggers the CM core, which then transmits the control data stored in Buffer₁ to the PC. This sequence of operations is repeated continuously.

Therefore, in the third control-data acquisition method employing the double-buffering algorithm, the CM core is required, in each control cycle, to transmit only the control data generated during a single control period. Accordingly, if the size of the control data that CPU1 writes into the shared memory in each control cycle is configured to be less than or equal to $P_{max}$, race conditions and data loss can be completely avoided. In addition, as illustrated in Figure 5, the idle time of the CM core and Ethernet interface is eliminated, and their utilization is significantly increased, leading to a substantial improvement in control-data transmission throughput. The synchronization between the completion of the CPU1 write operation and the initiation of Ethernet transmission by the CM core is realized through the synchronization mechanism supported by the IPC module.

We conclude this section by emphasizing the differences between the method proposed in this paper and that presented in [19]. Although both studies adopt buffering-based data acquisition architectures, the two works address fundamentally different application domains, system constraints, and technical challenges. The method in [19] focuses on high-speed data logging to a micro SD card, where the primary concerns are storage latency, file system overhead, and write-cycle endurance. In contrast, the present method targets real-time Ethernet-based data transmission, which introduces distinct challenges such as software-based Ethernet communication processing, frame scheduling, network throughput limitations, and synchronization between control execution and communication tasks.

5. Experiment

5.1. Experimental Setup

To verify the correct operation and performance of the proposed control-data acquisition methods for high-speed real-time control systems, we construct an experimental setup shown in Figure 6, in which a TI’s TMDSCNCD28388D control card is connected to a PC via Ethernet. The TMDSCNCD28388D control card is equipped with a TI’s TMS320F28388D multicore MCU integrating two DSP cores and one CM core, and the detailed specifications of the DSP and CM cores are summarized in

Table 1. Specifications of the TMS320F28388D DSP core (CPU1).

Parameter	Value	Unit
Architecture	C28x	-
Frequency	200	MHz
Flash memory	512	kB
CPU1 to CM shared RAM	4	kB
Total RAM	338	kB
Total processing	925	MIPS

and

Table 2. Specifications of the TMS320F28388D CM core.

Parameter	Value	Unit
Architecture	ARM Cortex-M4	-
Frequency	125	MHz
Flash memory	512	kB
CPU1 to CM shared RAM	4	kB
Total RAM	96	kB

, respectively, [14].

The first DSP core is referred to as CPU1. On CPU1, the control algorithm is executed with a control period of $T_{\mathrm{s}}$ = 62.5 µs (16 kHz). In each control period, the control algorithm runs during the initial $T_{\mathrm{ctrl}}$ = 32.5 µs, and during the remaining $T_{\mathrm{w}}$ = 30 µs the control data generated by CPU1 are written to a shared-memory buffer. The CM core then reads the control data stored in the shared-memory buffer by CPU1 and transmits this data to the external PC via Fast Ethernet with a nominal physical-layer data rate of 100 Mbps.

Experiments are conducted on the three control-data acquisition methods described in Section 4. In the first method, corresponding to Figure 3, the single-buffering algorithm is applied. In each control period, after CPU1 completes the write operation to the shared-memory buffer, the CM core reads the stored control data and transmits them to the PC via Ethernet. In this case, as the amount of data stored by CPU1 per control period increases, CPU1 may begin writing new data before the CM core finishes the Ethernet transmission, leading to a race condition in which CPU1’s write operation and the CM core’s read operation occur simultaneously on the same address region of the shared buffer.

In the second method, corresponding to Figure 4, the single-buffering algorithm is also used, but the CM core performs an Ethernet transmission once every two control periods, after CPU1 has finished writing the control data to the shared-memory buffer. In this case, race conditions are prevented because the CM core has a longer time window to complete the transmission; however, the control data generated in every other control period are discarded, resulting in data loss and reduced overall effective throughput.

In the third method, corresponding to Figure 5, the double-buffering algorithm is employed. In each control period, CPU1 alternately writes the control data to two shared-memory buffers, thereby simultaneously preventing race conditions and data loss and enabling the achievement of the maximum attainable transmission throughput.

For each method, 10 min transmission experiments are performed for various Ethernet payload sizes, and the transmission throughput is evaluated only in cases where no race condition occurred. The Ethernet payload size is varied, starting at 300 bytes and increasing in increments of 100 bytes. The maximum payload size $P_{max}$ is defined as the largest Ethernet payload that the CM core can transmit within the control period $T_s$ = 62.5 µs. From preliminary measurements of the CM core and the Ethernet interface used in this study, it is confirmed that up to 736 bytes could be transmitted within one control period; therefore, $P_{max}$ is set to 736 bytes. Therefore, if the Ethernet payload size, that is, the amount of control data stored by CPU1 during one control period, is configured to exceed 736 bytes, data loss would inevitably occur. To avoid such cases, the Ethernet payload size is set to be less than or equal to 736 bytes in all experimental conditions.

5.2. Experimental Results

The measured transmission throughputs for each method and payload size are summarized in

Table 3. Experimental results of the three control-data acquisition methods.

Ethernet Frame Size (bytes)		300	400	500	531	600	700	736
Ethernet throughput (Mbps)	Method 1 (Single-buffering, Figure 3)	38.4	51.2	64.0	68.0	RC	RC	RC
	Method 2 (Single-buffering, Figure 4)	19.2	25.6	32.0	34.0	38.4	44.8	47.1
	Method 3 (Double-buffering, Figure 5)	38.4	51.2	64.0	68.0	76.8	89.6	94.2

RC: race condition.

. For each method, if CPU1’s memory-buffer write operation and the CM core’s memory-buffer read operation occur simultaneously in the same memory address space, a race condition arises. Such cases are treated as errors, and the throughput measurement for that payload size is terminated.

In the first method of Figure 3, the time interval in each control period during which the CM core can safely read data from the shared-memory buffer and perform Ethernet transmission without a race condition is the initial portion of the control period, $T_{\mathrm{ctrl}}$ = 32.5 µs, when CPU1 is executing only the control algorithm and no buffer write is performed. Therefore, the amount of data that can be transmitted to the PC in every control period without data loss is approximately 50% of $P_{max}$ = 736 bytes, which corresponds to about 368 bytes every 62.5 µs and yields a predicted maximum throughput of approximately 47 Mbps.

However, even after CPU1 starts its write operation, the control data stored in the trailing region of the shared-memory buffer remain valid from the previous control period. As a result, the CM core can still transmit the control data stored in this trailing region from the previous control period without race conditions or data corruption for a certain additional time beyond $T_{\mathrm{ctrl}}$ = 32.5 µs. Taking this additional error-free transmission window into account, the actual achievable throughput is expected to exceed 47 Mbps. As shown by the experimental results for the first method in Table 3, a maximum throughput of 68.0 Mbps is achieved, which confirms the validity of this prediction.

In the second method of Figure 4, the CM core transmits up to $P_{max}$ = 736 bytes of control data once every two control periods. This corresponds to transmitting up to 736 bytes every 125 µs, which yields a predicted maximum throughput of approximately 47 Mbps, and the experimental results for the second method in Table 3 are consistent with this prediction. In this method, race conditions are avoided by design, but this is achieved at the cost of discarding 50% of the control-data samples, thereby reducing the effective utilization of the available maximum throughput.

In the third method of Figure 5, the CM core transmits up to $P_{max}$ = 736 bytes of control data in every control period. This corresponds to transmitting up to 736 bytes every 62.5 µs, which yields a predicted maximum throughput of approximately 94 Mbps. The experimental results for the third method in Table 3 confirm that this throughput is practically achieved. Consequently, the third method prevents both race conditions and data loss while maintaining the utilization of the CM core and the Ethernet interface close to their maximum values, thereby achieving the highest transmission throughput among the three methods.

Overall, the experimental results in Table 3 demonstrate the stable operation and effectiveness of the proposed high-rate control-data acquisition method. By applying the double-buffering algorithm, a 38.5% improvement in transmission throughput is obtained compared with the conventional single-buffering case. Furthermore, the maximum transmission throughput of 94.2 Mbps does not include protocol overhead, so the gross throughput is even higher and is very close to the nominal physical-layer rate of Fast Ethernet (100 Mbps). Therefore, these results clearly confirm the superior performance of the proposed high-rate control-data acquisition method.

6. Conclusions

In this paper, we propose a high-rate control-data acquisition method for real-time control systems with sub-millisecond control periods, in which large amounts of control data are transmitted in real time to an external host via Ethernet. By exploiting the multicore MCU architecture, the control and Ethernet-processing tasks are assigned to different cores, enabling high-rate data transfer without disturbing the short-period control loop.

It is shown that in the control-data acquisition methods based on a conventional single-buffering algorithm, race conditions, data loss, and reduced utilization of both the CM core and the Ethernet interface can occur, potentially leading to degradation of transmission-throughput performance. To address these issues, we introduce an Ethernet transmission method based on double buffering that guarantees race-free and lossless operation under an appropriate per-cycle payload constraint while allowing both cores to operate in parallel.

An experimental setup is built using TI’s TMS320F28388D multicore MCU, and various experiments are conducted for the proposed control-data acquisition methods. Experimental results on a 100 Mbps Fast Ethernet link with a 62.5 µs control period demonstrate a net payload throughput of 94.2 Mbps, corresponding to a 38.5% improvement over the single-buffering case and confirming the high performance and effectiveness of the proposed method.