A 1.06 ppm/°C Compact CMOS Voltage Reference

Abstract

This paper presents a low-area, low-temperature coefficient (TC) CMOS voltage reference (CVR) circuit utilizing a compensation technique. Compared to traditional CVR circuits, this design does not rely on compensating the temperature characteristics of the threshold voltage. It lowers current demand, reducing resistor dependency and thus minimizing circuit area. In addition, a curvature compensation circuit is constructed, improving temperature stability. Implemented in 180 μm CMOS the core area of the circuit is 0.0081 mm². Under a 1.8 V supply voltage, post-layout simulations show that the best TC reaches 1.06 ppm/°C over the temperature range of −40 °C to 125 °C, and the line regulation (LR) is 0.36%/V within a supply voltage range of 1.6 V to 2 V.

1. Introduction

Voltage references serve as a core supporting unit in mixed-signal systems such as analog-to-digital converters (ADCs), microcontrollers (MCUs), wearable devices, system-on-chip (SoC), and the Internet of Things (IoT), directly influencing the performance of critical components [1,2,3,4,5,6,7,8]. Currently, mainstream circuit configurations are primarily divided into two categories: bandgap reference circuits and CMOS reference circuits. These two types differ significantly in terms of operating principles, core dependent devices, working conditions, and performance characteristics. Bandgap references rely on bipolar junction transistors (BJTs), enabling high precision and excellent temperature stability to achieve stable output. Thus, they are commonly used in high-precision analog and mixed-signal circuits, and their output voltage is generally insensitive to variations in process and supply voltage [9,10,11,12,13,14]. In contrast, CMOS reference circuits generate voltage references based on the threshold voltage and subthreshold characteristics of CMOS devices through the design of circuit architectures such as current mirrors and operational amplifiers. Bandgap references typically require an operating voltage of at least 1.2 V, making them unsuitable for low-voltage application scenarios; CMOS reference circuits, however, can operate stably at lower supply voltages, which better meets the low-voltage requirements of battery-powered devices. Due to the need for integrating BJT devices, bandgap references have a relatively larger overall circuit area, and the operating current consumption of BJTs is usually higher; CMOS reference circuits are built on devices compatible with standard CMOS processes, featuring a more compact layout and lower controllable power consumption. Bandgap references require process support for BJT integration, imposing stricter requirements on process compatibility; CMOS reference circuits are fully implemented based on standard CMOS processes, which reduces the difficulty of integration with digital logic circuits and makes them more suitable for the integrated design requirements of system-on-chip (SoC) devices.

As electronic devices increasingly demand lower voltage, miniaturization, and reduced power consumption, bandgap references struggle to meet next-generation IC demands due to their high operating voltage, large area, and high power consumption. However, CMOS voltage reference circuits have clear benefits. These circuits work stably at low supply voltages. This helps them match the voltage limits of battery-powered devices. Their compact size also makes them well-suited for wearable devices and IoT nodes [15,16,17,18,19,20,21]. These circuits are easy to manufacture and highly integrable, enabling efficient integration with digital logic circuits and providing solid support for SoC designs.

In recent years, reducing the TC of voltage references circuits has become a major challenge in many research efforts. Refs. [22,23], use advanced higher-order compensation methods to improve the temperature stability of the output voltage; however, due to the complexity of the compensation circuit or structural limitations in the core circuits, the large area limits their application in compact systems. Although some designs adopt compact circuit architectures [24,25], they often suffer from a high TC, making them unsuitable for precision applications. Other works [26,27] demonstrate the temperature range for operation is still not broad enough to satisfy automotive temperature specifications.

To address the issues mentioned above, a low-TC and compact CVR circuit is proposed. It converts voltage into current to reduce the circuit’s dependence on resistor values, thereby saving area. The same current is then reused in the compensation circuit to lower the TC of the reference voltage.

2. Proposed Design

Figure 1 shows the schematic of the proposed CVR circuit. The CVR consists of the following functional circuits: $I_{CTAT}$ current generator, $I_{PTAT}$ current generator, compensation circuit, $V_{REF}$ generation circuit, TC and $V_{OUT}$ trimming circuit.

Figure 2 depicts the conceptual schematic of the compensation process. Within the $V_{REF}$ generation circuit, an $I_{CTAT}$ current (complementary-to-absolute-temperature, CTAT) and an $I_{PTAT}$ current (proportional-to-absolute-temperature, PTAT) are merged via resistors so as to generate first-order CVR. Subsequently, compensation current is introduced into the $V_{REF}$ generation circuit, to reduce nonlinear errors caused by the physical properties of CMOS devices in the first-order CVR.

2.1. $I_{\mathit{CTAT}}$ and $I_{\mathit{PTAT}}$ Current Generators

As shown in Figure 3, M16 belongs to the thick-gate NMOS transistor (3.3 V), while all other MOSFETs employ thin-gate transistors (1.8 V). M17 is diode-connected to match M15, ensuring more accurate current matching between the M1 and M2 branches. M15, M16, and M17 are all operating in the subthreshold region. As reported in [21], within this region, when the drain-source voltage meets $V_{DS}\ge 4V_T$, the MOSFET’s drain current can be described by the following equation:

$$I_{DS}=\mu C_{OX}K(\eta -1)exp[V_T^2({\displaystyle \frac{V_{GS}-V_{TH}}{\eta V_T}})]$$

(1)

where T denotes the absolute temperature, $\mu$ represents the carrier mobility, and $\eta$ stands for the subthreshold slope factor. $V_T$ refers to the thermal voltage, which is defined as $k_{B}T/q$. Meanwhile, q denotes the elementary charge, $C_{\mathrm{ox}}$ represents the gate-oxide capacitance per unit area, and K corresponds to the transistor’s aspect ratio (expressed as $W/L$). $V_{GS}$ denotes the gate-to-source voltage, and $k_B$ is the Boltzmann constant. Below is the correlation between the threshold voltage and temperature:

$$V_{THn}=V_{THn}\left(T_0\right)-k_n(T-T_0)$$

(2)

where $V_{\mathrm{THn}}\left(T_0\right)$ denotes the threshold voltage corresponding to the reference temperature, and $k_t$ represents the temperature coefficient of this threshold voltage. Based on Formulas (1) and (2), under the assumption that ${\eta }_{16}={\eta }_{15}$, the gate–source voltage difference $V_{DS16}$ between transistors M16 and M15 can be deduced.

$$\begin{array}{cc}\hfill V_{DS16}& =V_{GS16}-V_{GS15}\hfill \\ \hfill & =V_{TH16}-V_{TH15}+\eta V_{T}ln{\displaystyle \frac{{\mu }_{15}{C}_{\mathrm{ox}15}{W}_{15}{L}_{16}}{{\mu }_{16}{C}_{\mathrm{ox}16}{W}_{16}{L}_{15}}}\hfill \end{array}$$

(3)

$$V_{TH16}-V_{TH15}=(k_{t15}-k_{t16})T+\left(V_{TH16}\left(T_0\right)-V_{TH15}\left(T_0\right)\right)$$

(4)

The high-gain operational amplifier (OPA1) forces its two input terminals to the same voltage:

$$I_{CTAT}={\displaystyle \frac{V_{DS6}}{R_1}}$$

(5)

Based on Formulas (3)–(5), the first-order derivative of $I_{CTAT}$ with regard to temperature is expressed as

$${\displaystyle \frac{\partial I_{CTAT}}{\partial T}}={\displaystyle \frac{\eta k_B}{q{R}_1}}ln{\displaystyle \frac{{\mu }_{15}{C}_{\mathrm{ox}15}{W}_{15}{L}_{16}}{{\mu }_{16}{C}_{\mathrm{ox}16}{W}_{16}{L}_{15}}}+{\displaystyle \frac{(k_{t15}-k_{t16})}{R_1}}$$

(6)

where W and L correspond to the transistor’s width and channel length, respectively. When the aspect ratio of M16 is larger than that of M15 and appropriately scaled, $\frac{\eta k_B}{q{R}_1}ln\frac{{\mu }_{15}{C}_{\mathrm{ox}15}{W}_{15}{L}_{16}}{{\mu }_{16}{C}_{\mathrm{ox}16}{W}_{16}{L}_{15}}+\frac{(k_{t15}-k_{t16})T}{R_1}<0$ [28], a voltage that decreases with increasing temperature can be obtained.Additionally, the temperature coefficient of $I_{CTAT}$ can be precisely tuned by adjusting the aspect ratios of M15 and M16, as well as the value of resistor $R_1$. For $V_{\mathrm{DS}6}$, its value decreases as temperature increases. To ensure that the condition $V_{\mathrm{DS}6}>4V_T$ is satisfied over the entire operating temperature range, stacked CMOS devices with thin and thick gate oxides are adopted.

Likewise, as illustrated in Figure 4, transistors M18, M19, and M20 are all working in the subthreshold region. The gate–source voltage difference $V_{DS19}$ between transistors M18 and M19 can be deduced as follows:

$$\begin{array}{cc}\hfill V_{DS19}& =V_{GS19}-V_{GS18}\hfill \\ \hfill & =V_{TH19}-V_{TH18}+\eta V_{T}ln{\displaystyle \frac{{\mu }_{18}{C}_{\mathrm{ox}18}{W}_{18}{L}_{19}}{{\mu }_{19}{C}_{\mathrm{ox}19}{W}_{19}{L}_{18}}}\hfill \end{array}$$

(7)

If transistor M18 and M19 belong to the same kinds of transistors, $\frac{\partial V_{\mathrm{th}}}{\partial T}=k_{t19}-k_{t18}=0$ [29]. Through appropriate scaling of the aspect ratio between M19 and M18, the simulation results indicate that $V_{DS19}$ can be maintained $V_{DS19}\ge 4V_T$ across the specified temperature range. $V_{DS19}$ can be expressed by the following formula:

$$V_{DS19}=V_{GS19}-V_{GS18}=\eta V_{T}ln{\displaystyle \frac{{\mu }_{18}{C}_{\mathrm{ox}18}{W}_{18}{L}_{19}}{{\mu }_{19}{C}_{\mathrm{ox}19}{W}_{19}{L}_{18}}}$$

(8)

The high-gain operational amplifier (OPA2) forces its two input terminals to the same voltage:

$$I_{PTAT}={\displaystyle \frac{V_{DS19}}{R_2}}$$

(9)

Based on Formulas (8) and (9), the first-order derivative of $I_{PTAT}$ with regard to temperature is expressed as

$${\displaystyle \frac{\partial I_{PTAT}}{\partial T}}={\displaystyle \frac{\eta k_{\mathrm{B}}}{q{R}_2}}ln{\displaystyle \frac{{\mu }_{18}{C}_{\mathrm{OX}18}{W}_{18}{L}_{19}}{{\mu }_{19}{C}_{\mathrm{OX}19}{W}_{19}{L}_{18}}}$$

(10)

According to Formula (10), when the aspect ratio of M18 is larger than that of M19, $\eta V_{T}ln\frac{{\mu }_{18}{C}_{\mathrm{ox}18}{W}_{18}{L}_{19}}{{\mu }_{19}{C}_{\mathrm{ox}19}{W}_{19}{L}_{18}}>0$, a voltage that increases with increasing temperature can be obtained. Additionally, the temperature coefficient of $I_{PTAT}$ can be precisely tuned by adjusting the aspect ratios of M15 and M16, as well as the value of resistor $R_2$.

In the $V_{REF}$ generator, the $I_{PTAT}$ current from M4 is mirrored proportionally by M9, and the $I_{CTAT}$ current from M2 is similarly mirrored by M14. These two currents are combined and converted through resistors to produce the first-order CVR($V_{REF1})$:

$$I_{REF}={\displaystyle \frac{{(W/L)}_9}{{(W/L)}_4}}{I}_{PTAT}+{\displaystyle \frac{{(W/L)}_{14}}{{(W/L)}_2}}{I}_{CTAT}$$

(11)

$$V_{REF1}=I_{REF}\ast (R_3+R_4)$$

(12)

2.2. Compensation Circuit

The compensation current $I_{COMP}$ is produced by the subtraction circuit in Figure 5. A schematic diagram of the compensation current variation with temperature is shown in Figure 6.

As shown in Figure 5 and Figure 6, the creation principle of $I_{\mathrm{HC}1}$ serves as an example to illustrate that of the compensation current. M10 and M5 mirror currents $I_{\mathrm{CTAT}}$ and $I_{\mathrm{PTAT}}$ in specific proportions, and M22 then mirrors the current in M10 at a specific proportion. When the temperature is below $T_3$, $K_3{I}_{\mathrm{CTAT}}$ is larger than $K_2{I}_{\mathrm{PTAT}}$, so $I_{\mathrm{COMP}}$ remains zero. As the temperature rises above $T_3$, $K_2{I}_{\mathrm{PTAT}}$ exceeds $K_3{I}_{\mathrm{CTAT}}$, such that the current in M29 is $K_2{I}_{\mathrm{PTAT}}-K_3{I}_{\mathrm{CTAT}}$. Then, M30 mirrors the current in M29 at a specific proportion, resulting in $I_{\mathrm{HC}1}=K_1(K_2{I}_{\mathrm{PTAT}}-K_3{I}_{\mathrm{CTAT}})$. Under this condition, $I_{\mathrm{HC}1}$ increases with temperature. Similarly, $I_{\mathrm{LC}1}$ can be generated using the same method. The corresponding formulas are as follows:

$$I_{HC1}=K_1(K_2{I}_{PTAT}-K_3{I}_{CTAT})(T_3<T)$$

(13)

$$I_{LC1}=K_4(K_5{I}_{CTAT}-K_6{I}_{PTAT})(T<T_2)$$

(14)

$$T_2={\displaystyle \frac{K_3{R}_2\left(V_{TH16}\left(T_0\right)-V_{TH15}\left(T_0\right)\right)}{R_1\eta k_B(K_2{R}_{2}lnM-K_3{R}_{2}lnN)-q{K}_3{R}_2(K_{t15}-K_{t16})}}$$

(15)

$$T_3={\displaystyle \frac{K_5{R}_2\left(V_{TH16}\left(T_0\right)-V_{TH15}\left(T_0\right)\right)}{R_1\eta k_B(K_6{R}_{2}lnM-K_5{R}_{2}lnN)-q{K}_5{R}_2(K_{t15}-K_{t16})}}$$

(16)

where $K_1,K_2,K_3,K_4,K_5$, and $K_6$ represent ${\displaystyle \frac{{(W/L)}_{30}}{{(W/L)}_{29}}}$, ${\displaystyle \frac{{(W/L)}_5}{{(W/L)}_4}}$, ${\displaystyle \frac{{(W/L)}_{10}{(W/L)}_{22}}{{(W/L)}_2{(W/L)}_{21}}}$, ${\displaystyle \frac{{(W/L)}_{34}}{{(W/L)}_{33}}}$, ${\displaystyle \frac{{(W/L)}_7}{{(W/L)}_2}}$, and ${\displaystyle \frac{{(W/L)}_{12}{(W/L)}_{26}}{{(W/L)}_4{(W/L)}_{25}}}$, respectively. $M,N$ represent ${\displaystyle \frac{{\mu }_{18}{C}_{\mathrm{OX}18}{W}_{18}{L}_{19}}{{\mu }_{19}{C}_{\mathrm{OX}19}{W}_{19}{L}_{18}}}$, ${\displaystyle \frac{{\mu }_{15}{C}_{\mathrm{OX}15}{W}_{15}{L}_{16}}{{\mu }_{16}{C}_{\mathrm{OX}16}{W}_{16}{L}_{15}}}$, respectively. $I_{HC2}$ and $I_{LC2}$ can also be generated following the similar approach. The formulas are provided below:

$$\begin{array}{cc}\hfill I_{HC2}& =K_7(K_6{I}_{PTAT}-K_9{I}_{CTAT})\hfill \\ \hfill & +K_1(K_2{I}_{PTAT}-K_3{I}_{CTAT})(T_4<T)\hfill \end{array}$$

(17)

$$\begin{array}{cc}\hfill I_{LC2}& =K_{10}(K_{11}{I}_{CTAT}-K_{12}{I}_{PTAT})\hfill \\ \hfill & +K_4(K_5{I}_{CTAT}-K_6{I}_{PTAT})(T<T_1)\hfill \end{array}$$

(18)

where $K_7$, $K_8$, $K_9$, $K_{10}$, $K_{11}$, and $K_{12}$ represent ${\displaystyle \frac{{(W/L)}_{32}}{{(W/L)}_{31}}}$, ${\displaystyle \frac{{(W/L)}_6}{{(W/L)}_4}}$, ${\displaystyle \frac{{(W/L)}_{11}{(W/L)}_{24}}{{(W/L)}_2{(W/L)}_{23}}}$, ${\displaystyle \frac{{(W/L)}_{36}}{{(W/L)}_{35}}}$, ${\displaystyle \frac{{(W/L)}_8}{{(W/L)}_2}}$, and ${\displaystyle \frac{{(W/L)}_{13}{(W/L)}_{28}}{{(W/L)}_4{(W/L)}_{27}}}$, respectively.

2.3. Trimming Circuit

Process variation is an unavoidable key issue in the manufacturing of CMOS integrated circuits, which significantly degrades the core performance of voltage reference circuits. Therefore, the design of the trimming circuit must take compensating for process variation as the core objective. This section elaborates on the types of process variation, their impact mechanisms on circuit performance, and further explains the necessity of the trimming circuit.

Process variation is mainly divided into two categories: global process variation and local process variation, and their degradation paths on the circuit are significantly different. Global process variation primarily includes the overall shift in resistor resistance, global drift of MOS transistor threshold voltage ($V_{\mathrm{th}}$), variation in carrier mobility caused by ion implantation dose deviation, and fluctuation of parasitic resistance/capacitance induced by metal interconnect linewidth variation. Such variations directly act on the core voltage division and biasing modules of the reference circuit, leading to unpredictable shifts in the output reference voltage ($V_{\mathrm{ref}}$). As the core index of the voltage reference, the stability of $V_{\mathrm{ref}}$ directly determines the precision of subsequent modules such as ADCs and operational amplifiers. If the offset exceeds the allowable range, it will directly render the reference circuit unusable. Local process variation is mainly manifested as the $V_{\mathrm{th}}$ mismatch of differential pair MOS transistors, uneven thickness of local oxide capacitance ($C_{\mathrm{ox}}$), deviation of Poly-Si gate thickness, and inconsistency of device dimensions caused by local etching deviation. Such variations damage the symmetry and temperature compensation mechanism of the circuit, severely degrading the TC. Local mismatch can cause significant dispersion in the TC, potentially pushing its value far beyond the strict requirement in high-precision application scenarios. This confirms the destructive impact of local process variation on temperature stability. It should be particularly noted that the degradation effect of process variation requires special attention in the trimming scenario; for circuits without trimming calibration, the $V_{\mathrm{ref}}$ shift and TC degradation will be amplified by subsequent high-precision modules, leading to the performance of the entire system deviating from the design expectations. In summary, to offset the $V_{\mathrm{ref}}$ shift caused by global process variation, compress the TC dispersion induced by local process variation, and ensure the performance stability of the circuit over the entire process corners and operating temperature range, the introduction of a trimming circuit is an indispensable key link in this design.

Figure 7 presents the TC trimming circuit, which uses a 4-bit digital control word to operate switch transistors. The transistors $M_{V1}$ to $M_{V4}$ are sized in binary-weighted ratios. These four bits control the circuit via low-active switches (V0–V3). The default code for the TT process corner is 1000, enabling bidirectional trimming. When a switch is on, it acts as a linear resistor in the deep triode region.

Figure 8 presents the $V_{\mathrm{OUT}}$ trimming circuit. Similarly, for the $V_{\mathrm{OUT}}$ trimming circuit, the switches are transistor-controlled, and the resistances of $R_{\mathrm{T}1}$ to $R_{\mathrm{T}4}$ are also arranged in a binary-weighted configuration. To support bidirectional adjustment, the default digital code for the TT process corner is set to 1000. The $V_{\mathrm{OUT}}$ trimming circuit is used only for output calibration and has minimal impact on the TC of the output $V_{\mathrm{REF}}$.

The trimming system primarily acts on the first-order CVR ($V_{\mathrm{REF}1}$). The trimmed $V_{\mathrm{REF}}$ can be expressed as the formula

$$\begin{array}{cc}\hfill V_{REF}& =[(A+\alpha )I_{PTAT}+B{I}_{CTAT}]·(R_3+R_4+\beta R_{TRIM})\hfill \\ \hfill & -I_{COMP}·R_4\hfill \end{array}$$

(19)

where $A={\displaystyle \frac{{(W/L)}_9}{{(W/L)}_4}}$, $B={\displaystyle \frac{{(W/L)}_{14}}{{(W/L)}_2}}$, $\alpha$ is the trimming coefficient controlled by the TC trimming code, and $\beta$ is the trimming coefficient controlled by the $V_{OUT}$ trimming code.

3. Post-Layout Simulation Results

The next section presents the performance characteristics and post-layout simulation results of the voltage reference circuit in this design, which is fabricated using a commercial 180 nm CMOS process. Figure 9 shows the layout of the proposed CVR circuit, with an effective area of approximately 0.0081 mm².

As shown in Figure 10, the proposed reference circuit exhibits stable performance. At a supply voltage of 1.8 V and without trimming, the temperature coefficient (TC) in the TT corner is measured as 1.06 ppm/°C. Under the same conditions, the SF corner yields a TC of 13.34 ppm/°C, FS 13.51 ppm/°C, FF 17.67 ppm/°C, and SS 19.11 ppm/°C, with these results covering the full operating range of −40 °C to 125 °C.

The trimmed circuit achieves temperature coefficients of 1.06 ppm/°C for the TT corner, 4.94 ppm/°C for SF, 3.42 ppm/°C for FS, 7.46 ppm/°C for FF, and 7.41 ppm/°C for SS, as shown in Figure 11. These results are based on simulations conducted at a supply voltage of 1.8 V across the temperature range from −40 °C to 125 °C. A detailed comparison of the temperature coefficients before and after trimming is provided in

Table 1. TC simulation results before and after trimming under different process corners.

Process Corner	TC Before Trimming (ppm/°C)	TC After Trimming (ppm/°C)
TT	1.06	1.06
FF	17.67	7.46
SS	19.11	7.41
FS	13.51	3.42
SF	13.34	4.94

All data are simulated at 1.8 V supply voltage; temperature range: −40°C to 125°C.

.

The power supply rejection ratio performance of the proposed voltage reference, operating at 1.8 V, is depicted in Figure 12. This simulation was conducted at a temperature of 25 °C across a frequency sweep from 0.1 Hz to 1 GHz. Under these conditions, the PSRR reaches −52.3 dB for the TT corner, −49.6 dB for SS, −54.9 dB for FF, −53.8 dB for SF, and −51.2 dB for FS at a specific frequency of 1 kHz. Meanwhile, the output voltage’s dependence on the supply voltage VDD, which is varied from 0.4 V to 2.4 V, is shown in Figure 13. Within the VDD range of 1.6 V to 2 V, the circuit exhibits a line regulation of 0.36%/V according to simulation results.

To evaluate the robustness of the proposed voltage reference, we simulated the output noise spectral density across typical process corners, including TT, FF, SS, FS, and SF, as shown in Figure 14. The noise remains relatively flat in the low-frequency region, which is crucial for DC and precision applications. At 1 Hz, the measured noise density is 20.4 μV/Hz for the TT corner, 23.2 μV/Hz for FF, 19.1 μV/Hz for SS, 19.6 μV/Hz for FS, and 22.8 μV/Hz for SF. Good consistency is observed across the different process corners.

Monte Carlo simulations were performed to assess the proposed voltage reference circuit, with both process variations and mismatch effects taken into account. As depicted in Figure 15, operating at a supply voltage of 1.8 V without trimming, the temperature coefficient exhibits an average value of 12.62 ppm/°C and a standard deviation of 7.54 ppm/°C. These simulation outcomes demonstrate that the output voltage (VOUT) is largely insensitive to such variations.

Table 2. Performance comparison of this circuit with other circuits.

Specification	[10] JSSC’21	[2] TCAS-II’22	[7] TCAS-II’21	[14] AEU’25	[25] IEICE’25	This Work
Technology (nm)	130	350	45	180	180	180
Supply Voltage (V)	3.3	2	1	3.3	3.3	1.8
Temp. Range (°C)	$-40$–150	$-45$–125	$-40$–125	$-40$–125	$-40$–125	$-40$–125
$V_{\mathrm{ref}}$ (V)	1.16	1.22	0.500	1.13	1.22	1.20
Line Regulation (%)	0.03	0.018	0.15	0.027	0.048	0.36
Avg. TC (ppm/°C)	8.75	12.3	22.4	7.7	7.86	4.86
Power (μW)	396	46	7.56	183.1	151.8	50.4
Active Area (mm2)	0.08	0.16	0.079	0.019	0.01	0.008
PSRR (dB)	−82 @10 Hz	−82.46 @100 Hz	−60 @10 kHz	−85 @100 kHz	−65 @1 kHz	−52.3 @1 kHz
Trimming	NO	YES	NO	YES	NO	YES
Sim or Meas	Meas	Meas	Meas	Sim	Sim	Sim
FoM °C3/(W·mm2)	$1.30\times {10}^{14}$	$3.01\times {10}^{14}$	$1.78\times {10}^{15}$	$1.01\times {10}^{15}$	$2.28\times {10}^{15}$	$1.39\times {10}^{16}$

$FoM={\displaystyle \frac{{(T_{\max }-T_{\min })}^2}{TC\times Power\times Area}}$.

compares the performance of the CVR in this work with other reported voltage references (VRs). For bandgap reference circuits, most core architectures are constructed using 1:8 BJTs as the main structure, and then curvature compensation is performed using the generated $I_{PTAT}$ and $I_{CTAT}$. Using BJTs provides better stability, but it also results in a larger circuit area, and the integration density is not as high as that of pure CMOS reference circuits. For pure CMOS reference circuits, most core architectures compensate for the threshold voltage difference in stacked thin- and thick-gate MOSFETs. To achieve a low TC, strict requirements are imposed on the current magnitude in the circuit, which leads to an extremely large resistor area. Additionally, due to the limitations of the core architecture, it is difficult to implement multi-stage curvature compensation designs, so the TC is usually relatively high. In contrast, this design uses $I_{PTAT}$ and $I_{CTAT}$ generators to convert the threshold voltage difference into current, respectively. This removes the restrictions on current magnitude and reduces the dependence on resistor size. At the same time, by utilizing $I_{PTAT}$ and $I_{CTAT}$, multi-stage curvature compensation can be introduced into the pure CMOS reference circuit to reduce the TC. The results show that the proposed CVR achieves a low TC while maintaining a compact layout. A key reason for this small area is its reduced reliance on threshold voltage and current magnitude. It should be explicitly pointed out that the performance data of the proposed design as well as that of some comparative designs are derived from post-layout simulation results, while the data of the remaining comparative designs are obtained from the taped-out measurement results reported in their respective studies. To ensure the fairness and engineering reference value of this simulation-based comparison, our post-layout simulations have strictly covered typical process corners, the full operating temperature range, and parasitic parameters extracted from the actual layout, striving to maximize the simulation of the behavior of practical chips. However, any simulation, no matter how comprehensive, will inevitably deviate from the final taped-out measurement results. Such deviations mainly stem from various practical non-ideal factors that are difficult to fully reproduce in the simulation environment. The primary purpose of this comparison is to demonstrate the theoretical advantages and improvement potential of the novel circuit architecture, rather than to claim absolute, experimentally verified performance superiority over other designs.

4. Conclusions

This paper proposes a compact CMOS voltage reference with a low-temperature coefficient. To address the dual requirements of miniaturization and high stability for precision integrated circuits, this design is implemented based on a 180 nm commercial process. Unlike traditional CMOS reference architectures, this approach does not directly utilize the threshold voltage difference generated by CMOS devices with stacked thin and thick gate oxides for compensation, but rather converts these two types of threshold voltage differences into proportional-to-absolute-temperature (PTAT) current and complementary-to-absolute-temperature (CTAT) current, respectively, and then reuses these two currents for first-order compensation and curvature compensation. This method significantly reduces the circuit’s reliance on resistor dimensions, thereby enabling the use of smaller resistors and effectively minimizing silicon area occupancy. The proposed scheme integrates a trimming circuit to suppress process variations. Post-layout simulation results verify its performance; powered by a 1.8 V supply and operating from −40 °C to 125 °C, the circuit outputs a stable reference voltage of 1.20 V. After trimming, its average temperature coefficient reaches 4.86 ppm/°C. This represents a 36.9% improvement compared to the 7.7 ppm/°C reported in the prior 180 nm scheme of [14], and is 38.2% lower than the 7.86 ppm/°C achieved by another same-node scheme in [25]. Even compared to the 45 nm process scheme in [7], which reported 22.4 ppm/°C, the proposed design exhibits a significant advantage in temperature stability. The core circuit occupies an effective area of only 0.008 mm². Among comparable schemes at the same process node, this area is 57.9% smaller than the 0.019 mm² area reported in [14] and 20% smaller than the 0.01 mm² area of [25]. Furthermore, its power supply rejection ratio reaches −52.3 dB at 1 kHz, which is sufficient to meet the low-frequency noise suppression requirements of most precision applications. Implemented based on the mature 180 nm process, this design successfully balances the performance of area and temperature coefficient, and is suitable for cost- and size-sensitive application scenarios such as portable medical sensors and IoT nodes.