Integrated Analytical Design of Boost DC–DC Converters and Cascade Current-Mode Control Using Integer- and Fractional-Order Lead–Lag Compensators

Abstract

This paper presents an integrated specification-driven analytical methodology for the design and practical implementation of cascade-controlled Boost DC–DC converters using integer-order and fractional-order lead–lag compensators. Unlike empirical tuning and optimization-based approaches, the proposed framework derives the controller parameters analytically from prescribed transient- and steady-state-performance requirements and, for the fractional-order lead–lag (FO–LL) controller, explicitly incorporates the control-effort level as an additional design specification. The methodology integrates converter sizing, averaged small-signal modeling, controller synthesis, rational approximation of fractional-order dynamics, electronic realization, and software-assisted verification within a reproducible workflow implemented in MATLAB, Simulink, and Simscape. The methodology is first evaluated using a numerical assessment case that examines sensitivity to the fractional approximation order, operation away from the nominal point, converter-parameter variations, controller-component tolerances, and load disturbances. Practical feasibility is then demonstrated using a separate experimental implementation case based on a second Boost converter with a hybrid IO–LL/FO–LL cascade configuration, evaluated through three validation levels—block-level simulation, switching circuit-level simulation, and experimental evaluation. The circuit-level and experimental evaluations exhibit consistent transient behavior under their respective test conditions, with representative overshoots of 5.02% and 4.2%, respectively, while the experimental prototype maintains a steady-state error of approximately 1% and achieves approximately 91% conversion efficiency. Overall, the results demonstrate that the proposed methodology provides a systematic and reproducible path from performance specifications to practical controller realization while retaining stable operation and implementation-oriented control effort under the evaluated modeling, operating, and hardware variations.

1. Introduction

The increasing use of renewable-energy systems, electric vehicles, battery-management systems, aerospace applications, and DC microgrids has intensified the demand for efficient and reliable DC–DC power converters. Depending on the required voltage-conversion ratio, these converters can be implemented using Buck, Boost, Buck–Boost, Cuk, Zeta, and Sepic topologies [1,2,3]. Among them, the Boost converter is particularly attractive when the required output voltage exceeds the available input voltage, as occurs in photovoltaic systems, fuel cells, battery-powered systems, DC microgrids, and electric transportation. Boost converters are also employed as PFC stages in wireless electric-vehicle charging systems, where power losses and conversion efficiency can have important thermal implications [4].

A DC–DC converter comprises passive energy-storage elements, semiconductor switching devices, and a feedback-control system [1,2]. Although a single voltage loop can be used for output regulation, high-performance applications frequently employ cascade architectures consisting of a fast inner current loop and a slower outer voltage loop. Such voltage–current cascade structures have also been experimentally implemented in Boost-derived converters to maintain output-voltage regulation under load variations [5]. This structure improves current regulation, output-voltage tracking, and disturbance rejection. Nevertheless, the integrated design of the power stage and its control system remains challenging because DC–DC converters are nonlinear switched systems subject to operating-point variations, parameter uncertainties, parasitic effects, and disturbances [1,2,3]. Consequently, the design must simultaneously consider transient performance, steady-state accuracy, robustness, control effort, and practical implementation constraints.

A wide variety of control strategies have been proposed for DC–DC converters, including PID controllers, frequency-domain compensators, sliding-mode control, active disturbance rejection control, and model predictive control [6,7,8,9,10]. PID controllers remain attractive because of their simplicity and ease of implementation [8], whereas phase lead–lag, PI–Lead, and Type-III compensators provide frequency-domain formulations that relate stability margins and crossover frequencies to controller parameters [7,11,12]. Other approaches, including sliding-mode control, active disturbance rejection control, and model predictive control, have also been applied to DC–DC converters to improve robustness and disturbance rejection [9,10,13]. These approaches involve different design elements, such as sliding surfaces, disturbance observers, prediction models, or optimization procedures, depending on the control strategy.

Fractional-order control extends conventional differentiation and integration operators to noninteger orders, providing additional degrees of freedom for shaping transient response, robustness, and disturbance rejection [14,15,16]. Its application to renewable-energy systems and power converters has consequently received increasing attention, including experimental and hardware-in-the-loop implementations [17,18,19]. Recent approaches have also combined fractional-order control with operating-point-dependent tuning and metaheuristic optimization. For example, Muñoz Hernandez et al. [20] applied a gain-scheduled FO-PID controller to a quadratic Buck converter, whereas Ghamari et al. [19] employed the Snake Optimization algorithm to tune an FOPID controller for a Buck–Boost converter. Nevertheless, controller synthesis and practical realization remain important challenges.

Table 1. Comparison of representative methodologies reported for the control of DC–DC converters.

Ref./Year	Converter	Controller	Design Approach	Cascade	Practical Realization	Validation
[21] (2003)	Buck	FO-BBC	Analytical	No	Digital	Experimental
[22] (2006)	Buck	FO-BBC, FO-SMC	Analytical	No	Digital	Experimental
[23] (2012)	Boost	FO-PI	Frequency-domain tuning	Yes	–	Simulation
[7] (2015)	Buck	Phase-lead	Analytical, frequency-domain	Yes	–	Simulation
[8] (2016)	Boost	PID	Empirical tuning	No	–	Simulation
[3] (2016)	Buck	FO-TSMC	Analytical, Lyapunov-based	No	–	Simulation
[24] (2018)	Buck	VMC	Modeling-oriented	No	–	Experimental
[13] (2018)	Boost	AFSMC	Simulation-based tuning	No	–	Simulation
[25] (2019)	Buck	FRSMC	Sliding-mode design	No	–	Simulation
[26] (2019)	Boost	Digital FO-PID	Partially analytical + numerical search	No	Digital	Experimental
[5] (2024)	AC–DC Boost PFC	PI	Cascade feedback control	Yes	–	Control: simulation; converter: experimental
[19] (2025)	Buck–Boost	FO-PID	Snake Optimization	No	Digital	Hardware-in-the-loop
[9] (2025)	Buck	FO-LADRC	Observer-based tuning	No	–	Experimental
[11] (2025)	Boost	PI-Lead	Partially analytical, frequency-domain	No	–	Simulation
[10] (2025)	Boost	FO-MPC	Optimization-based	No	–	Experimental
[27] (2025)	Boost	FO-PID	Partially analytical + optimization	No	–	Experimental
[20] (2025)	Quadratic Buck	Gain-scheduled FO-PID	Numerical tuning + gain scheduling	No	–	Simulation
[12] (2026)	Boost	Integer Type-III	Analytical, frequency-domain	No	Analog	Simulation
[28] (2026)	Buck	PID/FO-PID	Heuristic tuning	No	–	Simulation
[29] (2026)	Interleaved DC–DC	FO-PID, SMC, MRAC	Optimization-based	No	–	Simulation
This work (2026)	Boost	IO-LL/FO-LL	Analytical	Yes	Analog	Simulation + experimental (hybrid IO–LL/FO–LL)

summarizes representative methodologies reported for the control of DC–DC converters. The selected works include classical and fractional-order controllers, analytical and optimization-based design procedures, single-loop and cascade architectures, and simulation and experimental validation. The comparison is intended to identify how these characteristics have been combined in previous studies and to place the proposed methodology within this context.

Table 1 shows that analytical, fractional-order, cascade, and experimentally validated control strategies have been reported for DC–DC converters. However, these features are generally addressed from different perspectives rather than within a unified design framework. Analytical frequency-domain approaches derive controller parameters through explicit design relationships [7,11,12], whereas several fractional-order approaches rely on numerical search, optimization, operating-point-dependent gain scheduling, or additional tuning procedures [10,20,26,27,29]. Experimental realizations have also demonstrated the practical feasibility of different control strategies.

Nevertheless, comparatively limited attention has been devoted to integrated analytical frameworks that jointly address power-stage sizing, cascade-controller synthesis, fractional-order design, and practical realization. This observation defines the research gap addressed in this work: the need for a systematic methodology that connects the electrical specifications of the Boost converter with the synthesis and implementation of its cascade control system through a unified analytical design procedure.

To address this gap, this paper proposes an integrated methodology in which the Boost converter is first sized from its electrical specifications and the inner current and outer voltage controllers are subsequently synthesized from prescribed performance requirements. The controller synthesis builds on the analytical integer-order lead–lag design of Wang et al. [30] and its fractional-order extension proposed by Tavazoei et al. [31], which are incorporated here into a unified cascade-design framework. The performance requirements are mapped into frequency-domain quantities and then into controller parameters through explicit analytical relationships, avoiding optimization-based or trial-and-error tuning. In the fractional-order case, the additional degree of freedom is used to incorporate a prescribed initial control signal into the synthesis. The resulting controllers are finally translated into practical analog realizations, completing the design path from converter specifications to controller implementation.

The main contributions of this work can be summarized as follows:

• An integrated analytical methodology for the design of the Boost power stage and its cascade control system from prescribed electrical and performance specifications.
• Integration of integer-order and fractional-order phase lead–lag analytical design procedures into the synthesis of the inner current and outer voltage loops, avoiding optimization-based, heuristic, or trial-and-error controller tuning. In the fractional-order case, the additional degree of freedom is exploited to impose a constraint on the initial control effort.
• A complete engineering workflow connecting converter sizing and controller synthesis with software automation, operational-amplifier realization, numerical and circuit-level simulation, and experimental validation of the hybrid IO–LL/FO–LL cascade configuration.

The remainder of this paper is organized as follows. Section 2 presents the theoretical background. Section 3 develops the proposed integrated analytical design methodology, including the electronic realization and software implementation. Section 4 presents the numerical simulation and robustness analyses. Section 5 presents the circuit-level and experimental validation. Section 6 discusses the main findings, their implications, and the scope and potential extension of the proposed methodology. Finally, Section 7 summarizes the main conclusions.

2. Theoretical Background

2.1. Fractional Calculus Fundamentals

Fractional calculus extends conventional integer-order calculus by allowing differentiation and integration operations of arbitrary real order. The fractional-order operator is denoted by ${}_b\mathcal{D}_t^q$, where b and t represent the operation limits and $q\in \mathbb{R}$ denotes the fractional order. For $q>0$, the Riemann–Liouville definition is given by [16,32]       

$${}_b\mathcal{D}_t^{q}f\left(t\right)={\displaystyle \frac{1}{\Gamma (m-q)}}{\left({\displaystyle \frac{d}{dt}}\right)}^m{\int }_b^t{\displaystyle \frac{f\left(\tau \right)}{{(t-\tau )}^{q-m+1}}}d\tau ,$$

(1)

where $m-1<q<m$, $m\in \mathbb{N}$, and $\Gamma (·)$ is the Gamma function. For $q>0$, $q<0$, and $q=0$, the fractional operator represents fractional differentiation, fractional integration, and the identity operator, respectively. Under zero initial conditions, its Laplace transform can be expressed as [32]

$$\mathcal{L}\left\{{}_b\mathcal{D}_t^{q}f\left(t\right)\right\}=s^{q}F\left(s\right),$$

(2)

where $F\left(s\right)=\mathcal{L}\left\{f\right(t\left)\right\}$ and s is the Laplace variable. Evaluating the fractional power on the imaginary axis, $s=j\omega$, gives

$${\left(j\omega \right)}^q={\omega }^q\left[\cos \left({\displaystyle \frac{q\pi }{2}}\right)+j\sin \left({\displaystyle \frac{q\pi }{2}}\right)\right].$$

(3)

Fractional differential equations can therefore be represented in the Laplace domain using transfer functions containing noninteger powers of s. Considering $x\left(t\right)$ and $y\left(t\right)$ as the input and output signals, respectively, a general fractional-order transfer function can be expressed as [33]

$$H\left(s\right)={\displaystyle \frac{Y\left(s\right)}{X\left(s\right)}}={\displaystyle \frac{b_m{s}^{q_m}+b_{m-1}{s}^{q_{m-1}}+\cdots +b_0{s}^{q_0}}{a_n{s}^{r_n}+a_{n-1}{s}^{r_{n-1}}+\cdots +a_0{s}^{r_0}}},$$

(4)

where $q_k,r_k\in \mathbb{R}$, $X\left(s\right)=\mathcal{L}\left\{x\right(t\left)\right\}$, and $Y\left(s\right)=\mathcal{L}\left\{y\right(t\left)\right\}$. This representation enables fractional-order systems to be analyzed and designed in the frequency domain using tools analogous to those employed for integer-order systems.

For practical implementation, fractional-order operators are commonly represented by rational integer-order approximations. Several approximation methods have been proposed, including Newton, Muir, Oustaloup, Matsuda, and Continued Fraction Expansion (CFE) [34,35]. The CFE method is adopted in this work because it provides low-order rational approximations suitable for both numerical analysis and circuit realization. For $q\in (0,1)$, the first- and third-order CFE approximations of $s^q$ considered in this work are given by [34]

$$\begin{array}{ccc}\hfill s^q& \approx & {\displaystyle \frac{A_{1}s+1}{s+A_1}},\hfill \end{array}$$

(5)

$$\begin{array}{ccc}\hfill s^q& \approx & {\displaystyle \frac{C_1{s}^3+C_2{s}^2+C_{3}s+C_4}{C_4{s}^3+C_3{s}^2+C_{2}s+C_1}},\hfill \end{array}$$

(6)

where

$$\begin{array}{ccc}\hfill A_1& =& {\displaystyle \frac{1+q}{1-q}},\hfill \end{array}$$

(7)

$$\begin{array}{ccc}\hfill C_1& =& q^3+6q^2+11q+6,\hfill \end{array}$$

(8)

$$\begin{array}{ccc}\hfill C_2& =& -3q^3-6q^2+27q+54,\hfill \end{array}$$

(9)

$$\begin{array}{ccc}\hfill C_3& =& 3q^3-6q^2-27q+54,\hfill \end{array}$$

(10)

$$\begin{array}{ccc}\hfill C_4& =& -q^3+6q^2-11q+6.\hfill \end{array}$$

(11)

For fractional orders $1<q<2$, the operator is decomposed as $s^q=s{s}^{\tilde{q}}$, with $\tilde{q}=q-1\in (0,1)$; therefore, the CFE expressions above are applied to $s^{\tilde{q}}$, with their coefficients evaluated using $\tilde{q}$ in place of q.

2.2. Boost Converter Model

The proposed design methodology is based on the averaged small-signal model of the Boost DC–DC converter shown in Figure 1a. The converter increases the nominal input voltage $V_{in}$ to an output voltage $V_o$ by adjusting the steady-state duty cycle D. Under ideal steady-state conditions, the voltage-conversion ratio is given by [36]

$${\displaystyle \frac{V_o}{V_{in}}}={\displaystyle \frac{1}{1-D}}.$$

(12)

The energy-storage variables of the converter are the inductor current and the output-capacitor voltage. For the averaged small-signal model, $i_L\left(s\right)$ and $V_o\left(s\right)$ denote the inductor-current and output-voltage variations, respectively, while $d\left(s\right)$ represents the duty-cycle variation. Input-voltage variations around the nominal value $V_{in}$ are represented by the disturbance $V_g\left(s\right)$. Thus, $V_g\left(s\right)$ is not an independent physical input, but represents perturbations of the converter input voltage about its nominal operating point. The transfer functions required for the cascade-control design are given by [23]

$$\begin{array}{ccc}\hfill G_{id}\left(s\right)& =& {\displaystyle \frac{i_L\left(s\right)}{d\left(s\right)}}={\displaystyle \frac{{\displaystyle V_{o}Cs+\frac{2V_o}{R}}}{{\displaystyle LC{s}^2+\frac{L}{R}s+{(1-D)}^2}}}\hfill \end{array}$$

(13)

$$\begin{array}{ccc}\hfill G_{vovg}\left(s\right)& =& {\displaystyle \frac{V_o\left(s\right)}{V_g\left(s\right)}}={\displaystyle \frac{1-D}{{\displaystyle LC{s}^2+\frac{L}{R}s+{(1-D)}^2}}}\hfill \end{array}$$

(14)

$$\begin{array}{ccc}\hfill G_{iLvg}\left(s\right)& =& {\displaystyle \frac{i_L\left(s\right)}{V_g\left(s\right)}}={\displaystyle \frac{{\displaystyle Cs+\frac{1}{R}}}{{\displaystyle LC{s}^2+\frac{L}{R}s+{(1-D)}^2}}}\hfill \end{array}$$

(15)

$$\begin{array}{ccc}\hfill G_{voiL}\left(s\right)& =& {\displaystyle \frac{V_o\left(s\right)}{i_L\left(s\right)}}={\displaystyle \frac{R}{RCs+1}}\hfill \end{array}$$

(16)

where $V_o$ and D denote the steady-state output voltage and duty cycle, respectively. The transfer function $G_{voiL}\left(s\right)$ is obtained by assuming that the inner control loop regulates the inductor current, allowing the circuitry upstream of the output capacitor to be represented by the equivalent current source shown in Figure 1b.

The small-signal model in (13)–(16) assumes ideal converter components and operation in continuous-conduction mode (CCM); therefore, semiconductor losses and parasitic elements are neglected in the control-oriented dynamic model. To maintain CCM and restrict the output-voltage ripple to a prescribed value $\Delta V_o$, the inductance and capacitance must satisfy [37]

$$\begin{array}{ccc}\hfill L& >& {\displaystyle \frac{{(1-D)}^{2}DR}{2f}}\hfill \end{array}$$

(17)

$$\begin{array}{ccc}\hfill C& >& {\displaystyle \frac{D{V}_o}{Rf\Delta V_o}},\hfill \end{array}$$

(18)

where f is the switching frequency.

Although parasitic elements are neglected in the control-oriented small-signal model, the influence of the inductor parasitic resistance $R_L$ on the steady-state voltage gain and power-conversion efficiency can be evaluated as [38]

$$\begin{array}{ccc}\hfill A_V& =& {\displaystyle \frac{V_o}{V_{in}}}=\left({\displaystyle \frac{1}{1-D}}\right)\left({\displaystyle \frac{1}{{\displaystyle 1+\frac{R_L}{{(1-D)}^{2}R}}}}\right)\hfill \end{array}$$

(19)

$$\begin{array}{ccc}\hfill \eta & =& {\displaystyle \frac{1}{{\displaystyle 1+\frac{R_L}{{(1-D)}^{2}R}}}}.\hfill \end{array}$$

(20)

Figure 2 illustrates the effect of the duty cycle and normalized inductor parasitic resistance $R_L/R$ on the voltage gain and conversion efficiency. Increasing D increases the ideal conversion ratio, whereas increasing $R_L/R$ reduces both the achievable voltage gain and efficiency. These relationships illustrate the influence of the duty cycle and inductor parasitic resistance on the steady-state voltage gain and power-conversion efficiency.

2.3. Cascade-Control Structure

The Boost converter is controlled using a cascade architecture comprising a fast inner current loop and a slower outer voltage loop, as shown in Figure 3a. The inner loop regulates the inductor current, whereas the outer loop regulates the output voltage and generates the current reference required by the inner loop. This separation of the control time scales facilitates the synthesis of the two controllers and improves reference tracking and disturbance rejection. The current-feedback path is assumed to have unity incremental gain in the analytical model; any nonunity current-sensing gain can be incorporated multiplicatively into the inner-loop plant.

The controllers $G_{ci}\left(s\right)$ and $G_{cv}\left(s\right)$ correspond to the inner current and outer voltage loops, respectively. The outer voltage controller generates the inductor-current reference for the inner loop, whereas the output of the current controller determines the duty-cycle variation $d\left(s\right)$ applied to the converter through the pulse-width-modulation (PWM) stage. Since $d\left(s\right)$ is the control variable of the small-signal converter model, the PWM stage is not explicitly represented in the block diagram used for controller synthesis.

For practical implementation, the output voltage is scaled by the resistive divider formed by $R_{D1}$ and $R_{D2}$, as shown in Figure 3a. The resulting feedback voltage ${\widehat{V}}_o\left(s\right)$ is

$${\widehat{V}}_o\left(s\right)=H_v{V}_o\left(s\right),H_v={\displaystyle \frac{R_{D2}}{R_{D1}+R_{D2}}},$$

(21)

where $H_v$ denotes the voltage-feedback gain introduced by the resistive divider, and the reference signal $U\left(s\right)$ is scaled consistently with the same feedback-voltage range. Assuming that $R_{D1}+R_{D2}\gg R$, so that the divider does not significantly load the converter output, the corresponding transfer functions become

$$\begin{array}{ccc}\hfill G_{voiL}\left(s\right)& =& {\displaystyle \frac{{\widehat{V}}_o\left(s\right)}{i_L\left(s\right)}}\approx \left({\displaystyle \frac{R}{RCs+1}}\right)H_v\hfill \end{array}$$

(22)

$$\begin{array}{ccc}\hfill G_{vovg}\left(s\right)& =& {\displaystyle \frac{{\widehat{V}}_o\left(s\right)}{V_g\left(s\right)}}=\left({\displaystyle \frac{1-D}{{\displaystyle LC{s}^2+\frac{L}{R}s+{(1-D)}^2}}}\right)H_v.\hfill \end{array}$$

(23)

For proper cascade operation, the inner current loop is designed to exhibit faster dynamics than the outer voltage loop. Accordingly, the settling-time specifications are selected such that $t_{s,i}<t_{s,v}$, providing the required separation between the current- and voltage-loop time scales.

2.4. Controller Design Fundamentals

2.4.1. Design Specifications

The desired transient response is characterized using a canonical second-order underdamped model, with the settling time defined according to the 2% criterion. From the prescribed maximum overshoot $M_p$, settling time $t_s$, and steady-state error $e_{ss}$, the damping ratio $\zeta$, phase margin ${\varphi }_m$, closed-loop bandwidth ${\omega }_{BW}$, and required low-frequency loop gain $K_n$ are calculated as

$$\zeta ={\displaystyle \frac{\left|\ln \left(M_p/100\right)\right|}{\sqrt{{\pi }^2+{\ln }^2\left(M_p/100\right)}}},$$

(24)

$${\varphi }_m=\arctan \left[2\zeta {\left(-2{\zeta }^2+\sqrt{4{\zeta }^4+1}\right)}^{-1/2}\right],$$

(25)

$${\omega }_{BW}={\displaystyle \frac{4}{\zeta t_s}}\sqrt{(1-2{\zeta }^2)+\sqrt{4{\zeta }^4-4{\zeta }^2+2}},$$

(26)

and

$$K_n={\displaystyle \frac{100}{e_{ss}}}-1.$$

(27)

Here, $M_p$ and $e_{ss}$ are expressed as percentages, ${\varphi }_m$ in (25) is obtained in radians and is subsequently expressed in degrees for the frequency-domain design calculations, and $t_s$ is expressed in seconds.

For the analytical synthesis, the closed-loop bandwidth obtained from the prescribed transient-response specifications is adopted as an estimate of the target crossover frequency:

$${\omega }_c\approx {\omega }_{BW}.$$

(28)

2.4.2. PI and Fractional-Order PI Controllers

The fractional-order $P{I}^{\lambda }{D}^{\mu }$ controller generalizes the conventional PID structure by introducing the integration and differentiation orders $\lambda$ and $\mu$ as additional real-valued parameters [39]. Its transfer function is

$$C\left(s\right)=K_p+{\displaystyle \frac{K_i}{s^{\lambda }}}+K_d{s}^{\mu },$$

(29)

where $K_p$, $K_i$, and $K_d$ are the proportional, integral, and derivative gains, respectively. The conventional PID controller is recovered for $\lambda =\mu =1$.

For the cascade-control problem considered in this work, only proportional and integral actions are required for the reference controllers. Therefore, setting $K_d=0$ yields the fractional-order PI (FO–PI) controller

$$C\left(s\right)=K_p+{\displaystyle \frac{K_i}{s^{\lambda }}},$$

(30)

which reduces to the conventional PI controller when $\lambda =1$.

Conventional PI and FO–PI controllers have previously been applied to the inner current and outer voltage loops of the Boost converter considered in this study [40]. These controllers are therefore included as benchmark strategies for comparison with the integer-order and fractional-order lead–lag compensators considered in this work.

2.4.3. Integer-Order Lead–Lag Compensation

Phase-lead and phase-lag compensators modify the frequency response of a system to improve its steady-state and transient performance. Phase-lag compensation is primarily used to increase low-frequency gain, whereas phase-lead compensation provides positive phase and generally increases the achievable bandwidth [41]. Wang [30] proposed an analytical procedure for determining the parameters of a single-stage lead or lag compensator from prescribed magnitude and phase contributions at a selected crossover frequency.

The compensator is defined as

$$C\left(s\right)=K\left({\displaystyle \frac{1+\alpha \tau s}{1+\tau s}}\right),$$

(31)

where K is the DC gain, and $\alpha$ and $\tau$ determine the pole–zero configuration. Using the performance relationships introduced in Section 2.4.1, let M (dB) and p (rad), with $-\pi /2\le p\le \pi /2$, denote the required magnitude and phase contributions of the compensator at the crossover frequency ${\omega }_c$, respectively. Defining $c={10}^{M/20}$ and $\delta =\tan \left(p\right)$, a single-stage solution exists if [30]

$$\begin{array}{ccc}\hfill c& >& \sqrt{1+{\delta }^2},0<p\le \pi /2(\mathrm{phase}\mathrm{lead})\hfill \end{array}$$

(32)

$$\begin{array}{ccc}\hfill c& <& {\displaystyle \frac{1}{\sqrt{1+{\delta }^2}}},-\pi /2\le p<0(\mathrm{phase}\mathrm{lag}).\hfill \end{array}$$

(33)

When the corresponding feasibility condition is satisfied, the compensator parameters are obtained analytically as

$$\begin{array}{ccc}\hfill \alpha & =& {\displaystyle \frac{c\left(c\sqrt{1+{\delta }^2}-1\right)}{c-\sqrt{1+{\delta }^2}}}\hfill \end{array}$$

(34)

$$\begin{array}{ccc}\hfill \tau & =& {\displaystyle \frac{c-\sqrt{1+{\delta }^2}}{c\delta {\omega }_c}}.\hfill \end{array}$$

(35)

If neither condition is satisfied, the prescribed magnitude and phase contributions cannot be simultaneously achieved by the single-stage compensator in (31).

2.4.4. Fractional-Order Lead–Lag Compensation

Tavazoei [31] extended Wang’s analytical procedure to fractional-order phase-lead and phase-lag compensation by introducing the fractional order q as an additional degree of freedom. The resulting compensator is defined as

$$C_f\left(s\right)=K\left({\displaystyle \frac{1+\alpha \tau s^q}{1+\tau s^q}}\right),q\in (0,2).$$

(36)

Using the same definitions of K, c, p, and ${\omega }_c$ introduced for the integer-order compensator, a single-stage fractional-order solution exists if the corresponding feasibility condition is satisfied [31]:

$$\begin{array}{ccc}\hfill \cot \left({\displaystyle \frac{q\pi }{2}}\right)& <& {\displaystyle \frac{c\cos \left(p\right)-1}{c\sin \left(p\right)}},0<p\le {\displaystyle \frac{\pi }{2}}(\mathrm{phase}\mathrm{lead})\hfill \end{array}$$

(37)

$$\begin{array}{ccc}\hfill \cot \left({\displaystyle \frac{q\pi }{2}}\right)& <& {\displaystyle \frac{c-\cos \left(p\right)}{\sin \left(p\right)}},-{\displaystyle \frac{\pi }{2}}\le p<0(\mathrm{phase}\mathrm{lag}).\hfill \end{array}$$

(38)

When the corresponding feasibility condition is satisfied, the compensator parameters are obtained analytically as

$$\begin{array}{ccc}\hfill \alpha & =& {\displaystyle \frac{ab\tan \left(\frac{q\pi }{2}\right)-1}{b\tan \left(\frac{q\pi }{2}\right)-1}}\hfill \end{array}$$

(39)

$$\begin{array}{ccc}\hfill \tau & =& {\displaystyle \frac{1}{{\omega }_c^q}}\left[b\sin \left({\displaystyle \frac{q\pi }{2}}\right)-\cos \left({\displaystyle \frac{q\pi }{2}}\right)\right],\hfill \end{array}$$

(40)

where the auxiliary variables a and b are defined as

$$\begin{array}{ccc}\hfill a& =& c{\displaystyle \frac{c-\cos \left(p\right)}{c\cos \left(p\right)-1}}\hfill \end{array}$$

(41)

$$\begin{array}{ccc}\hfill b& =& {\displaystyle \frac{c\cos \left(p\right)-1}{c\sin \left(p\right)}}.\hfill \end{array}$$

(42)

In addition to satisfying the prescribed magnitude and phase contributions at ${\omega }_c$, the fractional order q provides an additional degree of freedom that can be used to impose a prescribed initial control-signal value $u_0$. For a step input and phase-lead compensation, $u_0\in (K,\infty )$ and q is determined as [31]

$$q=\left\{\begin{array}{ccc}{\displaystyle \frac{2}{\pi }{\tan }^{-1}\left(\frac{u_0-K}{b(u_0-Ka)}\right),}\hfill & \mathrm{if}\hfill & b(u_0-Ka)>0\hfill \\ 1,\hfill & \mathrm{if}\hfill & b(u_0-Ka)=0\hfill \\ {\displaystyle 2+\frac{2}{\pi }{\tan }^{-1}\left(\frac{u_0-K}{b(u_0-Ka)}\right),}\hfill & \mathrm{if}\hfill & b(u_0-Ka)<0\hfill \end{array}\right.$$

(43)

For phase-lag compensation, $u_0\in (0,K)$ and the corresponding fractional order is

$$q=\left\{\begin{array}{ccc}{\displaystyle 2+\frac{2}{\pi }{\tan }^{-1}\left(\frac{u_0-K}{b(u_0-Ka)}\right),}\hfill & \mathrm{if}\hfill & b(u_0-Ka)>0\hfill \\ 1,\hfill & \mathrm{if}\hfill & b(u_0-Ka)=0\hfill \\ {\displaystyle \frac{2}{\pi }{\tan }^{-1}\left(\frac{u_0-K}{b(u_0-Ka)}\right),}\hfill & \mathrm{if}\hfill & b(u_0-Ka)<0.\hfill \end{array}\right.$$

(44)

Thus, unlike the integer-order compensator, the fractional-order formulation allows the initial control effort to be explicitly incorporated as a design constraint while preserving the analytical nature of the synthesis procedure.

2.4.5. Rational Approximation for Electronic Realization

For practical implementation, the fractional-order operator $s^q$ in (36) must be represented by an integer-order rational approximation. Using the first-order CFE approximation in (5), two cases arise depending on the value of q.

• Case I ($0<q<1$): The fractional-order compensator is approximated as

$$C_f\left(s\right)\approx K\left({\displaystyle \frac{1+\alpha \tau A_1}{1+\tau A_1}}\right)\left({\displaystyle \frac{{\displaystyle s+\frac{A_1+\alpha \tau }{1+\alpha \tau A_1}}}{{\displaystyle s+\frac{A_1+\tau }{1+\tau A_1}}}}\right),$$

(45)

where $A_1$ is given by (7).

• Case II ($1<q<2$): Defining $\tilde{q}=q-1$, the fractional operator can be written as $s^q=s{s}^{\tilde{q}}$, where $0<\tilde{q}<1$. Applying (5) to $s^{\tilde{q}}$ gives

$$\begin{array}{ccc}\hfill C_f\left(s\right)& \approx & K{\displaystyle \frac{1+\alpha \tau s\left({\displaystyle \frac{A_{1}s+1}{s+A_1}}\right)}{1+\tau s\left({\displaystyle \frac{A_{1}s+1}{s+A_1}}\right)}}\hfill \\ & =& \alpha K\left({\displaystyle \frac{{\displaystyle s^2+\frac{{\omega }_z}{Q_z}s+{\omega }_z^2}}{{\displaystyle s^2+\frac{{\omega }_p}{Q_p}s+{\omega }_p^2}}}\right),\hfill \end{array}$$

(46)

where $A_1$ is obtained from (7) by replacing q with $\tilde{q}$, and

$$\begin{array}{ccc}\hfill {\omega }_p& =& {\displaystyle \frac{1}{\sqrt{\tau }}},\hfill \end{array}$$

(47)

$$\begin{array}{ccc}\hfill Q_p& =& {\displaystyle \frac{\sqrt{\tau }{A}_1}{\tau +1}},\hfill \end{array}$$

(48)

$$\begin{array}{ccc}\hfill {\omega }_z& =& {\displaystyle \frac{1}{\sqrt{\alpha \tau }}},\hfill \end{array}$$

(49)

$$\begin{array}{ccc}\hfill Q_z& =& {\displaystyle \frac{\sqrt{\alpha \tau }{A}_1}{\alpha \tau +1}}.\hfill \end{array}$$

(50)

For $q=1$, no rational approximation is required, since (36) directly reduces to the corresponding integer-order lead–lag compensator. Therefore, (45) and (46) provide first-order rational realizations over the two fractional-order intervals $0<q<1$ and $1<q<2$, respectively.

3. Design and Evaluation Methodology

This section presents the methodology adopted for both the integrated analytical design and the systematic numerical evaluation of the Boost DC–DC converter and its cascade control system. The methodology is organized into two complementary stages. First, the power stage and the inner current and outer voltage controllers are obtained through an integrated analytical design procedure starting from prescribed electrical and closed-loop performance specifications. Second, the resulting controllers are systematically evaluated under nominal and perturbed operating conditions using the averaged small-signal representation of the converter. This organization separates the proposed engineering design procedure from the numerical framework subsequently used to assess nominal performance, sensitivity to the fractional-order approximation, operating-point dependence, robustness to converter-parameter variations, sensitivity to controller-component tolerances, and load-disturbance rejection.

3.1. Integrated Analytical Design Procedure

The proposed design procedure integrates the sizing of the Boost power stage with the sequential analytical synthesis of its cascade current-mode control system. Starting from the electrical specifications of the converter and the prescribed transient- and steady-state performance requirements, the procedure sequentially determines the power-stage parameters, the inner current controller, and the outer voltage controller. Controller synthesis is performed using either the integer-order analytical method of Wang et al. [30] or its fractional-order extension by Tavazoei et al. [31], within the integrated design sequence that subsequently includes electronic realization, commercial component selection, and implementation-oriented verification.

The power-stage design starts from the input voltage $V_{in}$, desired output voltage $V_o$, rated output power $P_o$, switching frequency f, and admissible output-voltage ripple $\Delta V_o$. The nominal duty cycle and load resistance are obtained from the steady-state operating conditions, whereas the inductance L and capacitance C are selected using the design relationships in Section 2.2 so that the prescribed ripple requirements are satisfied and continuous-conduction-mode operation is maintained. Once the power-stage parameters and nominal operating point have been established, the averaged small-signal model is evaluated to obtain $G_{id}\left(s\right)$ and $G_{voiL}\left(s\right)$, which constitute the plant models required for the sequential cascade-controller design.

For each control loop, the prescribed values of $M_p$, $t_s$, and $e_{ss}$ are mapped into the damping ratio $\zeta$, phase margin ${\varphi }_m$, target bandwidth ${\omega }_{BW}$, and required low-frequency loop gain $K_n$ using the analytical relationships introduced in Section 2.4.1. For controller synthesis, the target crossover frequency is selected as ${\omega }_c\approx {\omega }_{BW}$, using the closed-loop bandwidth as an approximation of the desired loop crossover frequency. Consistent with the cascade-control requirement established in Section 2.3, the settling-time specifications are selected such that $t_{s,i}<t_{s,v}$, ensuring faster inner-loop dynamics.

The inner current loop is designed first using $G_{id}\left(s\right)$. After the inner loop is closed, its dynamics are incorporated into the effective plant seen by the outer voltage loop through the cascade structure defined in Section 2.3. The outer voltage controller is then synthesized from the corresponding voltage-loop specifications. Consequently, the inner-loop dynamics are explicitly included in the outer-loop design rather than treating the two controllers independently. For each loop, the integer-order and fractional-order designs share the same performance specifications and plant model; however, the fractional-order formulation introduces the order q as an additional design variable and incorporates the prescribed initial control signal $u_0$ as an additional synthesis constraint.

For the integer-order design, Wang’s analytical relationships are used to determine the compensator gain, phase contribution, and pole–zero parameters directly from the prescribed performance requirements and the uncompensated frequency response. For the fractional-order design, the same sequential procedure is followed, but the fractional order q provides an additional degree of freedom that is used to prescribe the initial control-signal value $u_0$. Thus, the fractional-order formulation incorporates a control-effort constraint directly into the analytical synthesis while retaining the magnitude and phase requirements at the target crossover frequency. No numerical optimization or iterative controller tuning is required in either design procedure.

The analytically obtained fractional-order controllers are subsequently expressed in the rational forms described in Section 2.4.5, providing the connection between the analytical synthesis, numerical simulation, and practical electronic realization. Integer-order compensators can be implemented directly using conventional operational-amplifier circuits, whereas fractional-order compensators are first represented through the corresponding CFE rational approximation. The resulting transfer functions are then used to determine the resistor and capacitor values of the analog realizations.

To enable direct comparison with the controllers reported in [23,40], the electrical specifications and component values of the converter considered in those studies are adopted for the comparative case study presented here. Thus, although power-stage sizing forms part of the general methodology, the previously reported converter is retained in this case to provide a common plant for controller comparison. The resulting parameters are summarized in

Table 2. Parameters of the Boost converter used for the comparative case study.

Parameter	Value	Parameter	Value
Vin	60 V	Vo	120 V
Po	120 W	R	120 Ω
C	400 µF	L	2.5 mH
f	40 kHz	D	0.5

.

For consistency with [23,40], the voltage-divider network $R_{D1}$–$R_{D2}$ is omitted in the comparative case study. Substitution of the parameters in Table 2 into the averaged small-signal model yields

$$G_{id}\left(s\right)={\displaystyle \frac{\mathrm{48,000}s+\mathrm{2,000,000}}{s^2+20.83s+\mathrm{250,000}}},G_{voiL}\left(s\right)={\displaystyle \frac{120}{0.048s+1}}.$$

(51)

The proposed controllers are benchmarked against the integer-order and fractional-order PI controllers reported in [40]. In that work, the IO–PI and FO–PI controllers were designed using SISOTOOL. The inner current loop was tuned for a damping ratio of $\zeta =0.707$ ($M_p=4.3\%$), while maintaining the closed-loop bandwidth below one-fifth of the switching frequency. The same damping-ratio specification was adopted for the outer voltage loop. The resulting controllers are

$$G_{ci}\left(s\right)=0.3040+{\displaystyle \frac{2172}{s^{\lambda }}},G_{cv}\left(s\right)=0.2507+{\displaystyle \frac{61.15}{s^{\lambda }}},$$

(52)

where $\lambda =1$ and $\lambda =0.5$ correspond to the IO–PI and FO–PI implementations, respectively.

The design specifications adopted for the proposed compensators were selected to provide transient-response requirements comparable to those achieved by the IO–PI controllers reported in [40]. The FO–PI controllers were not used as the reference for selecting these specifications because their substantially faster responses are accompanied by excessively large control signals, as discussed in Section 4. In the proposed fractional-order design, this limitation is explicitly addressed by imposing a prescribed constraint on the initial control signal.

The complete integrated design procedure is summarized in Figure 4.

Starting from the converter specifications and the prescribed closed-loop performance requirements, the procedure sequentially addresses Boost power-stage sizing, small-signal modeling, inner current-loop design, construction of the effective outer-loop plant, outer voltage-loop design, and electronic realization. Integer- or fractional-order lead–lag compensation can be selected independently for each loop. The resulting controller parameters are subsequently translated into practical component values for implementation and verification.

3.1.1. Integer-Order Design Procedure

The integer-order design procedure applies Wang’s analytical method sequentially to the inner current and outer voltage loops. The corresponding compensators are defined as

$$\begin{array}{ccc}\hfill G_{ci}\left(s\right)& =& K_{int}\left({\displaystyle \frac{1+{\alpha }_i{\tau }_{i}s}{1+{\tau }_{i}s}}\right),\hfill \end{array}$$

(53)

$$\begin{array}{ccc}\hfill G_{cv}\left(s\right)& =& K_{ext}\left({\displaystyle \frac{1+{\alpha }_e{\tau }_{e}s}{1+{\tau }_{e}s}}\right).\hfill \end{array}$$

(54)

The design is carried out according to the following procedure:

1.

Specify the desired values of $M_p$, $t_s$, and $e_{ss}$ for the inner and outer control loops.

2.

Calculate $\zeta$, ${\varphi }_m$, ${\omega }_{BW}$, and $K_n$ from (24)–(27). The parameter $K_n$ represents the low-frequency loop gain required to satisfy the prescribed steady-state error. For controller synthesis, the target crossover frequency is approximated as ${\omega }_c\approx {\omega }_{BW}$.

3.

Design the inner current loop. Since $G_{id}\left(0\right)$ contributes to the low-frequency loop gain, the DC gain required from the inner compensator is

$$K_{int}={\displaystyle \frac{K_n}{G_{id}\left(0\right)}}.$$

(55)

Evaluate the magnitude and phase of $K_{int}{G}_{id}\left(j{\omega }_c\right)$. Denoting the uncompensated-loop phase at ${\omega }_c$ by ${\varphi }_u$, calculate the required phase contribution as

$$p=-\pi +{\varphi }_m-{\varphi }_u.$$

(56)

The required magnitude contribution M is the negative of the uncompensated-loop magnitude, expressed in decibels.

4.

Calculate $c={10}^{M/20}$ and $\delta =\tan \left(p\right)$, verify the corresponding feasibility condition in (32) or (33), and calculate ${\alpha }_i$ and ${\tau }_i$ from (34) and (35).

5.

Once the inner current controller has been obtained, form the equivalent plant for the outer-loop design as

$$K_{LI}\left(s\right)=G_{voiL}\left(s\right)\left[{\displaystyle \frac{G_{ci}\left(s\right)G_{id}\left(s\right)}{1+G_{ci}\left(s\right)G_{id}\left(s\right)}}\right].$$

(57)

Thus, $K_{LI}\left(s\right)$ includes the closed inner current loop connected in series with the current-to-output-voltage dynamics $G_{voiL}\left(s\right)$.

6.

Design the outer voltage loop. Since $K_{LI}\left(0\right)$ now contributes to the low-frequency gain of the outer loop, the DC gain required from the outer compensator is

$$K_{ext}={\displaystyle \frac{K_n}{K_{LI}\left(0\right)}}.$$

(58)

Evaluate the magnitude and phase of $K_{ext}{K}_{LI}\left(j{\omega }_c\right)$ and determine the required compensator contributions M and p as in Step 3. Calculate c and $\delta$, verify the corresponding feasibility condition, and obtain ${\alpha }_e$ and ${\tau }_e$ from (34) and (35).

7.

Construct $G_{ci}\left(s\right)$ and $G_{cv}\left(s\right)$ from (53) and (54) and evaluate the resulting cascade-controlled system against the prescribed performance specifications.

For the comparative case study, the inner-loop specifications are $M_p<5\%$, $t_s=0.35$ ms, and $e_{ss}<0.15\%$, whereas the outer-loop specifications are $M_p<5\%$, $t_s=11$ ms, and $e_{ss}<0.2\%$. The resulting design parameters are summarized in

Table 3. Integer-order lead–lag design parameters for the inner and outer control loops.

Parameter	Inner Loop	Outer Loop
$M_p$	<5%	<5%
$t_s$	0.35 ms	11 ms
$e_{ss}$	<0.15%	<0.2%
$\zeta$	0.69	0.69
${\varphi }_m$	64.63°	64.63°
${\omega }_c\approx {\omega }_{BW}$	16.96 krad/s	0.540 krad/s
$K_n$	665.67	499
K	$K_{int}=83.21$	$K_{ext}=4.16$
${\varphi }_u$	−90.07°	−87.80°
M	−47.45 dB	−25.71 dB
p	−25.30°	−27.58°
c	0.00424	0.05185
$\delta$	−0.473	−0.522
$\alpha$	0.00383	0.04535
$\tau$	0.03240	0.07366

.

Using the parameters in Table 3, the inner-loop compensator is

$$G_{ci}\left(s\right)=83.21\left({\displaystyle \frac{1+\left(0.00383\right)\left(0.0324\right)s}{1+0.0324s}}\right),$$

(59)

whereas the outer-loop compensator is

$$G_{cv}\left(s\right)=4.16\left({\displaystyle \frac{1+\left(0.04535\right)\left(0.0736\right)s}{1+0.0736s}}\right).$$

(60)

The resulting compensators are subsequently evaluated against the prescribed transient- and steady-state performance specifications.

3.1.2. Fractional-Order Design Procedure

The fractional-order design follows the same sequential cascade procedure described in Section 3.1.1. Therefore, the calculation of $\zeta$, ${\varphi }_m$, ${\omega }_{BW}$, $K_n$, $K_{int}$, and $K_{ext}$, as well as the construction of the equivalent outer-loop plant after closing the inner loop, follows the same sequence as in the integer-order case. The additional fractional orders $q_i$ and $q_e$ are used to impose prescribed initial control-signal values on the inner and outer loops, respectively.

The design is carried out according to the following procedure:

1.

Specify $M_p$, $t_s$, $e_{ss}$, and the initial control signal $u_0$ for each loop. Calculate $\zeta$, ${\varphi }_m$, ${\omega }_{BW}$, $K_n$, and the corresponding controller gain following Steps 1–3 of Section 3.1.1, with ${\omega }_c\approx {\omega }_{BW}$.

2.

For the inner current loop, evaluate the magnitude and phase of $K_{int}{G}_{id}\left(j{\omega }_c\right)$ and determine the required magnitude contribution M and phase contribution p as in the integer-order procedure. Calculate $c={10}^{M/20}$ and the auxiliary parameters a and b from (41) and (42).

3.

Using the prescribed initial control signal $u_{0,i}$, calculate $q_i$ from (43) or (44), according to the required phase contribution. Verify the corresponding feasibility condition in (37) or (38); if it is satisfied, calculate ${\alpha }_i$ and ${\tau }_i$ from (39) and (40) and construct $G_{cif}\left(s\right)$.

4.

Close the fractional-order inner current loop and form the equivalent outer-loop plant as

$$K_{L{I}_f}\left(s\right)=G_{voiL}\left(s\right)\left[{\displaystyle \frac{G_{cif}\left(s\right)G_{id}\left(s\right)}{1+G_{cif}\left(s\right)G_{id}\left(s\right)}}\right].$$

(61)

Determine $K_{ext}$ from the low-frequency gain requirement following the same procedure used for the integer-order outer loop.

5.

For the outer voltage loop, evaluate the magnitude and phase of $K_{ext}{K}_{L{I}_f}\left(j{\omega }_c\right)$ and calculate M, p, c, a, and b. Using $u_{0,e}$, determine $q_e$, verify the corresponding fractional-order feasibility condition, and calculate ${\alpha }_e$ and ${\tau }_e$ to construct $G_{cvf}\left(s\right)$.

6.

For numerical simulation and electronic realization, obtain the rational approximations of $G_{cif}\left(s\right)$ and $G_{cvf}\left(s\right)$ using (45) for $0<q<1$ or (46) for $1<q<2$.

For the comparative case study, the inner-loop specifications are $M_p=5\%$, $t_s=5$ ms, $e_{ss}=0.15\%$, and $u_{0,i}=4$, whereas the outer-loop specifications are $M_p=5\%$, $t_s=11$ ms, $e_{ss}=0.2\%$, and $u_{0,e}=3.5$. The resulting fractional-order design parameters are summarized in

Table 4. Fractional-order lead–lag design parameters for the inner and outer control loops.

Parameter	Inner Loop	Outer Loop
$M_p$	5%	5%
$t_s$	5 ms	11 ms
$e_{ss}$	0.15%	0.2%
$u_0$	4	3.5
$\zeta$	0.6901	0.6901
${\varphi }_m$	64.63°	64.63°
${\omega }_c\approx {\omega }_{BW}$	1.1871 krad/s	0.5396 krad/s
$K_n$	$K_{n,i}=665.67$	$K_{n,e}=499$
K	$K_{int}=83$	$K_{ext}=4$
${\varphi }_u$	−90.79°	−87.78°
M	−72.22 dB	−25.35 dB
p	−24.59°	−27.59°
c	0.000245	0.05400
a	2.228 × 10−4	0.04720
b	9.807 × 103	38.07
q	$q_i=1.9987$	$q_e=1.9975$
$\alpha$	0.04819	0.8750
$\tau$	1.4925 × 10−5	4.0165 × 10−6

.

Using the parameters in Table 4, the inner-loop compensator is

$$G_{cif}\left(s\right)=83\left({\displaystyle \frac{1+\left(0.04819\right)(1.4925\times {10}^{-5})s^{1.9987}}{1+1.4925\times {10}^{-5}{s}^{1.9987}}}\right),$$

(62)

whereas the outer-loop compensator is

$$G_{cvf}\left(s\right)=4\left({\displaystyle \frac{1+\left(0.8750\right)(4.0165\times {10}^{-6})s^{1.9975}}{1+4.0165\times {10}^{-6}{s}^{1.9975}}}\right).$$

(63)

Since $1<q_i,q_e<2$, the first-order CFE approximation in (46) is applied to both compensators. The resulting rational approximations are

$$G_{cif}\left(s\right)={\displaystyle \frac{4s^2+3582.94s+5.5611\times {10}^6}{s^2+43.1686s+6.70012\times {10}^4}},$$

(64)

and

$$G_{cvf}\left(s\right)={\displaystyle \frac{3.5s^2+1258.91s+9.9589\times {10}^5}{s^2+314.727s+2.48973\times {10}^5}}.$$

(65)

3.1.3. Electronic Realization

The analytically obtained controllers are implemented using the operational-amplifier circuits shown in Figure 5. The same realization procedure applies to both control loops by taking $K=K_{int}$, $\alpha ={\alpha }_i$, and $\tau ={\tau }_i$ for the inner controller, or $K=K_{ext}$, $\alpha ={\alpha }_e$, and $\tau ={\tau }_e$ for the outer controller.

For the integer-order compensator, the circuit in Figure 5a is employed. After selecting the capacitor $C_g$ as a free design parameter, the resistor values $R_1$–$R_4$ are obtained directly from K, $\alpha$, $\tau$, and $C_g$ according to the relationships indicated in the figure.

For a fractional-order compensator with $0<q<1$, the circuit in Figure 5b is used. The values of $C_g$ and $R_x$ are selected as free design parameters, and $A_1$ is calculated from (7). The resistor values $R_1$–$R_4$ are then determined from K, $\alpha$, $\tau$, $A_1$, $R_x$, and $C_g$ using the relationships indicated in the figure.

For $1<q<2$, the circuit in Figure 5c is employed. In this case, the fractional power is expressed as $s^q=s{s}^{\tilde{q}}$, where $\tilde{q}=q-1$, as described in Section 2.4.5. The electronic realization provides two effective degrees of freedom: the time-scaling factor $T_g$ and the impedance-scaling resistance $R_f$. The former is implemented through the product of $R_g$ and $C_g$,

$$T_g=R_g{C}_g.$$

(66)

Thus, after selecting $T_g$ and $R_f$, either $R_g$ or $C_g$ can be chosen according to practical component-value considerations, with the remaining component determined from $T_g=R_g{C}_g$. The parameter $A_1$ is calculated from (7) using $\tilde{q}$. The remaining resistor values are then obtained as

$$\begin{array}{ccc}\hfill R_1& =& {\displaystyle \frac{\tau }{T_g^2}}{R}_f,R_2={\displaystyle \frac{\tau A_1}{T_g(1+\tau )}}{R}_f,\hfill \end{array}$$

(67)

$$\begin{array}{ccc}\hfill R_3& =& {\displaystyle \frac{\alpha \tau A_1}{T_g(1+\alpha \tau )}}{R}_f,R_4={\displaystyle \frac{\alpha \tau }{T_g^2}}{R}_f,\hfill \end{array}$$

(68)

$$\begin{array}{ccc}\hfill R_5& =& \alpha K{R}_f.\hfill \end{array}$$

(69)

The resulting nominal component values for the practical operational-amplifier realizations of the inner and outer IO–LL and FO–LL controllers are summarized in

Table 5. Nominal component values used for the controller realizations.

Controller	Element	Inner Loop	Outer Loop
IO–LL	Cg	100 nF	100 nF
	R1	1.241 kΩ	33.405 kΩ
	R2	323.952 kΩ	736.562 kΩ
	R3	323.952 kΩ	736.562 kΩ
	R4	103.292 kΩ	139.117 kΩ
FO–LL	Rf	3.650 kΩ	1.100 kΩ
	Rg	84.500 kΩ	107.000 kΩ
	Cg	10 nF	10 nF
	R1	76.296 kΩ	3.859 kΩ
	R2	100.042 kΩ	3.266 kΩ
	R3	4.821 kΩ	2.858 kΩ
	R4	3.677 kΩ	3.377 kΩ
	R5	14.600 kΩ	3.850 kΩ

.

3.1.4. Design Automation

The analytical formulation of the proposed methodology enables the complete design procedure to be automated without optimization-based or trial-and-error controller tuning. Consequently, an implementation based on MATLAB R2026a, Simulink, and Simscape Electrical was developed to automate the Boost-converter design, cascade-controller synthesis, electronic realization, and post-design simulation-based verification, without using the numerical evaluation results to retune the analytically obtained controllers. The developed files are provided as Supplementary Materials to reproduce the analytical design procedure, the corresponding block-level verification, and the circuit-level implementation described below.

The MATLAB script dc_dc_lead_lag.m receives the converter electrical specifications and the prescribed performance requirements for the inner and outer control loops. For fractional-order compensation, the desired initial control-signal constraints $u_{0,i}$ and $u_{0,e}$ are additionally specified. From these inputs, the program determines suitable power-stage parameters satisfying the continuous-conduction-mode and output-voltage-ripple constraints in (17) and (18), obtains the corresponding small-signal transfer functions, and applies the analytical procedures described in Section 3.1.1 and Section 3.1.2. Integer- or fractional-order compensation can be independently selected for each control loop.

The program subsequently calculates the controller parameters, the rational approximations required for fractional-order implementation, and the component values of the corresponding operational-amplifier realizations. It also generates the frequency and transient responses required for preliminary verification of the resulting design.

Circuit-level verification is performed using the Simulink/Simscape Electrical model dc_dc_lead_lag.slx, illustrated in Figure 6. The model incorporates the Boost converter shown in Figure 6a and the operational-amplifier controller realizations shown in Figure 6b, using the parameters calculated by the MATLAB script.

Thus, the developed software provides a reproducible automated workflow from converter and closed-loop performance specifications to power-stage sizing, analytical controller synthesis, electronic realization, and simulation-based verification, while preserving the analytical nature of the proposed design methodology.

The supplied MATLAB script reproduces the analytical controller-design procedure, the corresponding block-level verification, and the first- and third-order CFE rational approximations available within the design software. The first-order approximation is the one adopted for the practical analog realization and the associated circuit-level implementation reproduced with the supplied Simulink/Simscape model. The additional fifth- and seventh-order CFE sensitivity results, Monte Carlo converter-parameter analysis, and controller-component-tolerance analysis reported in Section 4 constitute post-design validation studies and are not generated by the supplied Supplementary Files.

3.2. Numerical Evaluation Methodology

The controllers obtained through the integrated analytical design procedure are systematically evaluated using the averaged small-signal representation of the Boost converter and the cascade-control structure defined in Section 2. The numerical evaluation considers nominal closed-loop performance, sensitivity to the fractional-order approximation, reference tracking and input-voltage disturbance rejection, operation away from the nominal design point, robustness to converter-parameter variations, robustness to controller-component tolerances, and load-disturbance rejection. Unless otherwise stated, the controllers are kept fixed at their nominal design values throughout the robustness analyses.

The IO–LL and FO–LL controllers are first evaluated under nominal operating conditions and compared with the IO–PI and FO–PI benchmark controllers. The inner current loop and the complete cascade-controlled voltage loop are analyzed separately using their corresponding reference changes. Closed-loop performance is characterized in terms of maximum overshoot $M_p$, settling time $t_s$, steady-state error $e_{ss}$, maximum control action $u_{\max }$, integral absolute error (IAE), and integral squared control variation (ISU). The first four quantities allow direct verification of the principal design and control-effort requirements, whereas IAE and ISU provide complementary measures of tracking performance and control effort. Because the unconstrained FO–PI produces large control amplitudes, an additional case with an ideal ±5 V output saturation is included to provide an amplitude-limited benchmark.

Because the fractional-order controllers require rational approximations for numerical simulation and practical realization, the influence of the Continued Fraction Expansion (CFE) approximation order is evaluated separately. Different CFE orders are applied while maintaining the analytically obtained fractional-order controller parameters unchanged; therefore, the approximation-order study constitutes a post-design sensitivity evaluation and is not used for controller tuning. The resulting transient responses and control signals are compared to assess the sensitivity of the closed-loop performance to the approximation order and to verify whether a low-order approximation preserves the intended controller behavior.

Reference tracking and input-voltage disturbance rejection are subsequently evaluated by applying successive output-voltage reference changes while superimposing a 10 kHz sinusoidal perturbation with an amplitude equal to 5% of the nominal input voltage. The disturbance is introduced through both the input-voltage-to-inductor-current and input-voltage-to-output-voltage transfer functions. The resulting output-voltage and inductor-current responses are used to assess tracking capability and disturbance attenuation.

The dependence of the closed-loop response on the converter operating point is evaluated for $D=\{0.40,0.45,0.50,0.55,0.60\}$. For each duty cycle, the corresponding steady-state output voltage and averaged small-signal model are recalculated, while the controllers remain fixed at the values obtained for the nominal condition $D=0.5$. A local +10% output-voltage reference step is applied around each operating point. This analysis evaluates the ability of the nominal controller designs to preserve their closed-loop behavior over the considered operating range without retuning.

Robustness to converter-parameter variations is evaluated through a Monte Carlo analysis with $N=1000$ realizations. The inductance L, capacitance C, and load resistance R are independently varied according to uniform distributions within ±20% of their nominal values. The controllers remain fixed at their nominal values, and the operating condition is maintained at $D=0.5$, $V_{in}=60$ V, and $V_{o0}=120$ V. A reference step from 120 to 132 V is applied in each realization, and the resulting distributions of the closed-loop performance indices are used to compare the sensitivity of the IO–LL and FO–LL designs to simultaneous converter-parameter variations.

A second Monte Carlo analysis with $N=1000$ realizations evaluates the robustness of the controller implementations to physical component tolerances. Every resistor and capacitor in the inner- and outer-loop IO–LL and FO–LL circuits is independently varied using uniform distributions, considering tolerances of ±5% for resistors and ±10% for capacitors, without assuming matched components. In this case, the converter parameters are maintained at their nominal values. For each realization, the controller transfer functions resulting from the perturbed circuit components are reconstructed and the complete closed-loop response is evaluated for the same 120–132 V reference step. This analysis quantifies the sensitivity introduced by the practical analog realization independently of converter-parameter uncertainty.

Finally, load-disturbance rejection is evaluated with the output-voltage reference fixed at $V_{\mathrm{ref}}=120$ V. The load resistance is sequentially changed according to

$$120\to 96\to 144\to 120 \Omega$$

(70)

at $t=50$, 100, and 150 ms, respectively, while the controllers remain unchanged. The resulting output-voltage, inductor-current, and capacitor-current responses are analyzed to assess the capability of the IO–LL and FO–LL implementations to reject load disturbances and recover the regulated output voltage.

Together, these numerical experiments provide a systematic assessment of nominal performance, fractional-order approximation sensitivity, operating-point dependence, robustness to converter-parameter variations, sensitivity to physical controller-component tolerances, and load-disturbance rejection. The corresponding results are presented and discussed in Section 4.

4. Closed-Loop Performance and Robustness Evaluation

4.1. Nominal Closed-Loop Performance

The nominal closed-loop performance of the proposed integer-order (IO–LL) and fractional-order (FO–LL) lead–lag controllers was first evaluated for the inner current loop and the complete cascade-controlled voltage loop. The IO–PI and FO–PI controllers were included as benchmarks. For the fractional-order controllers, a first-order CFE approximation was adopted for the nominal comparison, consistently with the low-order implementation considered for the proposed electronic realization; the influence of the approximation order is examined subsequently.

Figure 7 and Figure 8 show the simulated responses and control signals obtained with the proposed IO–LL and FO–LL controllers, respectively.

To complement the conventional transient-performance measures, the integral absolute error (IAE) and the integral squared control variation (ISU) were also calculated. To prevent these integral indices from depending on the small residual steady-state errors, they were evaluated with respect to the corresponding steady-state values as

$$\mathrm{IAE}={\int }_0^{T_f}\left|y_{\infty }-y\left(t\right)\right|dt,$$

(71)

and

$$\mathrm{ISU}={\int }_0^{T_f}{\left[u\left(t\right)-u_{\infty }\right]}^{2}dt.$$

(72)

For the inner and outer loops, respectively, the integration horizons were selected as

$$T_{f,i}=5 \mathrm{ms},T_{f,e}=100 \mathrm{ms}.$$

Table 6. Nominal performance comparison of the controllers.

Controller	${\mathit{M}}_{\mathit{p}}$ (%)	${\mathit{t}}_{\mathit{s}}$	${\mathit{e}}_{\mathit{ss}}$ (%)	IAE	ISU	${\mathit{u}}_{\mathbf{max}}$ (V)
(a) Inner current loop
IO–PI	20.4	0.474 ms	0	1.01 × 10−4	1.17 × 10−4	0.304
FO–PI	0.0026	0.125 µs	0.0026	1.17 × 10−7	3.29 × 10−2	724.3
FO–PI (sat.)	0.0032	4.25 µs	0.0026	2.16 × 10−6	2.16 × 10−4	5.000
IO–LL	21.40	0.437 ms	0.150	8.93 × 10−5	6.40 × 10−5	0.319
FO–LL	0.624	19.1 µs	0.150	1.54 × 10−5	1.01 × 10−4	4.000
(b) Outer voltage loop
IO–PI	15.7	13.0 ms	0	2.10 × 10−3	6.45 × 10−5	0.252
FO–PI	0	77.5 µs	0.0045	4.60 × 10−5	4.15 × 10−3	20.63
FO–PI (sat.)	0	0.121 ms	0.0045	7.11 × 10−5	2.02 × 10−3	5.000
IO–LL	19.43	12.99 ms	0.200	2.57 × 10−3	5.44 × 10−5	0.190
FO–LL	0.573	0.406 ms	0.208	1.39 × 10−4	7.28 × 10−4	3.500

summarizes the quantitative nominal performance of the four controller structures. Since the unconstrained FO–PI produces particularly large control amplitudes, an additional case with an ideal ±5 V saturation applied at the FO–PI controller output, after the rational CFE realization and before the corresponding plant input, is included. This saturation represents a generic amplitude constraint rather than the nonlinear model of a specific electronic device.

The integer-order results show that IO–PI and IO–LL provide comparable settling times and control amplitudes in both loops, although the IO–PI exhibits lower overshoot and steady-state error. Thus, the analytically designed IO–LL achieves a response speed and control demand comparable to those of the integer-order PI benchmark.

A different tradeoff is observed for the fractional-order controllers. The unconstrained FO–PI provides the fastest nominal tracking, but requires control amplitudes far beyond those of the other controllers, reaching 724.3 V in the inner loop and 20.63 V in the outer loop. Imposing the ±5 V limit substantially reduces this demand while preserving a very fast response. In contrast, the FO–LL incorporates the initial control-signal constraint directly into the analytical synthesis and remains below the prescribed amplitude limit without requiring an external saturation element, with $u_{\max }=4$ V and 3.5 V for the inner and outer loops, respectively. The resulting response is slower than that of the saturated FO–PI but requires lower overall control effort, as reflected by the ISU in both loops.

Figure 9 provides a complementary visualization of these tradeoffs, where 100% represents the least favorable value of each metric within the corresponding loop. The unconstrained FO–PI controller is intentionally excluded from this normalization because its extremely large control demand represents an unconstrained ideal benchmark rather than a practically amplitude-limited case. The saturated FO–PI generally provides the fastest tracking response, whereas the FO–LL provides a more balanced compromise between transient performance and control effort. The comparable settling times and control amplitudes of IO–PI and IO–LL are also evident.

No anti-windup compensation is included in the constrained FO–PI because the purpose of this case is to evaluate the original FO–PI design under the same finite control-amplitude limit considered for practical implementation. The saturation is applied only to the controller output; therefore, the internal states of the rational CFE approximation are neither clamped nor reset during saturation and continue to evolve according to the controller dynamics driven by the control error. No back-calculation or other feedback from the saturated output to the controller states is introduced. Consequently, state accumulation during saturation is permitted in this benchmark. Introducing an anti-windup scheme would add an additional control mechanism and modify the original benchmark, leading to a comparison with an augmented FO–PI architecture. Therefore, the constrained FO–PI is used to distinguish the effect of imposing the control-amplitude limit externally from incorporating the control-effort requirement directly into the analytical synthesis, as in the proposed FO–LL design.

Before evaluating the effect of the rational-approximation order on the closed-loop response, the accuracy of the CFE approximation of the fractional operator $s^q$ was quantified in the frequency domain for the actual fractional orders obtained for the FO–LL controllers. For the inner loop, $q_i=1.9987$, whereas for the outer loop, $q_e=1.9975$. Since $1<q<2$, the fractional operator is expressed as $s^q=s{s}^{\tilde{q}}$, with $\tilde{q}=q-1$, and the CFE is applied to the fractional factor $s^{\tilde{q}}$.

For this frequency-domain accuracy assessment, the CFE was additionally frequency-scaled about the corresponding design crossover frequency so that the approximation error could be evaluated over the frequency region relevant to each control loop. This frequency scaling is introduced only for the additional approximation-error analysis reported in Figure 10; the normalized CFE formulation described in Section 2.4.5 is the one used for the practical controller realization and for the closed-loop CFE-order simulations reported subsequently.

For the inner loop, the approximation was evaluated over $0.1{\omega }_{c,i}\le \omega \le 10{\omega }_{c,i}$, with ${\omega }_{c,i}=1187.1$ rad/s, corresponding to $118.71\le \omega \le 11871$ rad/s. For the outer loop, $0.1{\omega }_{c,e}\le \omega \le 10{\omega }_{c,e}$ was considered, with ${\omega }_{c,e}=539.6$ rad/s, corresponding to $53.96\le \omega \le 5396$ rad/s.

The approximation errors decrease systematically as the CFE order increases. For the first-order CFE, the maximum magnitude and phase errors over these intervals are approximately 0.026 dB and 0.26° for the inner loop, and 0.049 dB and 0.50° for the outer loop. The corresponding RMS magnitude and phase errors are approximately 0.015 dB and 0.096° for the inner loop and 0.029 dB and 0.184° for the outer loop. Higher-order CFE approximations further reduce these errors.

Although frequency scaling substantially improves the operator-level approximation around the corresponding crossover frequency, the practical FO–LL implementation in this work was based on the normalized CFE formulation introduced in Section 2.4.5. Therefore, an additional closed-loop comparison was performed to determine whether the absence of frequency scaling in the implemented realization materially affects the resulting FO–LL performance.

Table 7. Closed-loop FO–LL performance using normalized and frequency-scaled CFE realizations.

		${\mathit{M}}_{\mathit{p}}$ (%)		${\mathit{t}}_{\mathit{s}}$		ISU		${\mathit{u}}_{\mathbf{max}}$ (V)
Loop	CFE	Normalized	Scaled	Normalized	Scaled	Normalized	Scaled
Inner	1	0.627	0.631	19.1 µs	20.0 µs	1.008 × 10−4	1.006 × 10−4	4.0
Inner	3	0.592	0.631	19.9 µs	20.0 µs	1.006 × 10−4	1.006 × 10−4	4.0
Inner	5	0.613	0.631	20.0 µs	20.0 µs	1.006 × 10−4	1.006 × 10−4	4.0
Inner	7	0.620	0.631	20.0 µs	20.0 µs	1.006 × 10−4	1.006 × 10−4	4.0
Outer	1	0.572	0.920	0.406 ms	0.426 ms	7.276 × 10−4	7.271 × 10−4	3.5
Outer	3	0.653	0.892	0.422 ms	0.426 ms	7.269 × 10−4	7.271 × 10−4	3.5
Outer	5	0.684	0.892	0.424 ms	0.426 ms	7.268 × 10−4	7.271 × 10−4	3.5
Outer	7	0.727	0.892	0.424 ms	0.426 ms	7.269 × 10−4	7.271 × 10−4	3.5

Note: The maximum control-signal values are identical for the normalized and frequency-scaled realizations for all the cases reported.

shows that frequency scaling has only a limited influence on the evaluated FO–LL closed-loop performance. For the inner loop, the variations in $M_p$, $t_s$, ISU, and $u_{\max }$ are negligible. For the outer loop, the most noticeable difference occurs in the overshoot; however, it remains below 1% for both the normalized and frequency-scaled realizations. The settling time changes only slightly, whereas ISU and $u_{\max }$ remain essentially unchanged. Thus, although frequency scaling improves the approximation of the fractional operator over the frequency region surrounding the crossover frequency, the principal closed-loop performance conclusions obtained with the normalized CFE realization used in the practical implementation are preserved.

The influence of the CFE approximation order on the closed-loop response was then investigated using the normalized CFE formulation employed in the controller realization, considering first-, third-, fifth-, and seventh-order approximations. The FO–PI controller was evaluated with the ±5 V output limitation, whereas the FO–LL controller was evaluated without saturation because its nominal control signal remains within this range. Figure 11 compares the resulting overshoot, settling time, ISU, and maximum control-signal amplitude.

Figure 11 shows that the CFE approximation order has a limited influence on the FO–LL controller. For both loops, $M_p$, $t_s$, ISU, and $u_{\max }$ remain within a narrow range from first- to seventh-order approximations. The constrained FO–PI is also weakly affected in the inner loop, where the ±5 V limit dominates the initial control action. In the outer loop, however, increasing the CFE order produces a slower response with lower ISU; moreover, the seventh-order approximation no longer reaches the saturation limit, with $u_{\max }\approx 4.33$ V.

Overall, the constrained FO–PI exhibits a tradeoff between transient speed and control effort as the CFE order increases, particularly in the outer loop. In contrast, the FO–LL closed-loop response is only weakly affected by the CFE approximation order. The additional frequency-scaling analysis also shows that the FO–LL closed-loop performance obtained with the normalized realization remains close to that obtained when the CFE is scaled around the corresponding crossover frequency. These results support the use of the normalized first-order CFE adopted for the practical low-order realization, since the principal closed-loop performance conclusions are preserved while maintaining a low implementation complexity.

4.2. Reference Tracking and Input-Voltage Disturbance Rejection

The four controllers were evaluated under simultaneous reference changes and input-voltage disturbances using the averaged small-signal model. Successive output-voltage references of $120\to 108\to 114\to 126\to 120$ V were applied at $t=50$, 100, 150 ms, and 200 ms, respectively. Simultaneously, a 10 kHz sinusoidal input-voltage perturbation with an amplitude equal to 5% of the nominal input voltage, $V_{in}=60$ V, was applied around the nominal operating point,

$$V_g\left(t\right)=3\sin \left(2\pi {10}^{4}t\right)\mathrm{V}.$$

(73)

The disturbance was introduced through both $G_{i_L{v}_g}\left(s\right)$ and $G_{v_o{v}_g}\left(s\right)$, thereby accounting for its effect on both the inner current and outer voltage dynamics. The ±5 V control-signal constraint was retained for the FO–PI controller.

Figure 12 shows the output-voltage and average inductor-current responses. All controllers maintain stable tracking for the evaluated reference changes in the presence of the input-voltage disturbance. The zoomed regions around $t=150$ ms highlight the corresponding transients, whereas those between 550 and 560 ms show the residual steady-state oscillations after the reference transient has decayed.

Since the averaged model does not reproduce the 40 kHz PWM switching process, the oscillations observed in the steady-state zooms correspond exclusively to the residual effect of the imposed 10 kHz input-voltage disturbance and not to switching ripple. Their peak-to-peak values were measured directly over $550\le t\le 560$ ms, without additional filtering, as

$$\Delta V_{o,\mathrm{pp}}=V_{o,\max }-V_{o,\min },\Delta i_{L,\mathrm{pp}}=i_{L,\max }-i_{L,\min }.$$

(74)

Figure 13 summarizes the residual peak-to-peak output-voltage and average-inductor-current oscillations produced by the 10 kHz input-voltage disturbance.

For the imposed 10 kHz input-voltage disturbance, the fractional-order controllers provide stronger attenuation than their corresponding integer-order counterparts. FO–PI reduces the output-voltage and inductor-current oscillations by 75.3% and 68.0%, respectively, relative to IO–PI, whereas FO–LL achieves reductions of 57.9% and 61.3% relative to IO–LL. Thus, under the evaluated disturbance condition, the fractional-order implementations maintain stable reference tracking while providing improved disturbance rejection at both the regulated output and the inner current loop.

4.3. Performance at Different Duty-Cycle Operating Points

The proposed IO–LL and FO–LL controllers, designed at the nominal operating point $D=0.5$, were kept fixed and subsequently evaluated at $D=\{0.40,0.45,0.50,0.55,0.60\}$. For $V_{in}=60$ V, the corresponding operating-point voltages, obtained from $V_{o0}=V_{in}/(1-D)$, are $V_{o0}=\{100,109.09,120,133.33,150\}$ V. For each value of D, the averaged small-signal converter model was recalculated without retuning either controller.

Since each small-signal model describes the converter dynamics around its corresponding operating point, a +10% reference step was applied around each $V_{o0}$. The resulting transitions were $100\to 110$, $109.09\to 120$, $120\to 132$, $133.33\to 146.67$, and $150\to 165$ V. Figure 14 shows the resulting output-voltage responses and incremental control signals, whereas

Table 8. Closed-loop performance for +10% reference steps at different duty-cycle operating points.

D	Controller	${\mathit{M}}_{\mathit{p}}$ (%)	${\mathit{t}}_{\mathit{s}}$ (ms)	${\mathit{e}}_{\mathit{ss}}$ (%)	$\mathbf{\Delta }{\mathit{u}}_{\mathbf{max}}$ (V)
0.40	IO–LL	19.436	12.995	0.2002	0.0190
0.45	IO–LL	19.431	12.990	0.2001	0.0190
0.50	IO–LL	19.428	12.986	0.2000	0.0190
0.55	IO–LL	19.426	12.982	0.1999	0.0190
0.60	IO–LL	19.425	12.980	0.1999	0.0190
0.40	FO–LL	0.566	0.402	0.2084	0.3500
0.45	FO–LL	0.569	0.404	0.2083	0.3500
0.50	FO–LL	0.573	0.406	0.2082	0.3500
0.55	FO–LL	0.577	0.407	0.2081	0.3500
0.60	FO–LL	0.581	0.409	0.2081	0.3500

summarizes the corresponding $M_p$, $t_s$, $e_{ss}$, and maximum incremental control action $\Delta u_{\max }$.

The results show that both controllers preserve essentially the same closed-loop behavior throughout the evaluated duty-cycle range without retuning. For IO–LL, the variations in $M_p$, $t_s$, and $e_{ss}$ are negligible, while $\Delta u_{\max }$ remains approximately $0.0190$ V. Similarly, FO–LL maintains $M_p<0.6\%$, $t_s<0.41$ ms, and $e_{ss}\approx 0.21\%$, with $\Delta u_{\max }\approx 0.35$ V at all operating points. The closed inner current loop therefore contributes to reducing the sensitivity of the effective outer-loop dynamics to changes in the duty-cycle operating point over the evaluated range.

For the FO–LL controller, the approximately 0.35 V maximum incremental control action produced by the +10% reference step is consistent with the prescribed $u_0=3.5$ V for a unit normalized reference change.

4.4. Robustness to Converter Parameter Variations

The robustness of the IO–LL and FO–LL controllers to converter-parameter variations was evaluated through a Monte Carlo analysis with $N=1000$ realizations. The controllers were kept fixed at their nominal design values, while L, C, and R were independently varied according to uniform distributions within ±20% of their nominal values. The nominal operating point was maintained at $D=0.5$, $V_{in}=60$ V, and $V_{o0}=120$ V, and a local +10% reference step ($120\to 132$ V) was applied in every realization.

Figure 15 shows the output-voltage and incremental control-signal responses. The shaded regions represent the pointwise 95% intervals obtained from the Monte Carlo realizations, together with the corresponding mean and nominal responses. All 1000 realizations remained stable for both controllers.

Table 9. Monte Carlo results for simultaneous ±20% variations in L, C, and R ($N=1000$).

Metric	IO–LL	FO–LL
Stable cases (%)	100	100
$M_p$ (%)	19.285 ± 1.379	0.570 ± 0.067
$t_s$ (ms)	12.950 ± 0.628	0.406 ± 0.046
$e_{ss}$ (%)	0.2025 ± 0.0234	0.2108 ± 0.0243
$\Delta u_{\max }$ (V)	0.0190 ± 0.00002	0.3500
Original-design compliance
$P(M_p\le 5\%)$	≈0%	≈100%
$P(t_s\le 11 \mathrm{ms})$	≈0.1%	≈100%
$P(e_{ss}\le 0.2\%)$	≈45.8%	≈32.8%
Nominal-performance preservation
$P(M_p\le 1.2M_{p,\mathrm{nom}})$	≈99.8%	≈96.0%
$P(t_s\le 1.2t_{s,\mathrm{nom}})$	≈100%	≈96.1%
$P(e_{ss}\le 1.2e_{ss,\mathrm{nom}})$	≈94.6%	≈94.6%

Note: L, C, and R were independently sampled from bounded uniform distributions over ±20% of their nominal values. This sampling represents bounded parameter uncertainty and does not assume a measured manufacturing distribution. Nominal-performance preservation allows a maximum 20% degradation relative to the achieved nominal value of each performance index.

summarizes the resulting performance indices and the corresponding compliance probabilities. The IO–LL controller exhibits mean values of $M_p$ and $t_s$ close to their nominal values, with standard deviations corresponding to approximately 7.2% and 4.8% of their respective means. For FO–LL, the corresponding relative dispersions are approximately 11.8% and 11.3%; however, the resulting overshoot and settling-time values remain small in absolute terms. The relative dispersion of $e_{ss}$ is similar for both controllers, approximately 12%, while the maximum incremental control action is practically unaffected by the converter-parameter variations. Both controllers remain stable throughout the considered uncertainty range without controller retuning.

The compliance results distinguish between the original outer-loop specifications and preservation of the achieved nominal performance. FO–LL essentially preserves the original $M_p$ and $t_s$ requirements, whereas IO–LL does not, since its nominal complete cascade already exhibits approximately 19% overshoot and 13 ms settling time. Nevertheless, when a maximum 20% degradation relative to the achieved nominal performance is adopted as a robustness criterion, both controllers exhibit high performance-preservation probabilities. The lower compliance with the original $e_{ss}\le 0.2\%$ requirement is explained by the nominal steady-state errors lying very close to this limit.

4.5. Robustness to Controller-Component Tolerances

The robustness of the analog IO–LL and FO–LL implementations was evaluated through a Monte Carlo analysis with $N=1000$ realizations. Every physical resistor and capacitor in the inner- and outer-loop controller circuits was independently varied using uniform distributions, with tolerances of ±5% for resistors and ±10% for capacitors, without assuming matched components. The nominal component values are those reported in Table 5. The converter parameters were kept at their nominal values, and a local reference step from 120 to 132 V was applied.

Figure 16 shows the resulting output-voltage and control-signal responses. The shaded regions represent the 95% intervals, while the nominal and Monte Carlo mean responses are also shown. All 1000 realizations remained stable for both controller implementations.

The transient-response indices remain relatively concentrated despite the independent component variations. For IO–LL, $M_p=19.39\pm 1.55\%$ and $t_s=13.27\pm 1.37$ ms, whereas FO–LL yields $M_p=0.565\pm 0.183\%$ and $t_s=0.409\pm 0.018$ ms. In contrast, the steady-state error is more sensitive to component mismatch, with mean values of 3.996% and 1.072% for IO–LL and FO–LL, respectively.

This sensitivity is mainly associated with resistor-ratio mismatch in the differential and summing stages. When only these resistor tolerances were reduced from ±5% to ±1%, the maximum $e_{ss}$ decreased from 16.95% to 3.17% for IO–LL and from 4.00% to 0.98% for FO–LL. These results indicate that resistor matching in the differential and summing stages plays a dominant role in the steady-state accuracy of the implemented controllers.

Temperature drift was not modeled separately because its quantitative evaluation would require the temperature coefficients and operating-temperature profiles of the specific components. Nevertheless, its principal effect on the passive controller network is reflected in variations of the effective resistor and capacitor values, whose influence is already assessed by the component-tolerance analysis. A dedicated thermal characterization of the analog implementation is therefore beyond the scope of this work.

4.6. Load-Step Disturbance Rejection

The load-disturbance rejection of the IO–LL and FO–LL controllers was evaluated with the controllers fixed at their nominal design values and the output-voltage reference maintained at $V_{\mathrm{ref}}=120$ V. The load resistance was changed according to

$$120\to 96\to 144\to 120 \Omega$$

at $t=50$, 100, and 150 ms, respectively.

Since the analysis is based on averaged small-signal models, the converter model was recalculated for each value of R. The simulation was performed piecewise by switching to the corresponding linearized model at each load transition while preserving the inductor-current, output-voltage, and controller states. Thus, neither the plant nor the controllers were reinitialized, allowing the transient evolution between successive operating conditions to be evaluated continuously.

Figure 17 shows the load profile and the corresponding output-voltage, average inductor-current, and capacitor-current responses. The capacitor current was obtained consistently from the averaged model as

$$i_C\left(t\right)=C{\displaystyle \frac{d{v}_o\left(t\right)}{dt}}.$$

(75)

At each load transition, the inductor current remains continuous and evolves toward the value required by the new load, whereas the capacitor supplies or absorbs the instantaneous current imbalance, with $i_C$ subsequently returning toward zero.

Both controllers maintain stable voltage regulation throughout the load sequence. For the $120\to 96$, $96\to 144$, and $144\to 120 \Omega$ transitions, the maximum absolute output-voltage deviations from the 120-V reference are 0.797, 1.282, and 0.494 V for IO–LL, respectively, and 0.069, 0.062, and 0.042 V for FO–LL.

To quantify disturbance rejection independently of the small steady-state offset, the recovery time was evaluated with respect to the post-disturbance steady-state voltage. For each load transition, $\Delta V_{o,\mathrm{tr}}$ was defined as the maximum transient deviation from the corresponding post-disturbance steady-state value, and $t_r$ as the time required for the output-voltage deviation to enter and remain within 2% of $\Delta V_{o,\mathrm{tr}}$. The corresponding recovery times are approximately 19.1 ms for IO–LL and 7.9 ms for FO–LL for all three load transitions.

Therefore, both controllers reject the considered load variations without retuning, while FO–LL exhibits substantially smaller output-voltage excursions and faster disturbance recovery.

5. Circuit-Level Simulation and Experimental Validation

To complement the comparative evaluation presented in Section 4, the proposed methodology was applied to a second Boost converter intended for experimental implementation. The prototype operates with $V_{in}=20$ V and a nominal output voltage of $V_o=46$ V, with $R=116 \Omega$, $L=0.7$ mH, $C=470$ µF, and a switching frequency of $f=20$ kHz. The nominal duty cycle is $D=0.565$. For this implementation, the cascade architecture combines an IO–LL controller in the inner current loop and an FO–LL controller in the outer voltage loop.

For this hybrid IO–LL/FO–LL configuration, validation is performed at three successive levels: block-level verification using the averaged small-signal model, circuit-level simulation using the switching Simulink/Simscape model, and experimental evaluation using the physical prototype. The controller parameters obtained from the analytical design are retained throughout these stages, enabling a progressive assessment of the design as increasing implementation detail is introduced.

5.1. Automated Controller Design and Block-Level Verification

The controllers were synthesized using the automated procedure described in Section 3.1.4 and implemented in dc_dc_lead_lag.m. The resulting closed-loop system was first evaluated at block level using the averaged small-signal model. The controller parameters and analog component values obtained at this stage were retained for the subsequent circuit-level and experimental validation.

For the inner current loop, the prescribed design specifications were $M_p=5\%$, $t_s=0.5$ ms, and $e_{ss}<0.15\%$ (design value: $e_{ss}=0.1435\%$). The resulting IO–LL controller is

$$G_{ci}\left(s\right)={\displaystyle \frac{0.02957s+166}{0.18179s+1}}.$$

(76)

After closing the inner current loop, the resulting effective plant $K_{LI}\left(s\right)$ is used for the outer-loop synthesis. For the outer voltage loop, $M_p=5\%$, $t_s=25$ ms, and $e_{ss}<0.15\%$ were specified, together with a control-effort specification of $u_{0,e}=5$ V. The resulting fractional-order parameters are $K_{ext}=198$, $q_e=1.1286$, ${\alpha }_e=0.02525$, and ${\tau }_e=0.15377$ s.

Using the first-order CFE adopted for the electronic realization, the ideal fractional-order outer controller is approximated by

$$G_{cvf}\left(s\right)\approx {\displaystyle \frac{5.000s^2+997.97s+1287.61}{s^2+5.7928s+6.5031}}.$$

(77)

The practical component values selected for the circuit implementation are reported in

Table 10. Design parameters and component values of the experimental Boost converter and controllers.

Boost Converter		IO–LL Inner Loop		FO–LL Outer Loop
Figure 3a		Figure 5a		Figure 5c
Element	Value	Element	Value	Element	Value
$V_{in}$	20 V	$R_1$	178 Ω	$R_1$	15.4 kΩ
C	470 µF	$R_2$	180 kΩ	$R_2$	17.4 kΩ
L	0.7 mH	$R_3$	180 kΩ	$R_3$	510 Ω
R	116 Ω	$R_4$	29.4 kΩ	$R_4$	390 Ω
$R_{D1}$	121.5 kΩ	$C_g$	1 µF	$R_5$	500 kΩ
$R_{D2}$	2.7 kΩ			$R_f$	100 kΩ
$\Delta V_{out}$	92 mV			$R_g$	1 MΩ
D	0.565			$C_g$	1 µF
f	20 kHz

.

The block-level closed-loop responses obtained from the averaged small-signal model are shown in Figure 18. The inner-loop response gives $M_p=20.81\%$ and $t_s=0.885$ ms. For the complete cascade system, $M_p=22.12\%$, $t_s=33.06$ ms, and $e_{ss}=0.200\%$ are obtained, with a maximum outer-loop control signal of approximately 5.05 V.

The simulated overshoot is higher than the prescribed 5% value for both loops. This discrepancy can be attributed, at least in part, to evaluating the actual interconnected closed-loop system rather than the second-order reference model used to derive the frequency-domain design specifications. Consequently, the prescribed overshoot should be interpreted as a design target associated with the reference-model-based synthesis rather than as an exact performance constraint on the complete interconnected system. The resulting responses nevertheless provide the baseline block-level behavior against which the subsequent circuit-level and experimental implementations are evaluated. In addition, the maximum outer-loop control signal of approximately 5.05 V closely agrees with the prescribed control-effort specification $u_{0,e}=5$ V, showing that this additional design requirement is effectively reflected in the resulting FO–LL controller.

5.2. Circuit-Level Simulation

The hybrid IO–LL/FO–LL cascade controller was subsequently evaluated using the switching circuit model implemented in dc_dc_lead_lag.slx. Unlike the averaged small-signal model used for block-level verification, the Simulink/Simscape implementation incorporates the switching power stage and the electronic controller realizations using the selected commercial component values. This model therefore provides an intermediate validation stage between the averaged analytical representation and the physical prototype.

Figure 19a shows the circuit-level output-voltage response under successive reference changes. The converter tracks both upward and downward changes while maintaining stable closed-loop operation with the controller parameters obtained from the analytical design. For the final reference transition, from approximately 36.5 to 50.5 V, the response yields $M_p=5.02\%$, $t_s=30.32$ ms, and $e_{ss}=0.236$ V (0.47%). Compared with the block-level response, for which $M_p=22.12\%$, $t_s=33.06$ ms, and $e_{ss}=0.20\%$, the switching circuit model preserves essentially the same settling-time scale and a small steady-state error, while exhibiting a substantially lower overshoot. Because the reference transitions and operating ranges are not identical, the difference in overshoot cannot be attributed solely to model fidelity. It may also be influenced by the range over which the block-level response was evaluated. In that analysis, the output-voltage response spans approximately 0–60 V, whereas the averaged small-signal model is obtained by linearization around the nominal operating point and is therefore intended to represent local perturbations. Such a large excursion may exceed the range over which the linearized model accurately represents the nonlinear Boost-converter dynamics. In contrast, the circuit-level switching model directly represents the converter operation over the complete voltage excursion. Therefore, the reduction from 22.12% to 5.02% should not be interpreted solely as an implementation-induced damping effect, but may also reflect both the different test conditions and the limitations of applying the small-signal block-level model to a large-signal transient.

Figure 19b shows the conversion efficiency after the final reference transition. Over the 0.35–0.50 s interval, the mean simulated efficiency is 98.31%. The remaining ripple is associated with the switching operation and the instantaneous power quantities used to compute the efficiency. This result provides a circuit-level estimate of the power-conversion performance that is not represented by the averaged small-signal closed-loop model.

Figure 19c shows the inner- and outer-loop control signals throughout the complete reference sequence. Both signals remain bounded despite the successive operating-point changes. In particular, the outer-loop control signal remains consistent with the $u_{0,e}=5$ V control-effort specification, while the inner-loop signal exhibits its largest excursion during the most demanding downward transition and subsequently returns to its nominal operating range. These results show that the hybrid cascade controller preserves stable operation over the evaluated reference sequence without controller retuning.

Figure 20 reports the inductor current $i_L$ obtained from the switching circuit-level simulation, including both the instantaneous waveform associated with the 20 kHz PWM operation and its filtered average value. The instantaneous current exhibits the switching-frequency ripple, whereas the average current highlights the slower dynamics imposed by the cascade control system. During the highlighted interval, $i_L$ reaches zero and remains at zero for a finite portion of the transient, indicating a temporary transition from continuous-conduction mode (CCM) to discontinuous-conduction mode (DCM). This behavior occurs when the large-signal transient drives the converter across the CCM–DCM boundary and, consequently, outside the validity region of the CCM small-signal model used for controller synthesis. The observed temporary transition to DCM therefore illustrates the nonlinear large-signal behavior captured by the switching circuit-level model and provides additional information beyond that obtainable from the CCM small-signal representation.

The finite bandwidth and slew-rate limitations of the operational amplifiers were neglected in the circuit-level simulation because the characteristic controller dynamics are well below the corresponding device limits. For the inner-loop controller, the pole is located at approximately $5.51 \mathrm{rad}/\mathrm{s}$, whereas its zero is at $5.63\times {10}^3 \mathrm{rad}/\mathrm{s}$ (≈896 Hz). The outer-loop controller exhibits even slower dynamics, with poles at approximately 1.52 and $4.27 \mathrm{rad}/\mathrm{s}$ and zeros at 1.30 and $198.5 \mathrm{rad}/\mathrm{s}$. The highest of these characteristic frequencies is therefore approximately 896 Hz, more than three orders of magnitude below the typical 3 MHz gain-bandwidth product of the TL084 operational amplifiers used in the experimental implementation. Moreover, the TL084 exhibits a typical slew rate of approximately $13 \mathrm{V}/\mathrm{\mu }\mathrm{s}$, corresponding to an ideal slew-limited transition time of only about $0.385 \mathrm{\mu }\mathrm{s}$ for a 5 V output excursion, whereas the relevant closed-loop transients evolve on a millisecond time scale. Consequently, neither finite gain bandwidth nor slew rate is expected to have a noticeable influence on the reported closed-loop response, and these nonidealities were not explicitly included in the circuit-level model.

5.3. Electronic Implementation and Experimental Setup

The controller circuits were implemented using the practical component values reported in Table 10 and TL084 operational amplifiers supplied at ±5 V.

The inner-loop feedback current is obtained using an ACS712 Hall-effect current sensor with a sensitivity of 0.185 V/A and a zero-current output voltage of 2.5 V. Its output is processed by a conditioning stage with $R_s=10$ k$\Omega$ and $R_f=54$ k$\Omega$, corresponding to a gain of $R_f/R_s=5.4$. The resulting incremental current-feedback gain is therefore $0.185\times 5.4=0.999$ V/A, which is approximated as unity in the small-signal model. The dc offset is removed by the conditioning stage and does not affect the incremental current-feedback signal used by the inner IO–LL controller.

For the outer voltage loop, the output voltage is scaled by the $R_{D1}$–$R_{D2}$ resistor network before being applied to the FO–LL controller. With $R_{D1}=121.5$ k$\Omega$ and $R_{D2}=2.7$ k$\Omega$, the resulting scaling factor is $R_{D2}/(R_{D1}+R_{D2})=0.02174$, such that the nominal converter output of 46 V corresponds to a feedback voltage of approximately $1.00$ V.

Figure 21 shows the implemented controller board, Boost converter, and experimental setup. The power stage and controller were constructed as separate boards, facilitating access to the relevant electrical variables during testing. Under the nominal experimental conditions, the converter operates in continuous-conduction mode, while the selected output capacitance limits the output-voltage ripple.

Experimental characterization was performed using the setup shown in Figure 21b. The experimental tests used the same hybrid IO–LL/FO–LL cascade architecture and controller parameters considered in the block-level and circuit-level evaluations, allowing the three validation levels to be assessed using the same controller configuration.

5.4. Experimental Results and Three-Level Validation

Figure 22 shows the experimental output-voltage response under successive reference changes. Reference voltages of $1.18$, $1.00$, and $0.80$ V correspond to converter output voltages of approximately $54.02$, $45.36$, and $36.46$ V, respectively.

The experimental response confirms stable tracking for both upward and downward reference changes around the nominal 46 V operating point. The same IO–LL inner controller and FO–LL outer controller are retained throughout the complete reference sequence, without gain scheduling or controller retuning. For the reference transition from $54.02$ to $45.36$ V, which brings the converter close to the nominal 46 V operating point, the experimental response yields $M_p=4.2\%$, $t_s=40$ ms, and $e_{ss}=1\%$. The maximum outer-loop control voltage is approximately 5 V, while the measured conversion efficiency is $91\%$. In addition to validating the nominal design, the ability to regulate the output at approximately $36.46$, $45.36$, and $54.02$ V demonstrates that the implemented cascade controller retains stable regulation over the evaluated operating range.

Table 11. Representative performance obtained at the block-level, circuit-level, and experimental validation stages for the hybrid IO–LL/FO–LL controller under their respective test conditions.

Performance Metric	Block-Level	Circuit-Level	Experimental
$M_p$ (%)	22.12	5.02	4.2
$t_s$ (ms)	33.06	30.32	40
$e_{ss}$ (%)	0.2	0.47	1
Efficiency (%)	–	98.31	91
Maximum outer-loop control voltage (V)	5.05	≤5	5

Note: The reported metrics correspond to representative transients evaluated at each validation level rather than to identical reference transitions; therefore, they should not be interpreted as a direct point-by-point comparison.

summarizes the representative performance obtained at the block, circuit, and experimental validation levels. Because the reported metrics correspond to the characteristic transients evaluated at each level rather than to identical reference transitions, the comparison is intended to assess the consistency of the overall closed-loop behavior rather than provide a point-by-point reproduction of the same transient. The three levels represent a progressive transition from the averaged small-signal description used for analytical verification, through the switching circuit and electronic realization, to the physical prototype, while retaining the controller parameters obtained from the analytical design.

The three-level comparison shows that the principal closed-loop characteristics are preserved as increasing implementation detail is introduced. The circuit-level and experimental results exhibit a similar transient time scale and comparable representative overshoot values under their respective test conditions, whereas the block-level averaged model provides a more conservative overshoot prediction. As discussed in Section 5.2, the larger block-level overshoot may be partly associated with the limitations of the averaged small-signal model under the large output-voltage excursion considered.

The control-effort results remain consistent with the analytical design specification. The outer FO–LL controller was synthesized using $u_{0,e}=5$ V as the prescribed control-effort specification, and the resulting maximum outer-loop control signals remain close to this design value at all three validation levels. Likewise, the circuit-level and experimental efficiencies remain high, with the lower experimental value reflecting losses present in the physical converter that are not fully represented in the circuit-level model.

Overall, the results confirm that the analytically synthesized hybrid IO–LL/FO–LL controller can be transferred from the averaged model to the switching circuit and finally to the physical prototype without retuning. The consistency observed between the circuit-level and experimental results under their respective test conditions, together with stable tracking over multiple output-voltage references, supports the practical validity of the proposed design and implementation procedure.

6. Discussion

From a broader perspective, the results address several of the limitations identified in the state-of-the-art analysis. Previous studies generally focus on specific aspects of DC–DC converter control, whereas approaches that jointly integrate transient specifications, analytical design, fractional-order control, explicit consideration of control effort, and a complete validation path up to experimental implementation remain limited. The proposed methodology brings these elements together within a unified specification-driven framework, without requiring optimization procedures to determine the controller parameters. In addition, computational tools are provided to reproduce the controller design and block-level simulations, as well as the circuit-level validation, facilitating verification and reuse of the methodology. Therefore, the contribution lies not only in the performance of a particular controller, but also in establishing a reproducible link between design specifications, analytical synthesis, simulation, and practical implementation.

The sensitivity and robustness evaluations show that the proposed design is not restricted to nominal conditions. Stable operation and acceptable performance are maintained under changes in the fractional approximation order, operation away from the nominal point, converter-parameter variations, controller-component tolerances, and load disturbances. This is particularly relevant for fractional-order controllers, whose practical realization necessarily involves finite-order approximations and components subject to tolerances. Overall, these tests support the robustness of the analytical design against the principal modeling, operating, and implementation uncertainties considered.

The three-level validation of the hybrid IO–LL/FO–LL cascade configuration further demonstrates the transition from analytical synthesis to physical implementation. The averaged small-signal model provides a suitable basis for analytical design and block-level verification, whereas the switching circuit model captures additional large-signal and switching effects that are not represented by the averaged model. Despite these modeling differences, the same analytically obtained controller parameters are transferred from the averaged model to the switching circuit and ultimately to the physical prototype without retuning, while maintaining stable regulation and a control effort close to the prescribed value. This result also emphasizes the complementary roles of the three validation levels rather than requiring the averaged model to reproduce all implementation effects observed in the switching circuit and experimental prototype.

Within this general framework, the FO–LL controller provides the additional capability of explicitly incorporating control effort as a design specification together with the transient-performance requirements. Unlike the FO–PI with ideal saturation, where the control-signal amplitude is bounded through an external constraint, the FO–LL control-effort level is established as part of the analytical synthesis itself, providing a practical advantage for implementation. Although the present formulation and validation are limited to Boost converters operating in CCM, the underlying specification-driven methodology is not inherently restricted to this topology or conduction mode. Extension to other conduction modes, such as Discontinuous Conduction Mode (DCM), would require rederiving the corresponding steady-state relationships and dynamic models before applying the analytical controller-synthesis procedure. Similarly, the methodology could, in principle, be extended to other DC–DC converter topologies, such as Buck, Buck–Boost, Cuk, SEPIC, and Zeta converters, by deriving the corresponding topology-specific models and adapting the analytical synthesis equations to their particular dynamics. Validation of these extensions to other conduction modes and converter topologies constitutes a relevant direction for future work.

7. Conclusions

This paper presented an integrated specification-driven methodology for the analytical design and practical implementation of cascade-controlled Boost DC–DC converters. The proposed framework establishes a direct connection between converter specifications, power-stage sizing, averaged small-signal modeling, analytical controller synthesis, rational approximation of fractional-order dynamics, electronic realization, and experimental implementation. Unlike empirical, heuristic, or optimization-based approaches, the controller parameters are obtained analytically from the prescribed performance requirements, providing a systematic and reproducible design procedure.

The numerical evaluation showed that the resulting controllers maintain stable operation and acceptable performance beyond the nominal design conditions. The sensitivity studies considered the order of the fractional approximation, operation away from the nominal point, converter-parameter variations, controller-component tolerances, and load disturbances. These results indicate that the analytical design is not critically dependent on a particular approximation order or on exact nominal parameter values, which is especially relevant for the practical realization of fractional-order controllers.

For the hybrid IO–LL/FO–LL cascade configuration, the transition from analytical design to physical implementation was further assessed through block-level, switching circuit-level, and experimental validation. The same analytically obtained controller parameters were transferred through these three levels without retuning. Although the averaged small-signal model provides a conservative prediction of the overshoot for the large voltage excursion considered, the circuit-level and experimental evaluations exhibit consistent transient behavior under their respective test conditions. Representative overshoots of approximately 5.02% and 4.2% were obtained in the circuit-level and experimental evaluations, respectively; these values correspond to different reference transitions and are therefore not intended as a direct point-by-point comparison. The settling times nevertheless remain within the same characteristic time scale, and the steady-state error remains at or below 1%. The experimental converter also achieved an efficiency of approximately 91% and maintained stable voltage regulation over multiple reference conditions.

Within this general methodology, the fractional-order lead–lag controller provides an additional design capability by incorporating the control-effort level directly into the analytical synthesis. For the outer loop, the prescribed value of $u_{0,e}=5$ V remained representative from the analytical design through circuit-level simulation and experimental implementation. This differs fundamentally from imposing an external saturation constraint on a controller after synthesis: the required control effort is treated as a design specification rather than as a posteriori limitation. The resulting FO–LL solution therefore provides a direct analytical compromise between transient performance and implementation-oriented control effort.

Finally, the accompanying computational tools reproduce the analytical workflow, block-level verification, and circuit-level implementation, facilitating independent verification and reuse of the proposed procedure. Although the present work focuses on the Boost topology, the specification-driven formulation is not inherently restricted to this converter. Extension to Buck, Buck–Boost, and other DC–DC topologies, after deriving their corresponding dynamical models and adapting the synthesis equations, represents a natural direction for future work.