Multirate Quasi-Cycle-by-Cycle Control of High-Switching-Frequency Three-Phase Current Source Rectifier

Abstract

High-switching-frequency three-phase current source rectifiers can reduce passive-component size, but their short switching periods impose stringent real-time computational requirements on cycle-by-cycle digital control. This paper proposes a multirate quasi-cycle-by-cycle control scheme that separates computationally intensive control calculations from high-frequency control-input updates. A 10 kHz slow-rate interrupt service routine calculates a sequence of control inputs using the average model and second-order Lagrange interpolation, while a 100 kHz fast-rate interrupt service routine applies these inputs in successive switching cycles. Experimental validation is conducted on a three-phase current source rectifier operating at a switching frequency of 100 kHz and an output power of 409.5 W. With a multirate factor of $N=10$, the proposed scheme increases the effective control-input update rate from 10 kHz to 100 kHz. Compared with the conventional 10 kHz non-cycle-by-cycle control scheme, the proposed scheme reduces the input current total harmonic distortion from 14.50% to 4.02%, corresponding to a relative reduction of 72.28%. It also achieves a lower total harmonic distortion than the conventional 50-kHz control scheme, which produces a value of 6.06%. Accounting for both interrupt levels, the $20.59\mathsf{\mu }\mathrm{s}$ slow-rate ISR and ten $3.30\mathsf{\mu }\mathrm{s}$ fast-rate ISR executions require a total of $53.59\mathsf{\mu }\mathrm{s}$ of processor time during each $100\mathsf{\mu }\mathrm{s}$ slow-rate interval. This corresponds to an overall processor utilization of 53.59% and an overall computational redundancy of 46.41%, compared with only 8.85% redundancy for the conventional 50 kHz implementation. The maximum measured error of the Lagrange-reconstructed phase voltage is 0.2 V. These results demonstrate that the proposed scheme improves input-current quality while preserving sufficient computational margin for cycle-by-cycle control-input updating at a switching frequency of 100 kHz.

1. Introduction

With the increasing pressure of fossil fuel depletion and environmental issues, electric aircraft has become a new trend in the aviation transportation industry [1,2,3,4]. Among various types of electric aircraft, more electric aircraft (MEA) replace pneumatic, hydraulic, and mechanical sources in the secondary system with electrical systems. Due to its advanced characteristics in cost, efficiency, and reliability, it is currently the preferred choice [3,4]. MEA can significantly reduce initial investment and achieve lower emissions, less fuel combustion, and easier maintenance [5,6].

The three-phase rectifier serves as a crucial front-end power conversion stage in MEAs, efficiently converting generator AC power to a regulated DC bus voltage [7,8,9]. Compared to the three-phase voltage source rectifier, the three-phase current source rectifier offers superior operational characteristics, including limited inrush current, wide output voltage regulation range, and inherent short-circuit protection, which establishes the three-phase current source rectifier as a preferred solution for MEA applications that demand high reliability and robust performance [10]. Generally, a high switching frequency (100–200 kHz) is required for aviation three-phase current source rectifiers to enhance power density and reduce current harmonic distortion. Nevertheless, the short interrupt cycle, stemming from high switching frequency operation, poses significant challenges for cycle-by-cycle control of three-phase current source rectifiers, because analog-to-digital (ADC) conversion, digital signal filters for electromagnetic interference noise mitigation, overcurrent/overvoltage protection, and main control scheme execution should be implemented within such a short interrupt cycle [11,12,13].

Beyond more electric aircraft, three-phase converters operating at switching frequencies of 50–100 kHz have considerable potential in high-performance AC–DC power-conversion applications. A higher switching frequency shifts the dominant switching harmonics toward a higher-frequency range, thereby facilitating the reduction of input and output filter size. When accompanied by a sufficiently high control-input update rate, it can also improve input-current tracking, reduce delay-induced current distortion, and enhance DC-link voltage regulation under dynamic load conditions. These characteristics are attractive for the grid-side AC–DC interfaces of photovoltaic and energy-storage systems, DC microgrids, and electric-vehicle fast-charging stations. The heterogeneous and time-varying charging-power profiles reported in [14] further indicate the need for fast and reliable regulation in the AC–DC front-end stage of DC fast chargers. High-frequency conversion is also important in inductive power-transfer systems because it enables compact magnetic couplers and power-conversion stages. However, the associated switching losses, electromagnetic interference, and thermal-management requirements must be carefully considered, as demonstrated by the thermal analysis of a high-frequency inductive power-transfer system in [15]. Therefore, the proposed multirate control principle may provide a useful grid-side control solution for these applications, although further application-specific investigations at higher power levels are required.

Regarding cycle-by-cycle control for three-phase current source rectifiers, extensive literature has been published in recent years due to their high control performance. A passivity-based nonsingular terminal sliding-mode control was proposed in [16]. The control strategy combines the advantages of passivity-based control and nonsingular terminal sliding mode control, achieving resonance suppression, improving dynamic response, reducing chattering associated with traditional sliding mode control, and enhancing system robustness. In [17], a simplified switch short-circuit fault-tolerant scheme for the three-phase current source rectifier was implemented. By paralleling two diodes in each phase without affecting the active switch, an effective fault-tolerant structure is constructed to withstand multiple switch short-circuit faults. A model predictive control strategy is proposed in [18] for multi-objective control, which improves the robustness of the system and the performance of grid current reference tracking. A direct carrier-based modulation scheme was proposed in [19] to reduce the ripple of DC-link current over the whole index range. Although these control schemes can achieve cycle-by-cycle control and improve the control performance of three-phase current source rectifiers in various aspects, their practical adoption is constrained by the high computational burden, which leads to interrupt execution overruns in the short interrupt cycle at high switching frequencies.

Apart from low-switching-frequency cycle-by-cycle control schemes, extensive research has investigated high-switching-frequency control schemes for three-phase current source rectifiers. A reconstructed phase voltages-based power following control under unbalanced input phase voltages was proposed in [20]. By reconstructing the input phase voltage, this technique produces a modulation signal that is more balanced than the input phase voltage. The imbalance in the input current is reduced by regulating it to be proportional to the rebuilt phase voltage. However, the scheme creates three control interrupts to reduce the computational burden, the quickest of which is 100 kHz and cannot match the 200 kHz switching frequency. The authors of [21] investigated the starting inrush current problem of the three-phase current source rectifier, analyzed in detail the mechanism of rectifier starting inrush current generation, and proposed a soft starting scheme and its starting curve design method based on this. However, the control frequency of this scheme is limited to only 50 kHz by the inadequate computing capacity of the microprocessor, leading to incompatibility with the 150 kHz switching frequency. It should be noted that these methods achieve high switching frequencies at the expense of non-cycle-by-cycle control, leading to control input multiplexing in the generation of switching signals and introducing inherent quantization errors and delays that degrade control performance.

In addition to basic power conversion and waveform regulation, modern digitally controlled converters increasingly incorporate online estimation, diagnostic, and resilient-control functions. Lu et al. proposed a differential impedance-detection method using a series–parallel direct-injection soft open point, which distinguishes feeder impedance from the overall grid impedance and further separates transformer and cable contributions through converter-based reactive-current injection without additional external detection equipment [22]. Lin et al. developed a detection-free neural DC-link voltage-correction method based on a dual-stream denoising scheme for cyber-resilient solid-state transformers, demonstrating the role of signal reconstruction and data-driven correction in maintaining reliable converter operation under corrupted voltage information [23]. Although these studies address different converter topologies and control objectives, they demonstrate that emerging power-electronic systems must execute increasingly complex estimation, signal-processing, and resilience-related tasks in addition to conventional feedback control and PWM generation. This trend further motivates digital architectures that provide sufficient computational time while retaining high-rate modulation-input updating.

Multirate control and predictive input generation have previously been investigated to alleviate the computational burden of high-switching-frequency power converters. Multirate finite-control-set model predictive control uses a lifted converter model to predict fast-rate state variables from slow-rate measurements and optimizes a sequence of switching states or voltage vectors within one sampling interval [24,25]. Predictive duty-cycle methods calculate or optimize duty-ratio corrections for specific objectives, such as neutral-point voltage-fluctuation and input-current-harmonic suppression [26]. Digital-delay-compensation methods predict or advance a control command to compensate for calculation and PWM-update delays [27,28,29].

The proposed method addresses a different implementation problem. It establishes a general rate-decoupled framework that separates computationally intensive control-input generation from switching-cycle-scale control-input application. Instead of holding one control input for N switching periods, the slow-rate task generates an online N-element sequence of distinct future control inputs, and the fast-rate task applies one sequence element during each switching period. Unlike multirate finite-control-set predictive control, the implementation presented in this paper does not require switching-state enumeration or online optimization of a converter-state trajectory. Unlike one-step delay compensation, it increases the number of distinct control inputs applied within one slow-rate interval rather than only advancing one command.

The framework is not inherently restricted to a particular converter topology or control algorithm. It can be combined with different converter topologies and control methods, provided that the slow-rate task can generate a sequence of future control inputs and that the fast-rate PWM task can apply them sequentially. In this paper, second-order Lagrange interpolation is used for sequential-input generation, and the framework is combined with indirect current control and SVPWM and experimentally verified on a three-phase current source rectifier.

In the experimental implementation, $f_s=10$ kHz, $N=10$, and $f_f=f_{\mathrm{sw}}=100$ kHz. Thus, $f_f/f_{\mathrm{sw}}=1$, whereas $f_s/f_{\mathrm{sw}}=0.1$. One slow-rate calculation generates ten distinct control inputs that are applied at 10 $\mathsf{\mu }$s intervals. The conventional 10-kHz and 50-kHz implementations hold one input for ten and two switching periods, respectively, and produce input-current THDs of 14.50% and 6.06%. The proposed framework applies one distinct input per switching period and reduces the THD to 4.02%. Considering both interrupt levels, the proposed implementation requires $20.59\mathsf{\mu }\mathrm{s}$ for the slow-rate ISR and $10\times 3.30\mathsf{\mu }\mathrm{s}$ for the ten fast-rate ISR executions within each $100\mathsf{\mu }\mathrm{s}$ slow-rate interval. The resulting overall processor utilization is 53.59%, leaving 46.41% overall computational redundancy, compared with only 8.85% for the conventional 50 kHz implementation.

In view of this, the main contributions of this paper are summarized as follows:

(1)

A multirate quasi-cycle-by-cycle control framework is proposed to decouple the control calculation from the control-input update. The control calculations are performed in the slow-rate interrupt, while distinct control inputs are applied cycle by cycle in the fast-rate interrupt.

(2)

A sequential control-input generation and transfer mechanism is developed. Lagrange interpolation is used to generate N sequential control inputs, which are reliably transferred between the slow-rate and fast-rate interrupts using dual data arrays and timestamp verification.

(3)

The proposed scheme is experimentally validated on a three-phase current source rectifier operating at a switching frequency of 100 kHz. The input-current THD is reduced from 14.50% to 4.02%, while 46.41% overall computational redundancy is maintained after accounting for both the slow- and fast-rate ISR workloads.

In this paper, true cycle-by-cycle feedback control refers to an implementation in which the system states are sampled, the feedback controller is evaluated, and the control input is updated during every switching period. In contrast, the proposed quasi-cycle-by-cycle scheme samples the system states and evaluates the feedback controller at the slow rate, generates N sequential control inputs, and applies one prepared input during each of the subsequent N switching periods. Therefore, “cycle-by-cycle” describes the control-input application rate, whereas “quasi” indicates that no new state feedback is acquired during the fast-rate sequence execution.

The rest of this paper is organized as follows. Section 2 presents the conventional indirect current control scheme and systematically analyzes the limitations of implementing cycle-by-cycle control for three-phase current source rectifiers at high switching frequency. In Section 3, the proposed multirate quasi-cycle-by-cycle control scheme for the three-phase current source rectifier is introduced, and the configuration and digital implementation of fast-rate and slow-rate interrupts are also explained. The experimental results are then presented in Section 4. Section 5 discusses the applicability and limitations of the proposed method, and Section 6 concludes the paper.

2. Conventional Indirect Current Control Scheme and Limitation Under High-Switching-Frequency Operation

This section first provides an overview of conventional indirect current control for three-phase current source rectifiers, highlighting its advantages in aviation applications, such as eliminating AC-side current sensors and simplifying the control structure [30,31]. Next, the limitation imposed by computing power shortage during high-switching-frequency operation in the conventional indirect current control scheme is systematically analyzed. In addition, the performance degradation of non-cycle-by-cycle control at low control frequencies is analyzed.

2.1. Three-Phase Current Source Rectifier Topology and Conventional Indirect Current Control Scheme

The circuit of the three-phase current source rectifier is shown in Figure 1, which consists of an input filter with inductors $L_x$ and capacitors $C_x(x=a,b,c)$, six anti-series connected switch-diode pairs $Q_i$-$D_i(i=1\sim 6)$ with parallel a freewheeling diode D, and an output filter using DC-link inductors $L_P$$L_N$ and capacitor $C_o$ to suppress DC voltage ripple [32]. The three-phase voltages, DC voltage, and DC current are denoted as ($v_a$, $v_b$, $v_c$), $v_o$, and $i_o$, respectively.

The indirect current control scheme in the abc reference frame for three-phase current source rectifiers is illustrated in Figure 2, which includes an outer DC voltage control loop, an inner DC current control loop, and space-vector pulse-width modulation (SVPWM). Proportional-integral (PI) controllers are used to implement both control loops. In this scheme, AC-Side current sensors are not required, eliminating the need for three-phase current sampling.

The control inputs of SVPWM are derived as follows:

$$\left\{\begin{array}{c}{m}_a=v_a{i}_{oPI}\hfill \\ m_b=v_b{i}_{oPI}\hfill \\ m_c=v_c{i}_{oPI}\hfill \end{array}\right.$$

(1)

2.2. Computing Power Shortage Under High-Switching-Frequency Operation

The control inputs are updated using a conventional indirect current control scheme that computes the current inner loop and three-phase voltage signals in real time. These signals are then fed into the SVPWM module to generate switching signals [33,34]. This implementation operates with a fixed control frequency ($f_s=1/T_s$), defining a single-rate framework with a unified timescale $T_s$, as illustrated in Figure 3. The maximum allowable interrupt service routine (ISR) execution time $t_{isr}$ can be defined as

$$t_{isr}=T_s-t_m$$

(2)

where $t_m$ represents the safety margin of the interrupt control cycle (typically 20–30% of $T_s$) reserved to accommodate interrupt jitter.

A detailed breakdown of the estimated execution time for essential digital tasks in a conventional indirect current control scheme implemented on a typical digital signal controller (e.g., the TI C2000 series) is provided in

Table 1. Execution time of digital tasks.

Digital Task	Execution Time
ADC conversion	1.0–1.5 $\mathsf{\mu }$s
Digital filter	0.5–1.0 $\mathsf{\mu }$s
Voltage and current PI controllers	1.0–2.0 $\mathsf{\mu }$s
SVPWM module	1.0–2.0 $\mathsf{\mu }$s
PLL module	1.0–1.5 $\mathsf{\mu }$s
Protection algorithms	1.0–1.5 $\mathsf{\mu }$s

. The execution time for each task varies within a range due to factors such as instruction cycle variability, cache hit rates, and occasional interrupt servicing. Therefore, the total execution time for digital tasks is estimated to fall between 5.5 $\mathsf{\mu }$s to 9.5 $\mathsf{\mu }$s.

The limitation of the conventional single-rate scheme becomes evident at high switching frequencies, where the allowable ISR execution time is severely constrained by the switching period $T_s$. For example, in an aviation three-phase current source rectifier operating at a switching frequency of 100 kHz ($f_{sw}$ = 100 kHz), the total interrupt cycle is only 10 $\mathsf{\mu }$s ($T_s$ = 10 $\mathsf{\mu }$s). After accounting for safety margins, the practical computational redundancy is typically reduced to 8 $\mathsf{\mu }$s or less, as illustrated in Figure 4. However, the total execution time of digital tasks ranges from 5.5 $\mathsf{\mu }$s to 9.5 $\mathsf{\mu }$s, which already threatens to exceed or completely consume the available 8 $\mathsf{\mu }$s redundancy at a 100 kHz switching frequency. This leaves no margin for additional features, advanced control algorithms, or the handling of interrupt jitter. As a result, the system operates with minimal computational redundancy, making it vulnerable to interrupt execution overruns and control logic instability, especially during transient conditions or parametric variations. This fundamental timing conflict renders the conventional single-rate scheme unsuitable for high-switching-frequency aviation rectifiers, which require both high performance and high reliability.

2.3. Performance Degradation of Non-Cycle-by-Cycle Control Under High-Switching-Frequency Operation

To mitigate the risk of interrupt execution overrun in a single-rate framework, a common approach is to reduce the control frequency $f_s$ below the switching frequency $f_{sw}$. This results in a non-cycle-by-cycle control scheme, where the same control input is applied for N consecutive switching cycles, and N = $f_{sw}$/$f_s$. As a result, the control input is updated only once every N switching cycles, as illustrated in Figure 5. This approach introduces an inherent and quantifiable control input update delay $t_d$, which can be expressed as

$$t_d=(N-1)T_{sw}$$

(3)

where $T_{sw}$ represents the switching cycle. The control input applied at any given switching cycle is based on system states sampled up to (N − 1) switching cycles earlier, resulting in a delay of (N − 1)$T_{sw}$. This delay has two main detrimental effects. First, it directly degrades dynamic performance. For instance, when $f_{\mathrm{sw}}=100\mathrm{kHz}$ and $f_s=50\mathrm{kHz}$ ($N=2$), the control input is updated every $T_s=1/f_s=20\mathsf{\mu }\mathrm{s}$. However, according to Equation (3), the maximum additional control-input update delay relative to cycle-by-cycle updating is $t_d=(N-1)T_{\mathrm{sw}}=10\mathsf{\mu }\mathrm{s}$. When $f_s=10\mathrm{kHz}$ ($N=10$), the control-input update interval becomes $100\mathsf{\mu }\mathrm{s}$ and the corresponding maximum additional delay increases to $90\mathsf{\mu }\mathrm{s}$, which can lead to larger voltage deviations and slower recovery during load steps or reference changes. Second, this delay has a negative impact on AC systems by introducing a phase lag in the current control loop, which can be expressed as

$${\varphi }_d=2\pi f_g{t}_d$$

(4)

where $f_g$ is the AC source frequency. In a 400 Hz aviation system, one electrical cycle lasts 2500 $\mathsf{\mu }$s. A 90 $\mathsf{\mu }$s delay (N = 10) corresponds to a phase lag of approximately 13°. This misalignment between the grid voltage and current reference directly increases the total harmonic distortion (THD) of the current, thereby compromising the power quality and stability that the high-performance rectifier is designed to achieve [27,28,29]. For clarity and to differentiate it from the proposed multirate quasi-cycle-by-cycle control scheme, this conventional indirect current control scheme is uniformly referred to as a non-cycle-by-cycle control scheme throughout the paper.

3. Proposed Multirate Quasi-Cycle-by-Cycle Control Scheme

To address the conflict between short interrupts and the control overhead required for high-performance control under high-switching-frequency operation, a multirate quasi-cycle-by-cycle control scheme is proposed. In the proposed scheme, system-state sampling and computationally intensive feedback-control calculations are executed in the slow-rate interrupt, where a sequence of future control inputs is generated. The prepared sequence is subsequently extracted and applied in the fast-rate interrupt, with one sequence element applied during each switching period. No new system-state measurement or feedback-controller evaluation is performed during the fast-rate sequence execution. The overall control diagram is shown in Figure 6. The proposed multirate quasi-cycle-by-cycle control scheme consists of three steps. First, the Lagrange interpolation calculation of a set of sequential control inputs during the slow-rate interrupt is proposed, which uses multiple control inputs to avoid interrupt execution overrun. Next, the process of extracting these sequential control inputs within the fast-rate interrupt is explained to ensure real-time updates of the control input. Finally, the digital implementation of the proposed multirate quasi-cycle-by-cycle control is presented, including detailed descriptions of both the fast-rate and slow-rate interrupt configurations. Additionally, a comprehensive theoretical analysis is conducted to examine the characteristics of truncation error.

3.1. Sequential Control Inputs Calculation in Slow-Rate Interrupt

To prevent interrupt execution overrun at high switching frequencies, most calculations in the proposed scheme are implemented in a slow-rate interrupt, ensuring sufficient interrupt time and avoiding interrupt execution overrun. Specifically, the proposed scheme first calculates N control inputs during each slow-rate interrupt to prepare for the control input updates in subsequent fast-rate interrupts. The parameter N determines the number of sequential modulation inputs applied within each slow-rate interval. It is selected according to the switching frequency and the slow-rate interrupt frequency as

$$N={\displaystyle \frac{f_{sw}}{f_s}},$$

(5)

where $f_{sw}$ represents the switching frequency, and $f_s$ represents the slow-rate interrupt frequency. The fast-rate modulation-input application frequency is therefore $f_f=N{f}_s=f_{sw}$. It should be emphasized that N increases the modulation-input application rate rather than the sampling frequency or the feedback-controller bandwidth. The output voltage/current sampling, PLL calculation, and voltage- and current-loop PI controllers are still executed at the slow-rate frequency $f_s$.

The proposed multirate framework is depicted in Figure 7, where $T_s$ and $T_f$ denote the slow- and fast-rate interrupt periods, respectively. The three-phase voltages $v_{xs}(x=a,b,c)$ are sampled at the slow-rate time points $T_s^{k-1}$, $T_s^k$, and $T_s^{k+1}$, with a sampling frequency of $f_s$. In the slow-rate interrupt period $T_s^{k-1}$ to $T_s^k$, a set of sequential interpolated voltages $v_{xf}^{N|K}(x=a,b,c)$ through Lagrange interpolation, using in the next slow-rate interrupt period at $T_f^0$, $T_f^1$, …, $T_f^N$. Therefore, the frequency relationship follows $T_s=N{T}_f$ (equivalently expressed as $f_f=N{f}_s$) through uniform partitioning of the slow-rate period. Each slow-rate interrupt period initializes with the three-phase voltage values at $T_f^0$ as the starting point.

$$v_{xf}^{0|K}=v_{xs}^K,$$

(6)

where $K,(K=1,2,\dots )$ represents the Kth sampling point.

The phase angle values ${\theta }_{xs}^{K-1}$, ${\theta }_{xs}^K$, ${\theta }_{xs}^{K+1}$ corresponding to the phase voltages at each sampling point are calculated using a phase-locked loop. Subsequently, the corresponding angle for which the interpolation voltage point can be calculated as

$${\theta }_{xf}^{i|K}={\theta }_{xs}^K+i{\displaystyle \frac{{\theta }_{xs}^{K+1}-{\theta }_{xs}^K}{N}},$$

(7)

where $i|K,(i=0,1,2,\dots ,N)$ represents the control point during the slow-rate interrupt from $T_s^K$ to $T_s^{K+1}$.

These angle values are then processed using the standard second-order Lagrange polynomial interpolation formulation [35,36]. The corresponding Lagrange basis functions are expressed as

$$l^{K-1}\left(\theta \right)={\displaystyle \frac{[{\theta }_{xf}^{i|K}-{\theta }_{xs}^K][{\theta }_{xf}^{i|K}-{\theta }_{xs}^{K+1}]}{[{\theta }_{xs}^{K-1}-{\theta }_{xs}^K][{\theta }_{xs}^{K-1}-{\theta }_{xs}^{K+1}]}}$$

(8)

$$l^K\left(\theta \right)={\displaystyle \frac{[{\theta }_{xf}^{i|K}-{\theta }_{xs}^{K-1}][{\theta }_{xf}^{i|K}-{\theta }_{xs}^{K+1}]}{[{\theta }_{xs}^K-{\theta }_{xs}^{K-1}][{\theta }_{xs}^K-{\theta }_{xs}^{K+1}]}}$$

(9)

$$l^{K+1}\left(\theta \right)={\displaystyle \frac{[{\theta }_{xf}^{i|K}-{\theta }_{xs}^{K-1}][{\theta }_{xf}^{i|K}-{\theta }_{xs}^K]}{[{\theta }_{xs}^{K+1}-{\theta }_{xs}^{K-1}][{\theta }_{xs}^{K+1}-{\theta }_{xs}^K]}}$$

(10)

The sequential three-phase voltage inputs are subsequently reconstructed from the second-order Lagrange interpolation polynomial as [35,36]

$$\begin{array}{cc}\hfill v_{xf}^{i|K}& =v_{xs}^{K-1}{l}^{K-1}\left(\theta \right)\hfill \\ \hfill & +v_{xs}^K{l}^K\left(\theta \right)+v_{xs}^{K+1}{l}^{K+1}\left(\theta \right)\hfill \end{array}$$

(11)

Three adjacent voltage samples are employed because they constitute the minimum data set required for second-order Lagrange interpolation. This formulation captures the local curvature of the phase voltage while requiring fewer arithmetic operations and stored samples than higher-order interpolation. It also avoids the increased noise sensitivity and numerical oscillation that may accompany a higher interpolation order. Therefore, the three-point formulation represents a compromise among reconstruction accuracy, computational burden, memory usage, and real-time implementation capability. Its adequacy assumes that the phase voltage and the PLL-estimated phase angle vary smoothly within the local interpolation interval.

The interpolation does not require the input frequency to remain exactly constant. The interpolation nodes ${\theta }_{xs}^{K-1}$, ${\theta }_{xs}^K$, and ${\theta }_{xs}^{K+1}$ are obtained from the PLL, and the fast-rate angles in (7) are calculated using the local angular increment ${\theta }_{xs}^{K+1}-{\theta }_{xs}^K$. Consequently, gradual frequency variations are reflected in the node spacing. In addition, the three phase voltages are interpolated independently; hence, unequal phase amplitudes under unbalanced conditions do not invalidate the interpolation. However, rapid frequency transients, large PLL errors, or severe voltage distortion can increase the reconstruction error. In particular, voltage distortion increases the local third-derivative bound $M_3$ in the Lagrange remainder. Under such conditions, a higher slow-rate sampling frequency, adaptive interpolation, or improved phase estimation may be required.

The influence of sampled-voltage error can be evaluated by representing each measured sample as $v_{xs}^j+n_x^j$. The corresponding error in the interpolated voltage is

$$e_{n,x}^{i|K}={\displaystyle \sum _{j=K-1}^{K+1}}{l}_j\left({\theta }_{xf}^{i|K}\right)n_x^j$$

(12)

If $\left|n_x^j\right|\le {\epsilon }_n$, the error satisfies

$$\left|e_{n,x}^{i|K}\right|\le {\mathrm{\Lambda }}_i{\epsilon }_n,{\mathrm{\Lambda }}_i={\displaystyle \sum _{j=K-1}^{K+1}}\left|l_j\left({\theta }_{xf}^{i|K}\right)\right|$$

(13)

For approximately uniformly spaced angular nodes and ${\theta }_{xf}^{i|K}\in [{\theta }_{xs}^K,{\theta }_{xs}^{K+1}]$, ${\mathrm{\Lambda }}_i\le 1.25$. Therefore, bounded measurement noise is amplified by no more than approximately 25% under this condition. ADC quantization can be incorporated by replacing ${\epsilon }_n$ with ${\epsilon }_n+q_{\mathrm{ADC}}/2$, where $q_{\mathrm{ADC}}$ is the ADC voltage resolution.

For a small PLL phase error $\delta \theta$, the resulting voltage error can be approximated and bounded as

$$e_{\mathrm{PLL},x}^{i|K}\approx {\displaystyle \frac{d{v}_x}{d\theta }}\delta \theta ,\left|e_{\mathrm{PLL},x}^{i|K}\right|\le M_1\left|\delta \theta \right|,M_1=\underset{\theta \in I_K}{\max }\left|{\displaystyle \frac{d{v}_x}{d\theta }}\right|$$

(14)

When the phase error is primarily caused by a PLL delay ${\tau }_{\mathrm{PLL}}$, $\delta \theta \approx {\omega }_g{\tau }_{\mathrm{PLL}}$, and hence $\left|e_{\mathrm{PLL},x}^{i|K}\right|\le M_1{\omega }_g{\tau }_{\mathrm{PLL}}$. This relationship indicates that the effect of the PLL delay increases with the input angular frequency, the PLL delay, and the local voltage slope.

When the converter losses are neglected, the instantaneous input and output powers can be related using the power-balance and conductance-based current-shaping principle adopted for three-phase current-source rectifiers [20,34]. Therefore

$$\begin{array}{c}\hfill p_{in}={\displaystyle \sum _{x=a,b,c}}{\left(v_{xf}^{i|K}\right)}^{2}G=v_o{i}_o=p_{out},\end{array}$$

(15)

where G is the conductance of each phase on the input side.

From (15), the given conductance can be expressed as

$$\begin{array}{c}\hfill G^{\ast }={\displaystyle \frac{P_{out}^{\ast }}{{\displaystyle \sum _{x=a,b,c}}{\left(v_{xf}^{i|K}\right)}^2}}\end{array}$$

(16)

Therefore, the reference of the DC-side output current can be formulated as

$$\begin{array}{c}\hfill i_o^{\ast }={\displaystyle \frac{{\displaystyle \sum _{x=a,b,c}}{\left(v_{xf}^{i|K}\right)}^2{G}^{\ast }}{v_o}}\end{array}$$

(17)

For a converter with an efficiency of $\eta$, the loss-compensated equivalent input conductance is

$$G_{\eta }^{\ast }={\displaystyle \frac{P_{\mathrm{out}}^{\ast }}{\eta {\sum }_{x=a,b,c}{\left(v_{xf}^{i|K}\right)}^2}}={\displaystyle \frac{G^{\ast }}{\eta }}.$$

(18)

Therefore, the nominal lossless model underestimates the required input conductance by $1-\eta$ relative to the loss-compensated value, while the required correction relative to the nominal conductance is $1/\eta -1$. For example, assumed efficiencies of 90%, 94%, and 98% correspond to conductance underestimations of 10%, 6%, and 2%, respectively. Over the investigated output-power range of 136.5–409.5 W, the corresponding loss ranges are 15.17–45.50 W, 8.71–26.14 W, and 2.79–8.36 W. These efficiency values are used only as sensitivity parameters and are not measured efficiencies of the experimental prototype.

Substituting Equation (16) into Equation (17) gives $i_o^{\ast }=P_{\mathrm{out}}^{\ast }/v_o$. Thus, when the same reconstructed phase-voltage values are used consistently in the two equations, the voltage-squared term cancels algebraically. Converter losses primarily increase the required input conductance and input-current amplitude. Moreover, the outer DC-voltage PI controller contains integral action and therefore compensates a constant loss-related power mismatch in steady state, provided that the controller remains stable and unsaturated. The lossless assumption consequently introduces a feedforward conductance bias and additional feedback correction rather than an uncompensated steady-state DC-voltage error.

Moreover, the output of the current loop is $i_{oPIf}^{i|K}$ at different $i|K$. The control inputs, which are used to generate gating signals via SVPWM to control the switches of the three-phase current source rectifier, are expressed as

$$\left\{\begin{array}{c}{m}_{x1}=v_{xf}^{1|K}{i}_{oPIf}^{1|K}\hfill \\ m_{x2}=v_{xf}^{2|K}{i}_{oPIf}^{2|K}\hfill \\ \dots \hfill \\ m_{xi}=v_{xf}^{i|K}{i}_{oPIf}^{i|K}\hfill \\ \dots \hfill \\ m_{xN}=v_{xf}^{N|K}{i}_{oPIf}^{N|K}\hfill \end{array}\right.$$

(19)

In this way, a set of control inputs $m_{x1}$, $m_{x2}$,…,$m_{xi}$,…,$m_{xN}$ can be obtained in each slow-rate interrupt and placed in a specific array, waiting for the sequential extraction of subsequent fast-rate interrupts.

3.2. Sequential Control Inputs Extraction Cycle-by-Cycle in Fast-Rate Interrupt

To provide switching-cycle-scale control-input updating, one element of the N-element sequence generated by the slow-rate task is extracted and applied whenever a fast-rate interrupt occurs. The sequence is executed without acquiring new system-state measurements during the current slow-rate interval. Therefore, the fast-rate task provides cycle-by-cycle input application rather than cycle-by-cycle feedback recalculation. As shown in Figure 8, to ensure reliable extraction of control inputs from slow-rate interrupts during fast-rate interrupts and facilitate their real-time update, the proposed scheme employs a dual-array architecture with timestamp verification for data synchronization. This architecture effectively bridges the timing gap between different interrupt frequencies. More specifically, one array is designated as the active buffer and is read only by the fast-rate interrupt, whereas the other is designated as the inactive buffer and is written only by the slow-rate interrupt. After all $3N$ modulation inputs have been generated, the slow-rate routine updates the timestamp and validity flag and changes the active-buffer index within a short protected operation. At the beginning of each fast-rate interrupt, the active-buffer index is read once and retained throughout the current ISR execution. Therefore, the fast-rate interrupt always extracts data from one completely updated buffer and cannot access the buffer being written by the slow-rate interrupt.

Additionally, the scheme incorporates error-prevention and fault-tolerance mechanisms to enhance system reliability. Upon initialization, the dual-array architecture is populated with default values, and the timestamp is reset to prevent the accidental use of uninitialized data. In the event of data corruption or timing violations (e.g., exceeding two slow-rate interrupt cycles), the scheme automatically reverts to the last valid dataset, increments an error counter, and issues a system alarm. This ensures continuous operation even in the presence of transient faults, thereby improving robustness in real-time control applications. For 32-bit floating-point data, the memory required by the two three-phase modulation-input buffers is $2\times 3\times N\times 4$ bytes. Therefore, the buffer-data memory is 240 bytes for $N=10$, excluding the small additional memory required by the indices, validity flags, timestamps, and error counter.

3.3. Fast-Rate/Slow-Rate Interrupt Configuration and Digital Realization

To achieve enhanced control frequency and cycle-by-cycle control performance, the digital implementation of the proposed scheme employs a multirate framework that decouples control into fast- and slow-rate parts, implemented in nested interrupts. The interrupt execution flowchart of the proposed scheme implemented in digital is shown in Figure 9. The slow-rate interrupt handles all computationally intensive tasks, including output voltage/current sampling, input phase-voltage sampling, phase-angle derivation, sequential control-input calculations, and output regulation. The fast-rate interrupt is singularly dedicated to generating switch signals through SVPWM. Moreover, the digital implementation ensures that fast-rate interrupt modulation calculations are fully completed before the slow-rate interrupt is activated, with enforced isolation via minimum timing margins.

The controller is implemented on a TMS320F28377S DSP(Texas Instruments, Dallas, TX, USA) operating at a system clock frequency of 200 MHz. ADC sampling is initiated at the beginning of each slow-rate interval $T_s^K$. The fast-rate interrupt is synchronized with the PWM carrier and is assigned a higher priority than the slow-rate interrupt. At each fast-rate instant $T_f^{i|K}$, the extracted modulation inputs are written to the PWM shadow registers and transferred to the active registers at the immediately following predefined PWM carrier boundary. Therefore, the duty ratios are updated only at switching-period boundaries.

As shown in Figure 10, in contrast to conventional single-rate implementations, the multirate framework necessitates elevating the carrier frequency to match the control frequency $f_f$ to accommodate multiple modulation signals generated within each slow-rate interrupt. During the slow-rate interrupt, high-priority fast-rate interrupts can preempt operations to generate multiple switching signals. Upon completion of the fast-rate interrupt service routine, execution automatically returns to the preemption point in the slow-rate interrupt handler.

The measured slow-rate ISR execution time reported in this paper represents the active processor time consumed by the slow-rate task and excludes the intervals during which its execution is suspended by the higher-priority fast-rate ISR. Therefore, the slow-rate execution time cannot be used alone to represent the overall processor utilization. The complete processor workload must include both the slow-rate ISR and all fast-rate ISR executions occurring within the same slow-rate interval.

Consequently, a distinct modulation input and the corresponding switching signals are applied during every fast-rate period. This increases the modulation-input application rate from $f_s$ to $f_f=N{f}_s$ without changing the slow-rate sampling, PLL, or PI-controller execution frequency.

In the experimental implementation, $f_s=10$ kHz, $N=10$, and $f_f=f_{\mathrm{sw}}=100$ kHz. Therefore, new voltage and current measurements are acquired and the PLL and PI controllers are evaluated once every 100 $\mathsf{\mu }$s, whereas a distinct predicted modulation input is applied once every 10 $\mathsf{\mu }$s. The fast-rate interrupt does not acquire new feedback information or reevaluate the PI controllers. Consequently, the proposed method reduces the modulation-input holding error within each slow-rate interval but does not increase the closed-loop feedback bandwidth by a factor of N.

3.4. Truncation Error Analysis

The second-order Lagrange interpolation polynomial provides an approximation of the actual phase-voltage function at the fast-rate instants. Let $v_x\left(\theta \right)$ denote the actual voltage of phase x, expressed as a function of the phase angle $\theta$, and let $v_{xf}^{i|K}$ denote its interpolated value at the ith fast-rate instant within the Kth slow-rate interval. The corresponding interpolation error is defined as

$$R_2\left({\theta }_{xf}^{i|K}\right)=v_x\left({\theta }_{xf}^{i|K}\right)-v_{xf}^{i|K},i=0,1,\dots ,N.$$

(20)

According to the classical remainder theorem for second-order Lagrange polynomial interpolation [35,36], there exists an intermediate point $\xi$ within the smallest interval containing the three interpolation nodes and the evaluation point such that the interpolation remainder is determined by the third derivative of the phase-voltage function. Define $M_3={\max }_{\theta \in I_K}\left|d^3{v}_x\left(\theta \right)/d{\theta }^3\right|$, where $I_K$ denotes the interpolation interval. The interpolation-error bound can then be expressed as

$$\begin{array}{cc}\hfill \left|R_2\left({\theta }_{xf}^{i|K}\right)\right|\le & {\displaystyle \frac{M_3}{6}}\left|\left({\theta }_{xf}^{i|K}-{\theta }_{xs}^{K-1}\right)\left({\theta }_{xf}^{i|K}-{\theta }_{xs}^K\right)\right.\hfill \\ \hfill & \left.\times \left({\theta }_{xf}^{i|K}-{\theta }_{xs}^{K+1}\right)\right|.\hfill \end{array}$$

(21)

In Equation (21), $M_3$ has the unit $\mathrm{V}{\mathrm{rad}}^{-3}$, while the product of the three phase-angle differences has the unit ${\mathrm{rad}}^3$. Therefore, the resulting interpolation-error bound has the unit V, which confirms the dimensional consistency of the expression. The bound becomes zero at the interpolation nodes and is nonzero only at the intermediate fast-rate points.

It should be emphasized that Equations (20) and (21) describe the truncation error associated with approximating the actual phase-voltage function using a second-order interpolation polynomial. Round-off, coefficient quantization, ADC quantization, and other finite-word-length effects constitute additional numerical implementation errors and are not included in the classical interpolation remainder. These numerical effects should therefore be distinguished from the interpolation truncation error [37].

The derived bound quantifies the phase-voltage interpolation error, whereas the resulting duty-ratio error depends on its propagation through the subsequent control and modulation calculations. To evaluate its propagation through Equations (16)–(19), define the phase-voltage interpolation error as $e_x^{i|K}=v_{xf}^{i|K}-v_x\left({\theta }_{xf}^{i|K}\right)$, with $|e_x^{i|K}| \le {\epsilon }_v$. Furthermore, define $S_i={\sum }_{x=a,b,c}{v}_x^2\left({\theta }_{xf}^{i|K}\right)$ and ${\widehat{S}}_i={\sum }_{x=a,b,c}{\left(v_{xf}^{i|K}\right)}^2=S_i+\mathrm{\Delta }{S}_i$. The perturbation of the squared-voltage sum satisfies

$$\mathrm{\Delta }{S}_i=2\sum _{x=a,b,c}{v}_x\left({\theta }_{xf}^{i|K}\right)e_x^{i|K}+\sum _{x=a,b,c}{\left(e_x^{i|K}\right)}^2,\left|\mathrm{\Delta }{S}_i\right|\le 2{\epsilon }_v\sqrt{3S_i}+3{\epsilon }_v^2.$$

For the balanced 115 V RMS input used in the experiment, $S_i=3v_{\mathrm{rms}}^2=\mathrm{39,675}{\mathrm{V}}^2$. Using the maximum measured interpolation error ${\epsilon }_v=0.2\mathrm{V}$ gives $|\mathrm{\Delta }{S}_i|/S_i\le 0.348\%$. If $G_0^{\ast }=P_{\mathrm{out}}^{\ast }/S_i$ and ${\widehat{G}}^{\ast }=P_{\mathrm{out}}^{\ast }/{\widehat{S}}_i$, the corresponding conductance error satisfies

$${\displaystyle \frac{|{\widehat{G}}^{\ast }-G_0^{\ast }|}{G_0^{\ast }}}={\displaystyle \frac{|\mathrm{\Delta }{S}_i|}{|S_i+\mathrm{\Delta }{S}_i|}}\le 0.349\%.$$

The DC-current reference does not have the same sensitivity because the same reconstructed squared-voltage sum is used in Equations (16) and (17). Consequently,

$${\widehat{i}}_o^{\ast }={\displaystyle \frac{{\widehat{S}}_i{\widehat{G}}^{\ast }}{v_o}}={\displaystyle \frac{P_{\mathrm{out}}^{\ast }}{v_o}},$$

and the interpolation error does not directly introduce a steady-state bias into $i_o^{\ast }$. For the modulation input, a local sensitivity analysis with a fixed current-controller output gives

$$\mathrm{\Delta }{m}_{xi}=e_x^{i|K}{i}_{oPIf}^{i|K},|\mathrm{\Delta }{m}_{xi}|\le {\epsilon }_v\left|i_{oPIf}^{i|K}\right|.$$

Since the phase-voltage peak is $\sqrt{2}{v}_{\mathrm{rms}}=162.63\mathrm{V}$, the measured 0.2 V error corresponds to 0.123% of the phase-voltage peak. The conservative normalized error of the complete three-phase modulation vector is no greater than 0.174%. Within a fixed SVPWM sector, the duty ratios are piecewise-linear functions of the modulation vector; therefore, the resulting duty-ratio perturbation is of the same small order. However, its exact instantaneous value also depends on the active sector, modulation index, and current-controller output, and a universal duty-ratio bound cannot be obtained from the voltage error alone.

4. Experimental Verification

To verify the effectiveness of the proposed multirate quasi-cycle-by-cycle control scheme, an experimental prototype of a 400 W three-phase current source rectifier has been designed and built as shown in Figure 11, whose detailed parameters are listed in

Table 2. System parameters.

Parameter	Value
AC voltage (RMS), $v_{\mathrm{rms}}$	115 V
AC input frequency, $f_{\mathrm{in}}$	400 Hz
Output voltage, $v_o$	200 V
Input inductors, $L_a$, $L_b$, and $L_c$	100 $\mathsf{\mu }$H
Input capacitors, $C_a$, $C_b$, and $C_c$	620 nF
Output inductors, $L_P$ and $L_N$	660 $\mathsf{\mu }$H
Output capacitor, $C_o$	880 nF
Switching frequency, $f_{sw}$	100 kHz

.

The parameters were selected to construct a representative scaled laboratory prototype for more-electric-aircraft power-conversion applications. The 115-V/400-Hz AC input represents a typical aircraft AC supply, whereas the 200-V DC output and approximately 400-W power level were selected according to the ratings of the laboratory source, semiconductor devices, DC load, and measurement equipment. The switching frequency was set to 100 kHz to evaluate the proposed method under a short switching period of 10 $\mathsf{\mu }$s. Accordingly, the slow-rate and fast-rate interrupt frequencies were set to 10 kHz and 100 kHz, respectively, resulting in a sequence length of $N=10$. The input- and DC-side filter parameters were selected to attenuate the switching ripple and ensure stable operation under the investigated condition.

These parameters are representative experimental values rather than mandatory values of the proposed method. The multirate framework is not inherently restricted to the investigated voltage, power, or input-frequency levels. However, the fast-rate interrupt must be completed within each switching period, while the slow-rate calculation and sequence preparation must be completed before the next data transfer. Moreover, the slow-rate frequency and sequence length must provide sufficient interpolation accuracy. Therefore, extending the proposed method to higher power levels or more severe operating conditions requires appropriate redesign of the power stage, passive components, protection circuits, and control parameters.

In the prototype, metal–oxide–semiconductor field-effect transistors (MOSFETs) STD18N65M5 (STMicroelectronics, Plan-les-Ouates, Switzerland) are used. The DSP TMS320F28377S is used to implement the proposed scheme.

Two non-cycle-by-cycle control schemes are designed for comparison: one with an interrupt frequency set at 10 kHz (equal to the slow-rate interrupt frequency in the proposed scheme) and the other at 50 kHz (the fastest frequency without interrupt execution overrun). In the proposed scheme, the slow-rate interrupt frequency is set to 10 kHz, and the fast-rate interrupt frequency is set to 100 kHz. The same proportional and integral gains are intentionally used for the voltage and current controllers in all three experimental cases, and the PI gains are not independently retuned for each implementation. In the proposed scheme, both PI controllers are evaluated in the 10 kHz slow-rate interrupt, which is identical to the PI-controller execution rate of the 10 kHz non-cycle-by-cycle baseline. Only the sequential modulation-input application rate is increased to 100 kHz through the fast-rate interrupt. Therefore, the comparison between these two cases keeps the PI gains, PI execution rate, switching frequency, power stage, and operating conditions unchanged, thereby isolating the influence of the control-input updating mechanism.

The 50 kHz non-cycle-by-cycle scheme represents the highest conventional control frequency that can be executed on the adopted DSP without interrupt execution overrun. It is included as a supplementary reference for evaluating the effects of a shorter control-input holding interval and a reduced computational margin. The reported results therefore constitute a matched-controller comparison and are not intended to claim superiority over every independently retuned conventional controller.

4.1. Steady-State Performance

To validate the steady-state performance of the proposed scheme, experimental tests were first conducted to verify the stable operation of the three-phase current source rectifier. The comparative analysis is conducted at the same switching frequency ($f_{sw}=100$ kHz) to achieve a fair comparison. In the test, the three-phase current source rectifier operates at an output power ($P_o=409.5$ W) with an AC input frequency ($f_{in}=400$ Hz). The steady-state performance of the three-phase current-source rectifier under three control schemes is shown in Figure 12. From top to bottom, the waveform is DC-link output voltage $v_o$, phase-a grid voltage $v_a$, phase-a grid current $i_a$, and three-phase grid currents $i_{abc}$. As shown in Figure 12, all three control schemes exhibit high sine values for the three-phase input current and a stable 200 V output voltage, while maintaining unity power factor. However, the proposed scheme provides improved input-current quality and lower output-voltage ripple because it replaces one control input held for multiple switching periods with a sequence of distinct control inputs applied at the switching frequency. This result demonstrates the benefit of switching-cycle-scale control-input updating rather than equivalence to true cycle-by-cycle feedback control.

Furthermore, the fast Fourier transform (FFT) spectrum analysis of the phase-a current is shown in Figure 13. The current waveform analysis reveals that non-cycle-by-cycle control ($f_s=10$ kHz) exhibits poor performance with significant current ripple and high total harmonic distortion (THD) of 14.5%. As the control frequency increases to ($f_s=50$ kHz), THD drops to 6.06%. In contrast, the proposed scheme ($f_s=10$ kHz, $N=10$) achieves THD of 4.02%, representing a 72.27% improvement compared to the non-cycle-by-cycle control scheme benchmark ($f_s=10$ kHz).

4.2. Dynamic-State Performance

In addition to the steady-state performance verification discussed earlier, the dynamic-state performance of the proposed scheme is tested to verify its closed-loop regulation capabilities under DC-link voltage reference variations and DC-link load switching.

(1) DC-link voltage reference variation: The DC-link load is assumed to be a constant value, and the process of changing the DC-link voltage reference from 150 V to 200 V is shown in Figure 14a. From top to bottom, the waveform is the DC-link output voltage $v_o$, three-phase grid currents $i_{abc}$. The proposed scheme reduces the current ripple without affecting the dynamic performance of non-cycle-by-cycle control schemes. As shown in the upper part of Figure 15, the proposed scheme produces a smoother transient waveform and lower output-voltage ripple by reducing the modulation-input holding error. However, the response to newly sampled feedback information is still determined by the 10 kHz slow-rate control loop.

(2) DC-link Load Switching: Furthermore, the DC-link voltage reference is assumed to be a constant value, and the dynamic test with load switching from 136.5 W to 409.5 W is shown in Figure 14b and the bottom of Figure 15. It can be observed that all schemes exhibit a rapid response to the external disturbance. Compared with the non-cycle-by-cycle control schemes, the proposed scheme produces fewer spikes in the three-phase input currents and a smoother output-voltage waveform during the tested load transient. These improvements result from the switching-cycle-scale updating of the modulation input rather than an N-fold increase in the feedback-controller bandwidth.

As summarized in

Table 3. Quantitative comparison of the dynamic experimental results.

Test	Control Scheme	${\mathit{t}}_{\mathbf{s}/\mathbf{r}}$ (ms)	$\mathbf{\Delta }{\mathit{V}}_{\mathbf{under}}$ (V)	$\mathbf{\Delta }{\mathit{v}}_{\mathit{o},\mathbf{pp}}$ (V)	${\mathit{I}}_{\mathbf{pk}}$ (A)
	Non-cycle-by-cycle scheme ($f_s=10$ kHz)	19.13	5.6	18.6	2.25
Reference step	Non-cycle-by-cycle scheme ($f_s=50$ kHz)	18.97	5.8	13.9	1.93
	Proposed scheme ($f_s=10$ kHz, $N=10$)	18.85	4.7	9.4	1.87
	Non-cycle-by-cycle scheme ($f_s=10$ kHz)	16.28	62.3	19.1	2.23
Load step	Non-cycle-by-cycle scheme ($f_s=50$ kHz)	17.34	48.7	14.3	1.99
	Proposed scheme ($f_s=10$ kHz, $N=10$)	14.56	39.8	10.1	1.92

, the proposed scheme achieves a reference-step settling time of 18.85 ms, comparable to 19.13 ms and 18.97 ms for the conventional 10 kHz and 50 kHz schemes, respectively, while reducing the voltage undershoot, output-voltage ripple, and peak input current to 4.7 V, 9.4 V, and 1.87 A. Under the load step, the recovery time decreases to 14.56 ms, corresponding to reductions of 10.57% and 16.03% relative to the two conventional schemes. The voltage undershoot decreases from 62.3 V and 48.7 V to 39.8 V, while the output-voltage ripple and peak input current decrease to 10.1 V and 1.92 A. These results demonstrate comparable reference-tracking speed, improved voltage and current characteristics, and faster recovery from the investigated load disturbance.

In conclusion, the proposed scheme reduces the current spikes, output-voltage ripple, and control-input holding delay under the tested transient conditions by applying a distinct modulation input during every switching cycle. Nevertheless, the sampling, PLL, and PI-controller execution frequencies remain at 10 kHz. Therefore, the response to newly sampled disturbances and reference changes is still limited by the slow-rate feedback loop, and the proposed scheme should not be interpreted as increasing the closed-loop bandwidth by a factor of N.

4.3. Truncation Error Analysis

To validate the accuracy of the reconstructed phase voltage by Lagrange interpolation under the proposed scheme, the truncation error of the Lagrange-interpolated phase-a voltage is shown in Figure 16. From top to bottom, the waveform is the measured and filtered phase-a voltage, the reconstructed phase-a voltage by Lagrange interpolation, and the truncation error of the Lagrange-interpolated phase-a voltage. As shown in Figure 16, the maximum observed interpolation error of the phase-a voltage is approximately 0.2 V. Relative to the 162.63 V phase-voltage peak, this error is 0.123%. According to the propagation analysis in Section 3.4, conservatively applying the same error bound to all three phases results in a maximum squared-voltage-sum error of 0.348%, an equivalent-conductance error of less than 0.349%, and a normalized three-phase modulation-vector error of less than 0.174%. The DC-current reference $i_o^{\ast }$ is not directly biased because the reconstructed squared-voltage sum cancels between Equations (16) and (17). These results indicate that the interpolation process introduces only a small additional perturbation into the sequential modulation inputs. The measured current THD cannot be derived directly from the voltage interpolation error because it also depends on the input filter, PWM mapping, controller dynamics, and converter nonidealities. Therefore, the THD improvement reported in

Table 4. Comparison of overall processor utilization and control performance.

Control Scheme	Switching Frequency (kHz)	THD (%)	ISR Execution Arrangement	Overall Utilization (%)	Overall Redundancy (%)
Non-cycle-by-cycle scheme ($f_s=10\mathrm{kHz}$)	100	14.50	$18.23\mathsf{\mu }\mathrm{s}$ per ISR at $10\mathrm{kHz}$	18.23	81.77
Non-cycle-by-cycle scheme ($f_s=50\mathrm{kHz}$)	100	6.06	$18.23\mathsf{\mu }\mathrm{s}$ per ISR at $50\mathrm{kHz}$	91.15	8.85
Proposed scheme ($f_s=10\mathrm{kHz}$, $N=10$)	100	4.02	$20.59\mathsf{\mu }\mathrm{s}$ at $10\mathrm{kHz}$ plus $3.30\mathsf{\mu }\mathrm{s}$ at $100\mathrm{kHz}$	53.59	46.41

is attributed primarily to updating the modulation input in every switching cycle, while the small interpolation error confirms that the high-rate input sequence does not introduce a significant additional modulation disturbance.

4.4. Computational Redundancy Comparison

To evaluate the complete computational burden of the proposed multirate implementation, the execution times of both the slow-rate and fast-rate ISRs must be considered. The overall processor utilization within one slow-rate interval is defined as

$$U_{\mathrm{total}}={\displaystyle \frac{t_{\mathrm{isr},\mathrm{s}}+N{t}_{\mathrm{isr},\mathrm{f}}}{T_s}}\times 100\%,$$

(22)

where $t_{\mathrm{isr},\mathrm{s}}$ and $t_{\mathrm{isr},\mathrm{f}}$ denote the active processor execution times of one slow-rate ISR and one fast-rate ISR, respectively. The overall computational redundancy is then defined as

$${\rho }_{\mathrm{total}}=100\%-U_{\mathrm{total}}.$$

(23)

For the proposed scheme, $T_s=100\mathsf{\mu }\mathrm{s}$, $N=10$, $t_{\mathrm{isr},\mathrm{s}}=20.59\mathsf{\mu }\mathrm{s}$, and $t_{\mathrm{isr},\mathrm{f}}=3.30\mathsf{\mu }\mathrm{s}$. Because ten fast-rate ISR executions occur within each slow-rate interval, the total processor time required by the two interrupt levels is

$$t_{\mathrm{CPU}}=t_{\mathrm{isr},\mathrm{s}}+N{t}_{\mathrm{isr},\mathrm{f}}=20.59+10\times 3.30=53.59\mathsf{\mu }\mathrm{s}.$$

(24)

Accordingly, the overall processor utilization is 53.59%, and the overall computational redundancy is 46.41%. The previously reported value of 79.41% represents only the slow-rate-task timing margin when the fast-rate ISR workload is not included; therefore, it is not used as the overall computational redundancy of the complete multirate implementation. As illustrated in Figure 17, the processor utilization of the proposed scheme consists of 20.59% slow-rate ISR utilization and 33.00% accumulated fast-rate ISR utilization, leaving 46.41% overall computational redundancy.

For the conventional scheme operating at 10 kHz, the measured ISR execution time is $18.23\mathsf{\mu }\mathrm{s}$ within a $100\mathsf{\mu }\mathrm{s}$ interrupt period, resulting in a processor utilization of 18.23% and a computational redundancy of 81.77%. When the conventional interrupt frequency is increased to 50 kHz, the same ISR is executed once every $20\mathsf{\mu }\mathrm{s}$. Consequently, its processor utilization increases to 91.15%, leaving only 8.85% computational redundancy. The overall processor utilization, computational redundancy, and input-current THD of the three schemes are summarized in Table 4.

All three control schemes in Table 4 were experimentally evaluated using the same converter prototype, switching frequency of 100 kHz, input and output operating conditions, and voltage- and current-loop PI parameters. For the 10-kHz non-cycle-by-cycle scheme, the measured ISR execution time is 18.23 $\mathsf{\mu }$s within a 100 $\mathsf{\mu }$s interrupt period, leaving 81.77 $\mathsf{\mu }$s of available computational time. However, because the same control input is held for ten consecutive switching cycles, the input-current THD reaches 14.50%. Increasing the conventional control frequency to 50 kHz reduces the THD to 6.06%, but the interrupt period decreases to only 20 $\mathsf{\mu }$s. Since the ISR execution time remains 18.23 $\mathsf{\mu }$s, only 1.77 $\mathsf{\mu }$s of available computational time remains, corresponding to a computational redundancy of 8.85%.

For the proposed scheme, the computationally intensive operations are performed in the 10-kHz slow-rate interrupt, while ten distinct control inputs are sequentially applied at the 100-kHz switching frequency. The measured slow-rate ISR execution time is 20.59 $\mathsf{\mu }$s within a 100 $\mathsf{\mu }$s slow-rate period, leaving 79.41 $\mathsf{\mu }$s of available computational time. Compared with the 10-kHz non-cycle-by-cycle scheme, the proposed scheme increases the slow-rate ISR execution time by only 2.36 $\mathsf{\mu }$s, while reducing the input-current THD from 14.50% to 4.02%, corresponding to a relative reduction of 72.28%. Compared with the 50-kHz non-cycle-by-cycle scheme, the proposed scheme further reduces the THD from 6.06% to 4.02%, while maintaining substantially greater computational redundancy. These results demonstrate that the proposed scheme improves the control-input update resolution and input-current quality without requiring the complete control algorithm to be executed within every switching period.

It should be noted that the reduction in THD from 14.50% to 4.02% in the primary comparison is not caused by different PI gains or a higher PI-controller execution rate. Both the proposed scheme and the 10 kHz non-cycle-by-cycle scheme use the same PI gains and evaluate the PI controllers at 10 kHz. The difference is that the conventional scheme holds one modulation input for ten switching cycles, whereas the proposed scheme generates ten sequential modulation inputs in each slow-rate interval and applies a distinct input during every 100 kHz switching cycle. The 50 kHz baseline reduces the holding interval to two switching cycles and consequently decreases the THD to 6.06%, but it is limited by the available interrupt execution time. These results indicate that the main improvement arises from the switching-cycle-scale updating of the modulation input rather than from PI-gain retuning.

5. Discussion

The experimental results demonstrate that the improved input-current quality is mainly attributed to the increased control-input update resolution. In the conventional 10-kHz non-cycle-by-cycle scheme, the same control input is held for ten consecutive switching cycles, resulting in a control-input holding effect and an input-current THD of 14.50%. Increasing the conventional control frequency to 50 kHz reduces the THD to 6.06%, but decreases the computational redundancy to only 8.85%. In contrast, the proposed scheme generates ten distinct control inputs during each 10-kHz slow-rate interval and sequentially applies them at the 100-kHz switching frequency. Consequently, the input-current THD is reduced to 4.02%, while an overall computational redundancy of 46.41% is retained after accounting for both the slow- and fast-rate ISR workloads. Compared with the conventional 10-kHz scheme, the proposed method increases the ISR execution time by only 2.36 $\mathsf{\mu }$s but reduces the THD by 72.28%, demonstrating a favorable balance between control performance and computational feasibility.

The proposed multirate implementation provides a potential solution for high-switching-frequency AC/DC converters in which the complete control algorithm cannot be executed within every switching period. However, the sequence length and slow-rate frequency must be selected by considering the switching frequency, computational burden, timing safety margin, and interpolation accuracy. A larger sequence length provides more computation time but may increase the interpolation error under distorted or rapidly varying input-voltage conditions. Moreover, the present experimental validation is limited to a 409.5 W prototype operating with a 115 V/400 Hz input, a 200 V DC output, and a switching frequency of 100 kHz. Extension to higher-power converters or other applications, including electric-vehicle charging and inductive power-transfer systems, requires application-specific hardware design, control-parameter adjustment, and further experimental validation. Future work will investigate higher-power operation, nonideal input conditions, efficiency, thermal performance, and electromagnetic interference.

The proposed multirate-decoupled framework is not inherently restricted to the approximately 400 W prototype. Extension to higher power requires appropriate semiconductor ratings, passive components, sensing ranges, controller parameters, and cooling arrangements. Higher switching frequencies also require renewed timing analysis: operation at $f_{\mathrm{sw}}=200\mathrm{kHz}$ with $f_s=10\mathrm{kHz}$ would require $N=20$ and a fast-rate period of $5\mathsf{\mu }$s. Both the fast-rate execution deadline and the increased sequence-generation workload must be accommodated. Increasing N raises the control-input update rate but does not proportionally increase the feedback bandwidth. Furthermore, switching and conduction losses, junction temperature, commutation overshoot, and current stress must be evaluated, together with EMI filtering, layout, and gate-drive requirements. Improved input-current THD does not by itself demonstrate conducted or radiated EMI compliance. Protection based solely on the 10 kHz slow-rate sampling task may incur a detection delay approaching $100\mathsf{\mu }$s before processing and actuation delays are included. A dedicated fast protection path should therefore override the buffered control inputs independently of the slow-rate calculation while preserving a safe path for the DC-link inductor current. Accordingly, the present experiments validate the proposed scheme at approximately 400 W and 100 kHz, whereas higher-power operation, 200 kHz switching, and aviation qualification require further dedicated validation.

6. Conclusions

This paper proposes a multirate quasi-cycle-by-cycle framework that separates slow-rate feedback calculation from fast-rate control-input application. During each slow-rate interval, an N-element control-input sequence is generated from the sampled system information, and one sequence element is subsequently applied during every switching period. The term “quasi-cycle-by-cycle” indicates that the control inputs are applied cycle by cycle but are generated in advance from slow-rate feedback information; therefore, the proposed method does not perform new state sampling or complete feedback-controller evaluation during every switching period and should not be interpreted as providing an N-fold increase in closed-loop bandwidth. The framework is experimentally validated on a three-phase current source rectifier operating at 100 kHz and 409.5 W. With $f_s=10$ kHz and $N=10$, the control-input application rate reaches 100 kHz. Compared with the conventional 10 kHz non-cycle-by-cycle scheme, the proposed method reduces the input-current THD from 14.50% to 4.02%. After accounting for the $20.59\mathsf{\mu }\mathrm{s}$ slow-rate ISR and ten $3.30\mathsf{\mu }\mathrm{s}$ fast-rate ISR executions within each $100\mathsf{\mu }\mathrm{s}$ slow-rate interval, the overall processor utilization is 53.59%, leaving 46.41% overall computational redundancy. These results demonstrate that the proposed framework improves control-input resolution and input-current quality while preserving sufficient computational margin. The framework can also be combined with other converter topologies and control algorithms capable of generating and sequentially applying future control inputs.