Joint Multiplier–Adder Approximation with Flag-Based Error Recovery for BF16 Digital Compute-in-Memory

Abstract

Digital computing-in-memory (DCIM) provides deterministic floating-point computation but incurs substantial area and power overhead from replicated mantissa multipliers and adder trees. This work proposes an error-recoverable BF16 DCIM arithmetic unit that jointly approximates a 2-bit multiplier and the first adder stage. For the 11 × 11 input, the multiplier outputs 0111 instead of the Baseline 1111, converting the error from +6 to −2 and fixing the product MSB to 0. This enables the first adder stage to be reduced from 4 bits to 3 bits. A lightweight flag detects the same error condition and is reused as a carry input for local compensation, avoiding a separate multi-bit correction circuit. Hierarchical design-space exploration selected the 0111 approximation with carry compensation at bit position 1. Transistor-level evaluation showed reductions of 14.81% in transistor count and 28.56% in average power relative to the Baseline. Across ResNet18, VGG16-BN, and AlexNet on CIFAR-10 and CIFAR-100, the Proposed scheme achieved the lowest BF16-referenced Layer NRMSE and Logit NRMSE among the evaluated Baseline, DIMC-S-derived, LSAC OR+SXAFA-derived, and Proposed schemes, while the Top-1 accuracy difference relative to the Baseline remained within −0.02%p to +0.12%p. These results demonstrate an improved hardware–accuracy trade-off without retraining or data rearrangement.

1. Introduction

As neural network (NN) models increase in scale, frequent data movement between memory and compute units becomes a bottleneck in conventional von Neumann architectures [1,2]. Because computing-in-memory (CIM) can perform multiply–accumulate (MAC) operations within memory, it can mitigate this bottleneck by minimizing data movement. In addition, by simultaneously activating multiple static random-access memory (SRAM) rows to perform parallel MAC operations, CIM can reduce the overhead of repetitive row-by-row memory access and improve energy efficiency and computational throughput [3,4,5]. Meanwhile, NN weights, activations, and intermediate results can span a wide range of values depending on the layer and computation stage. A limited-bit-width integer (INT) format involves a trade-off between representable range and quantization resolution, whereas a floating-point (FP) format supports a wider dynamic range through exponent scaling [6].

Among the various types of CIM, analog computing-in-memory (ACIM) in particular has provided high efficiency in low-power, low-precision edge-device environments because it can perform INT MAC operations at low energy and area cost [3,4]. However, reduced robustness caused by limited signal margins and process variation is a major source of inference-accuracy degradation and can impair performance [4,7]. Although FP computation can also be implemented using analog arithmetic, achieving both computational accuracy and low circuit cost is difficult because exponent processing, mantissa alignment, and high-resolution readout circuits are required [8,9]. In contrast, digital computing-in-memory (DCIM) performs computation in the digital domain and is therefore less sensitive to computational errors caused by the nonidealities of analog accumulation, while providing deterministic computation results [5,7]. It is also relatively straightforward to construct an FP datapath and support multiple precision levels by integrating DCIM with conventional digital logic. Accordingly, DCIM has attracted attention as a promising approach for accurate and flexible FP-CIM implementation [7,8,9].

Unlike integer MAC, however, FP MAC additionally requires exponent comparison, exponent-difference calculation, mantissa alignment, multiplication, and multi-input accumulation [7,8,9]. Repeated placement of the comparators, subtractors, shifters, multipliers, and adder trees required for these operations at the sub-array or column level substantially increases area and switching energy [7,8,10]. Conversely, sharing these circuits increases the number of processing cycles and latency, thereby limiting throughput [7,10]. Thus, FP arithmetic overhead not only degrades energy efficiency and compute density, but also reduces the fraction of SRAM bitcells within a fixed macro area, thereby limiting weight density [10,11].

Approximate arithmetic has been studied as a means of addressing these issues [12]. In a floating-point format, the exponent represents the magnitude of a value; therefore, lower mantissa bits have a relatively small effect on the overall value. In bfloat16 (BF16), exponent-based scaling can limit the relative effect of lower-mantissa-bit approximation on the overall value, and previous BF16-CIM designs have applied least significant bit (LSB) approximation based on this property [6,11]. This can reduce the area, energy, and processing cycles of multipliers and adder trees [11,13]. However, because the magnitude and direction of the resulting error depend on the approximation method and errors can accumulate through repeated MAC operations, recent studies have focused on maximizing hardware gains while limiting accuracy loss [14,15,16,17,18,19,20,21].

Accordingly, this work makes three main contributions. First, the exceptional 11 × 11 multiplier output and the first-stage adder are jointly redesigned so that the approximation error changes from +6 to −2 while the product MSB is fixed to 0, enabling the first-stage adder to be reduced from a 4-bit to a 3-bit structure. Second, the error-inducing output pattern is detected using a lightweight flag, which is reused in the existing bit-1 carry path to provide selective compensation without a separate multi-bit correction circuit. Third, a hierarchical design-space exploration of the multiplier output mapping and compensation position is performed, and the selected design is evaluated through transistor-level circuit analysis and full CIFAR-10/CIFAR-100 inference using ResNet18, VGG16-BN, and AlexNet without retraining or data rearrangement.

2. Related Work

2.1. Multiplier-Centric Approximation

Multiplier-centric approaches focus on reducing the multiplication and alignment costs of FP-CIM. Conventional pre-accumulation alignment repeatedly uses comparators and shifters before accumulating multiplication results. To reduce this cost, STAR-SRAM proposed pre-multiply symmetric alignment, which simultaneously aligns the input and weight mantissas before multiplication [10]. Although this method introduces its own numerical error because information is shifted within a limited bit width, it enables the partial products that contribute to MSB formation to be preserved while selectively removing the less significant remaining partial products [10].

Mitchell-based DCIM avoids directly performing conventional binary multiplication and instead transforms multiplication into operations centered on addition and shifting using an approximate logarithmic representation [22]. Although this avoids bit-serial multiplication, the actual datapath still requires multi-bit adders, shifters, 2’s-complement units, and an adder tree [22].

By concentrating approximation on alignment and multiplication, these multiplier-centric approaches are advantageous for reducing hardware cost with relatively limited error [10,19,22]. However, the scope of circuit reduction may be narrower than that of approaches that directly approximate compressors and adder trees.

2.2. Accumulation-Centric Approximation

In digital CIM, the compressor and adder tree that sum multiple multiplication results are major contributors to area and power [13,23]. DIMC constructs an approximate compressor in which errors are partially canceled by exploiting the fact that AND and OR operations generate negative and positive errors, respectively [23]. This approach substantially reduces the transistor count of the compressor; however, applying aggressive approximation directly to an existing trained model caused considerable accuracy degradation. DIMC therefore combined approximation-aware training with the MB-XNOR number format to recover inference accuracy [23].

LSAC replaces exact full adders in the adder tree with single-XOR- and single-OR-based approximate full adders [24]. It also applies different approximate adders to high-bit and low-bit weights, and reduces the frequency of input combinations that produce large errors through structural pruning and offline data rearrangement. Accordingly, LSAC represents hardware–software co-design that considers not only circuit-level approximation but also weight sparsity and data placement [24].

Because these methods directly simplify the adder tree, they have the potential to achieve greater circuit reduction than methods that approximate only part of the multiplier. However, arithmetic error increases as the approximation becomes more aggressive, and software-level processing such as retraining, pruning, or data rearrangement is required to maintain the accuracy levels reported in the corresponding studies [23,24]. In other words, rather than replacing only the hardware in an already trained model, the model and data mapping must be adapted to the approximate circuit.

2.3. Joint Multiplier–Adder-Tree Approximation

Joint approximation simultaneously reduces multiple computation stages in the mantissa datapath by simplifying both the local multiplier and the subsequent adder tree. The BF16 DCIM macro reported by Kim et al. divides the mantissa into 2-bit segments, processes them over three cycles, and approximates the exact 11 × 11 result of 1001 as 1111 [11]. In the following first adder-tree stage, it removes one full adder by using the OR of the MSBs of the two operands as the carry-in, thereby mitigating the resulting accumulation error [11]. Thus, the multiplier and adder-tree approximations are not independent; rather, they can be regarded as a fixed arithmetic co-design that combines a particular multiplier output pattern with an MSB-OR carry rule. However, because a systematic design-space exploration of other approximate output mappings and carry-compensation rules was not presented, it is difficult to determine whether this combination provides the optimal hardware–accuracy trade-off [11].

Joint approximation can reduce both multiplication and accumulation costs, but the errors generated in the two stages interact; therefore, joint design of the multiplier error pattern and adder compensation rule is important [14,15,16,17,18,19,20,25]. In this study, the error direction of the 11 × 11 approximation is constrained to be negative, and the corresponding condition is detected using a lightweight flag to apply carry compensation in the next adder stage. Unlike the conventional fixed MSB-OR carry rule, the proposed method detects the actual error-inducing multiplication case and selectively compensates for it.

3. Proposed Design

3.1. Joint Approximation

Figure 1 shows the overall mantissa datapath of the proposed BF16 DCIM macro. Weight mantissas are stored in four mantissa weight groups, each consisting of 64 sub-arrays. In each sub-array, the aligned input mantissa and stored weight mantissa are processed in 2-bit segments, and two 2-bit multipliers generate local products. The local products are accumulated through an adder tree, in which the proposed 3-bit approximate adder with flag-based recovery is applied at the first stage. Subsequent higher-stage adders and a shifter-and-adder combine the partial sums to generate the final mantissa-accumulation result.

This study jointly approximates the local multiplier and first-stage adder, which are major contributors to hardware cost in BF16 DCIM mantissa computation. In conventional independent approximation, the errors generated by each operation can overlap during accumulation and degrade accuracy [14,15,16,17,18]. In contrast, the proposed structure intentionally constrains the direction and occurrence condition of the multiplier error, detects whether an error has occurred, and conditionally compensates for it in the first-stage adder.

The exact result of 11 × 11 in 2-bit unsigned multiplication is as follows.

(11)₂ × (11)₂ = (1001)₂ = 9.

(1)

The Baseline multiplier approximates this case as 1111, producing the following positive error.

ε_BASE = 15 − 9 = +6.

(2)

In this study, the corresponding product is approximated as (0111)₂.

ε_PROP = 7 − 9 = −2.

(3)

Therefore, the absolute error of the error-inducing multiplication case is reduced from 6 to 2, and the error direction is constrained to be negative. This negative error can be compensated for by injecting a positive carry in the subsequent adder [14,15,16,20]. In contrast, directly compensating for a positive error may require a separate subtraction or borrow operation to remove a value from the result. Thus, a bounded negative error is more suitable for the proposed structure, which uses low-cost carry-in-based recovery [14,15,16,18,20].

Furthermore, among all input combinations of 2-bit unsigned multiplication, the only case in which bit 3 of the product is 1 is 11 × 11 = 1001. Because the proposed multiplier changes this result to 0111, the MSB is 0 for every reachable output generated by the proposed multiplier. Consequently, the first-stage adder does not need to process the fourth multiplier output bit, and the conventional 4-bit product-addition structure can be reduced to an adder structure with 3-bit operands. Thus, the 0111 mapping not only reduces multiplier error but also structurally reduces the cost of the subsequent first-stage adder.

Figure 2 shows the gate-level structures of the proposed multiplier and first-stage recovery adder. The multiplier in Figure 2b generates the product using the complementary inputs I[1:0] and W[1:0]. Z[0] and Z[2] are implemented using NOR gates with I[0], W[0] and I[1], W[1] as their respective inputs. Z[1] is generated by combining the two cross-product terms in an OAI22 form, and Z[3] is tied to GND. The output of the proposed multiplier can therefore be expressed as follows.

Z[0] = ~(~I₀ ∨ ~W₀) = I₀ ∧ W₀,

(4)

Z[1] = ~[(~W₁ ∨ ~I₀) ∧ (~W₀ ∨ ~I₁)] = (I₀ ∧ W₁) ∨ (I₁ ∧ W₀),

(5)

Z[2] = ~(~I₁ ∨ ~W₁) = I₁ ∧ W₁,

(6)

Z[3] = 0.

(7)

This gate configuration generates only the three valid product bits required for the proposed mapping and removes the Z[3] path that is required for exact multiplication when the inputs are 11 × 11. In particular, instead of cascading two partial-product AND gates followed by a separate OR gate, Z[1] can be integrated into a single OAI logic gate using complementary inputs. Therefore, the 0111 mapping contributes not only to output-width reduction but also to simplification of the internal multiplier logic.

For the 11 × 11 input that produces an approximation error, the output is 0111, and therefore Z[2] and Z[0] are simultaneously 1. Because this condition does not occur for any other output that can be generated by the proposed multiplier, the logical error event E can be detected as follows.

E = Z[2] ∧ Z[0].

(8)

In the actual circuit shown in Figure 2a, Z[2] and Z[0] are applied to a NAND gate to generate an active-low flag.

FLAG_N = ~(Z[2] ∧ Z[0]).

(9)

Thus, error detection requires only two product bits already generated by the multiplier and one NAND gate, without a separate comparator to re-evaluate the original operands.

Figure 2a shows the proposed first-stage adder that accumulates the outputs of two local multipliers and its flag-based recovery path. Let the 3-bit outputs of the two multipliers be A[2:0] and B[2:0], respectively. The LSBs A[0] and B[0] are processed by an 8T half adder to generate S[0] and carry C0. The active-low flag generated by each multiplier is transferred to the recovery logic. If the two flags are denoted as FLAG_N,A and FLAG_N,B, the active-high recovery signal R, which indicates that an error has occurred in at least one multiplier, is generated as follows.

R = ~(FLAG_N,A ∧ FLAG_N,B) = E_A ∨ E_B.

(10)

The generated recovery signal is ORed with the original carry C0 of the LSB half adder and then applied as the carry-in of the 18T FA responsible for bit 1.

C_in,1 = C0 ∨ R.

(11)

The 16T FA at bit 2 then generates S[2] and the final carry S[3]. Thus, the proposed first-stage adder consists of an 8T HA, an 18T FA, and a 16T FA, and performs recovery within the existing carry path without a separate multi-bit correction adder.

The error introduced by the 11 × 11 → 0111 mapping is −2; therefore, activating the carry at bit position 1 provides a +2 arithmetic correction. When a single approximation event occurs, and the native carry generated by the LSB half adder is 0, the recovery signal changes the carry input at bit position 1 from 0 to 1, and the −2 multiplier error can be fully compensated. The flag is reused both as a signal indicating the occurrence of an error and as local metadata for generating the correction bit, thereby minimizing the additional datapath required for error detection and recovery [14,15,16].

In contrast, if an approximation event occurs while the native carry is already 1, activating the recovery signal cannot further increase the carry input. In this work, OR saturation denotes this logical condition in which the already-activated carry prevents the 1-bit OR-based recovery path from representing an additional +2 correction. Consequently, a single approximation event under this condition can leave a −2 residual error. When approximation events occur simultaneously in both multipliers, the total multiplier error becomes −4, but the two events are merged into a single binary recovery signal. Because the recovery path cannot represent two independent +2 corrections, a −4 residual error can remain. These incomplete-recovery conditions correspond to the nonzero entries in

Table 1. Output error for valid first-stage adder input combinations.

A\B	0000	0001	0010	0011	0100	0110	0111
0000	0	0	0	0	0	0	0
0001	0	0	0	0	0	0	−2
0010	0	0	0	0	0	0	0
0011	0	0	0	0	0	0	−2
0100	0	0	0	0	0	0	0
0110	0	0	0	0	0	0	0
0111	0	−2	0	−2	0	0	−4

−2/−4: residual error magnitude; 0: recovered or error-free output.

.

3.2. Design-Space Exploration

To determine which approximation method is most efficient for local arithmetic in BF16 DCIM, this study conducted a hierarchical design-space exploration of the multiplier and first-stage adder [17,19,25]. Because both operators are repeatedly used in the local computations of the mantissa datapath and account for a substantial portion of the circuit cost, even limited circuit modifications can produce considerable cost reductions. Throughout the exploration, exponent alignment, three-cycle operation, the multiplier-pair configuration, the subsequent accumulation structure, and the 16T/18T full-adder cells were held constant. The independent variables were limited to the exceptional output code of the 2-bit × 2-bit multiplier, the 3FA/4FA architecture of the first-stage adder, and the compensation position. Therefore, the candidates differed only in the multiplier error pattern and first-stage recovery method.

The exploration metrics were divided into arithmetic accuracy and hardware cost [17,18,19,25]. Arithmetic accuracy was evaluated using error rate, mean signed error, absolute bias, RMSE, maximum absolute error, and residual-error rate [17,18,19,25]. For the recovery candidates, full-recovery count and OR-saturation count were also measured. In the initial exhaustive search, the transistor counts of the multiplier, flag, and adder macro were used as hardware-cost proxies. Transistor-level PPA and CNN inference accuracy were then evaluated separately for the final candidate set.

In the first stage, the exceptional output of the 2-bit × 2-bit multiplier for the 11 × 11 input was varied from 0 to 15. Multiplication for the remaining 15 input combinations was fixed to exact multiplication. Because the exact result of 11 × 11 is 9, the multiplier error of exceptional code c was defined as c − 9. For each code, the multiplier transistor count, flag-generation overhead, error polarity and magnitude, and output MSB were compared. Codes 10–15 produce positive multiplier errors, which are difficult to reduce consistently through simple positive carry injection. Instead, positive errors require compensation such as XOR-based correction or adder reduction at the compensation stage. XOR-based compensation can provide precise correction but is more costly than OR-based compensation, whereas adder reduction makes it difficult to control the error magnitude. Therefore, under the proposed positive-carry compensation constraint, negative-error mappings are more suitable.

Codes 0–8 produce negative multiplier errors and are therefore directionally compatible with subsequent positive carry compensation. In particular, codes 0–7 always have an output MSB of 0, allowing the first-stage adder to be reduced from 4FA to 3FA. Within this range, code 7 outputs 0111 and produces a bounded error of −2, while exhibiting the lowest circuit cost with a 16T multiplier and a 20T implementation including the flag. Code 8 has a smaller error of −1, but its output MSB is 1 and the multiplier cost increases. Thus, when both multiplier cost and the possibility of adder reduction are considered, code 7 emerges as the primary candidate.

Figure 3 compares the transistor count of the local multiplier for each exceptional output code. Code 7 has a lower circuit cost than code 9, which corresponds to exact multiplication, and fixes the output MSB to 0. It therefore enables both simplification of the multiplier itself and reduction of the first-stage adder to 3FA. Accordingly, when the transistor count and subsequent adder structure are considered together, code 7 is included among the most advantageous candidates.

In the second stage, only the compensation position was varied while each multiplier code was fixed. The evaluated candidates were a structure without compensation, a BIT0 structure that directly applies compensation to the LSB carry-in, and structures that insert OR compensation at BIT1, BIT2, BIT3, or the output bit. All candidates were exhaustively evaluated over the 256 possible input combinations of the two multipliers. This evaluation considered not only the nominal compensation weight but also OR saturation, in which compensation is lost because of a native carry.

Table 2. Code 7 compensation-placement comparison.

Placement	Total Transistors	Normalized RMSE (%)	Residual Error Rate (%)	Absolute Bias	Maximum Error	Full Recovery	OR Saturation
NONE	74	4.0493	12.109%	0.250000	4	0	0
BIT0	94	2.1684	12.109%	0.128906	3	0	0
OR_BIT1 (Proposed)	92	2.1960	2.734%	0.062500	4	24	7
OR_BIT2	92	4.0493	12.109%	0.000000	4	0	15
OR_BIT3	92	8.3910	12.109%	0.187500	6	0	17
OR_OUTPUT4	92	26.9495	12.109%	1.687500	14	0	0

The RMSE was normalized by the maximum exact sum of two 2-bit multiplication results, i.e., 18. The selected Proposed configuration is shown in bold.

summarizes the results obtained by varying the compensation position for the code-7 multiplier. The NONE structure without compensation has the lowest circuit cost at 74T, but its residual-error rate remains at 12.109%. BIT0 has the lowest RMSE and maximum error; however, because it injects only +1 for every error event, no complete recovery occurs, and the residual-error rate is not reduced. OR_BIT2 has a mean bias of 0, but this results from cancelation between positive and negative errors, and neither the RMSE nor residual-error rate is improved. In contrast, OR_BIT1 provides compensation with the same weight as the −2 error of the code-7 multiplier, completely recovering 24 of the 31 event cases. It reduces the residual-error rate from 12.109% to 2.734% and the absolute bias from 0.128906 to 0.062500. Its RMSE is approximately 1.27% higher than that of BIT0, but its total transistor count is lower by 2T. Across the complete 256 pair-input combinations, 31 combinations contain at least one Code-7 approximation event; 24 are fully recovered by OR_BIT1, whereas the remaining 7 are limited by the OR-based recovery path and retain a nonzero residual error.

Table 3. Final local-arithmetic architecture comparison.

Architecture	Total Transistors	RMSE (%)	Absolute Bias	Maximum Error	Role
Exact FULL4FA	156	0.00	0.00	0	Exact endpoint
Baseline 3FA	108	2.17	0.13	3	Baseline
Code 7 NONE	74	4.05	0.25	4	Minimum-cost endpoint
Code 7 BIT0	94	2.17	0.13	3	Minimum-RMSE endpoint
Proposed: Code 7 + OR_BIT1	92	2.20	0.06	4	Selected design point

The selected Proposed design point is shown in bold.

compares the principal candidates derived from the design-space exploration with the Exact and Baseline structures over the same local-arithmetic scope. The Proposed structure uses 92T, which is lower than the 156T of the Exact FULL4FA and the 108T of the Baseline 3FA. Its RMSE is approximately 1.27% higher than that of the minimum-RMSE endpoint, code 7 BIT0; however, the residual-error rate decreases from 12.109% to 2.734%, and the absolute bias decreases from 0.128906 to 0.062500. Therefore, the Proposed structure is not a candidate that minimizes only RMSE or transistor count; rather, it is a design point that improves both circuit cost and residual-error characteristics.

The final multiplier code was selected by considering both the exceptional-error magnitude and the possibility of reducing the first-stage adder width. For the exact exceptional multiplication (11₂ × 11₂ = 9), the error of an output code c is defined as ε = c − 9; therefore, Codes 6, 7, and 8 correspond to errors of −3, −2, and −1, respectively. Codes 0–7 have a zero output MSB and can therefore retain the reduced first-stage operand width. Among these MSB-zero candidates, Code 7 has the smallest exceptional-error magnitude. Code 8 further reduces the error magnitude to −1, but retains the output MSB and therefore does not provide the same first-stage width reduction.

The compensation position was subsequently evaluated according to its arithmetic correspondence with the multiplier error. The −2 error of Code 7 is directly matched by the +2 correction at bit 1, enabling exact recovery for a large fraction of the error-event cases. By contrast, Code 6 + OR_BIT1 applies only a +2 correction to a −3 error and therefore cannot exactly cancel a single approximation event. Code 8 + BIT0 directly matches its −1 error with a +1 correction and can consequently reduce the numerical error further; however, this configuration retains the multiplier-output MSB and cannot use the reduced first-stage architecture.

The joint DSE comprises 61 Code × compensation configurations evaluated exhaustively over all 256 multiplier-pair inputs. Code 7 + OR_BIT1 achieves a normalized RMSE of 2.1960% and a residual-error rate of 2.734%, with 24 full-recovery cases at an analytical structural cost of 92T. Code 8 + BIT0 further reduces the normalized RMSE to 0.3472% and the residual-error rate to 0.391%. However, because Code 8 retains the output MSB and does not enable the first-stage width reduction, its analytical structural cost increases to 122T, 30T higher than the Proposed configuration. Code 6 + OR_BIT1, in comparison, requires 104T, with a normalized RMSE of 2.3550% and a residual-error rate of 12.109%.

Table 4. Representative hardware–error trade-offs in the joint code–compensation design space.

Configuration	Error ε	Analytical Cost (T) *	Normalized RMSE (%)	Residual Error Rate	Absolute Bias	Maximum Error	Full Recovery	OR Saturation
Code 6 + OR_BIT1	−3	104	2.3550	12.109%	0.132812	4	0	0
Code 7 + NONE	−2	74	4.0493	12.109%	0.250000	4	0	0
Code 7 + BIT0	−2	94	2.1684	12.109%	0.128906	3	0	0
Code 7 + OR_BIT1 (Proposed)	−2	92	2.1960	2.734%	0.062500	4	24	7
Code 8 + NONE	−1	110	2.0246	12.109%	0.125000	2	0	0
Code 8 + BIT0	−1	122	0.3472	0.391%	0.003906	1	30	0
Code 8 + OR_BIT1	−1	120	1.9018	11.719%	0.117188	1	1	0

* Analytical Cost (T): DSE transistor-count proxy, not measured area/PPA. Code 8 retains the output MSB; NRMSE is normalized by 18. The selected Proposed configuration is shown in bold; additional bold values indicate the best numerical-error/recovery metrics among the listed alternatives.

summarizes representative hardware–error trade-offs in the joint code–compensation design space.

Accordingly, the final design point was selected based on the combined hardware–error trade-off rather than arithmetic-error minimization alone. Code 7 + OR_BIT1 preserves the reduced first-stage architecture and maintains substantially lower structural cost than the lower-error Code 8 alternative, while reducing the residual-error rate from 12.109% without compensation to 2.734%. Thus, the selected configuration provides the hardware reduction targeted by the joint multiplier–adder approximation while retaining effective error control.

4. Evaluation and Analysis

4.1. Evaluation Setup and Baseline

The Baseline local arithmetic unit used in this study was reconstructed from the BF16 DCIM arithmetic organization reported in [11]. In the published Baseline macro [11], the upper six bits of the 7-bit fraction of the BF16 weight mantissa, excluding the LSB, are divided into 2-bit segments and processed over three cycles. For the local circuit comparison, the overall datapath, including exponent alignment, three-cycle operation, and the accumulation structure, was kept consistent with the published architecture, and the compared arithmetic units are explicitly denoted as Exact, Baseline, and Proposed.

The Baseline and Proposed designs are not evaluated as two independently redesigned BF16 DCIM macros. The exponent-alignment scheme, three-cycle mantissa processing, multiplier-pair organization, and subsequent higher-stage accumulation are retained consistently with the published Baseline architecture, while the structural modification is concentrated in the local 2-bit × 2-bit multiplier and first-stage pair-adder boundary. The Proposed flag-generation and carry-recovery circuitry are also included within this local replacement boundary. Accordingly, the macro-level significance of the local circuit-level PPA can be examined from the replication of this arithmetic boundary in the published Baseline hierarchy.

The circuit-level comparison evaluates a common local arithmetic boundary consisting of two 2-bit × 2-bit multipliers and one first-stage pair adder, including the flag-generation and carry-recovery circuitry in the Proposed design. The arithmetic units were implemented at the transistor level in Cadence Virtuoso and evaluated using Spectre transient simulation in a 28 nm technology. Transistor count is used as a circuit-complexity-based area proxy rather than as a physical layout-area measurement. The nominal circuit-level comparison is performed at 1.0 V under the TT/25 °C condition. For the nominal power and energy comparison, the same 64-vector sequence is applied for 5 ns per vector with 50 ps input rise/fall times, for a total simulation interval of 320 ns.

CIFAR-10 and CIFAR-100 are 32 × 32 color-image classification datasets containing 60,000 images each, with 10 and 100 classes, respectively; each dataset contains 50,000 training images and 10,000 test images. Inference accuracy was evaluated on all 10,000 test images in each dataset using pretrained ResNet18, VGG16-BN, and AlexNet checkpoints.

To provide a controlled comparison with external approximate-arithmetic schemes, representative approximation mechanisms from DIMC and LSAC were functionally emulated within the same BF16 evaluation framework. DIMC-S-derived applies the single-approximate compressor mechanism [23], whereas LSAC OR+SXAFA-derived applies the OR+SXAFA approximate-adder-tree mechanism [24]. The same pretrained checkpoints, preprocessing, test-sample order, and BF16 reference were used for all schemes. Accordingly, this comparison evaluates the numerical behavior of the approximation mechanisms under a common BF16 workload rather than reproducing the native macros or their complete software co-design procedures.

Numerical error was evaluated using Layer normalized root mean square error (NRMSE) and Logit NRMSE against the same BF16 reference. Layer NRMSE was evaluated for Conv2d and Linear outputs over a fixed 64-image diagnostic subset, whereas Logit NRMSE and Top-1 accuracy were evaluated over the complete 10,000-image test set of each dataset.

4.2. PPA Evaluation

Table 5. Circuit-level implementation metrics for the local arithmetic unit.

Design	Transistor Count	Normalized Area	Average Power (µW)	Normalized Power	Energy (fJ)	Worst-Case Propagation Delay (ps)
Exact	156	1.000	1.71	1.00	546.40	75.457
Baseline	108	0.692	1.40	0.82	449.33	46.589
Proposed	92	0.590	1.00	0.59	321.00	54.602

Transistor count is used as an area proxy. Area and power are normalized to the Exact implementation. Energy is the total supply energy over the common 64-vector input sequence. Best values for each metric are shown in bold.

compares the circuit-level implementation results of the Exact, Baseline, and Proposed arithmetic units over the common local boundary. The transistor counts of the Exact, Baseline, and Proposed structures are 156T, 108T, and 92T, respectively; thus, the Proposed structure reduces the transistor count by 14.81% relative to the Baseline. The normalized area proxy likewise decreases from 0.692 for the Baseline to 0.590 for the Proposed structure.

The average power was measured as 1.71, 1.40, and 1.00 μW for the Exact, Baseline, and Proposed structures, respectively, and the Proposed structure consumed 28.56% less power than the Baseline. Over the same 320 ns, 64-vector sequence, the total supply energy decreased from 449.33 fJ for the Baseline to 321.00 fJ for the Proposed design. This result directly quantifies the energy advantage of the repeated local arithmetic boundary; the actual complete-macro energy reduction additionally depends on the switching activity of global circuitry, interconnect capacitance, and physical integration and is therefore not directly extrapolated from the local value.

At the nominal TT/1.0 V/25 °C condition, the worst propagation delays of the Baseline and Proposed local pair-arithmetic units are 46.589 ps and 54.602 ps, respectively. The Proposed design therefore introduces an absolute delay increase of 8.013 ps, corresponding to a 17.20% relative local delay overhead.

The same local timing boundary was further evaluated under representative PVT conditions. The Proposed-to-Baseline delay overheads are 18.67%, 16.30%, 17.20%, 16.38%, and 16.28% for SSF/0.9 V/125 °C, SSF/0.9 V/−40 °C, TT/1.0 V/25 °C, FFF/1.1 V/125 °C, and FFF/1.1 V/−40 °C, respectively. The maximum Proposed delay within the evaluated set is 98.568 ps. These results show that the relative local timing penalty remains within a narrow 16.28–18.67% range across the evaluated PVT conditions.

For macro-level timing interpretation, the absolute delay increment provides a more meaningful scale than directly applying the 17.20% local percentage to the macro clock frequency. The published Baseline shmoo includes a passing operating point at 205 MHz and 0.9 V [11], corresponding to a clock period of approximately 4.878 ns. The nominal 8.013 ps local delay increment is approximately 0.164% of this demonstrated clock-period scale. Therefore, the 17.20% relative delay increase observed inside the local arithmetic boundary does not correspond to an equivalent 17.20% reduction in macro operating frequency or throughput.

In addition, the Proposed arithmetic replacement preserves the Baseline three-cycle mantissa-processing schedule [11] and introduces no additional processing cycle or pipeline stage. Thus, the Proposed structure does not add cycle-level latency at the architectural level. The PVT results indicate a consistent local timing cost, while its absolute increment remains small relative to the demonstrated macro clock-period scale; accordingly, the local delay penalty is treated as a timing cost of the replacement boundary rather than as an equivalent macro-throughput penalty.

Table 6. Representative PVT timing evaluation of the local pair-arithmetic unit.

PVT Condition	Baseline Worst Delay (ps)	Proposed Worst Delay (ps)	Proposed vs. Baseline
SSF/0.9 V/125 °C	64.135	76.108	+18.67%
SSF/0.9 V/−40 °C	84.754	98.568	+16.30%
TT/1.0 V/25 °C	46.589	54.602	+17.20%
FFF/1.1 V/125 °C	33.279	38.729	+16.38%
FFF/1.1 V/−40 °C	34.781	40.443	+16.28%

summarizes the representative PVT timing results for the local pair-arithmetic unit.

The published Baseline contains eight CIM arrays, and three of the four mantissa-weight blocks in each array process non-sign 2-bit mantissa segments, while the remaining block implements the sign path. Because each non-sign block contains 64 2-bit multipliers, the published non-sign datapath affected by the Proposed structure contains a total of 1536 2-bit multipliers and 768 first-stage multiplier-pair boundaries [11].

In the present circuit-level comparison, one replacement boundary consists of two 2-bit multipliers and one first-stage pair adder, with transistor counts of 108T for the Baseline and 92T for the Proposed design. Replicating the same local implementation over the 768 pair boundaries identified in the published hierarchy gives transistor-count proxies of 82,944T and 70,656T, respectively. This corresponds to a reduction of 12,288T, or 14.81%, showing that the measured local reduction ratio is preserved when the replacement boundary is propagated through the repeated arithmetic hierarchy.

The first stage of the published six-stage Baseline adder tree consists of 32 three-bit pair adders. In terms of logical adder-bit instances, this stage contains 96 of the 246 instances in the approximate tree, corresponding to approximately 39.0%. Thus, the Proposed modification targets the most highly replicated stage of the adder tree rather than an isolated arithmetic element.

The reported compute/memory composition in Baseline Figure 4 assigns 20.7%, 48.3%, 22.9%, and 8.1% to MUX, MUL, ADDER, and SRAM, respectively [11], indicating that multiplier and adder circuitry are major hardware-cost components of the reported compute structure. When the measured implementation reductions of the multiplier and first-stage adder are combined with the topology-derived first-stage contribution, the resulting first-order hardware-cost proxy corresponds to an approximately 9.2% reduction in the four-category composition reported in Baseline Figure 4. This value is an architecture-derived area proxy obtained from the published topology and measured local transistor-count ratios, rather than a post-layout measurement of the complete macro.

Figure 4 visualizes the published Baseline hardware composition and the corresponding first-order Proposed composition after applying the architecture-derived reduction proxy. Figure 5 summarizes the normalized local area-proxy, average-power, and propagation-delay comparison between the Baseline and Proposed arithmetic units.

4.3. Numerical Error and Inference Accuracy

Table 7. BF16-referenced NRMSE comparison under common CNN workloads.

Dataset	Model	Baseline	DIMC-S-Derived	LSAC OR+SXAFA-Derived	Proposed
CIFAR-10	ResNet18	3.321/4.787	10.632/9.205	6.896/6.165	3.230/4.634
CIFAR-10	VGG16-BN	2.940/5.333	14.684/13.529	6.906/5.648	2.856/5.086
CIFAR-10	AlexNet	3.106/5.144	7.913/13.054	4.218/7.066	3.019/5.018
CIFAR-100	ResNet18	3.135/9.299	9.672/14.045	6.318/9.892	3.050/9.087
CIFAR-100	VGG16-BN	3.185/7.591	13.782/19.854	7.466/11.050	3.094/7.321
CIFAR-100	AlexNet	5.750/9.589	14.870/18.587	10.293/11.376	5.636/9.225

Layer/Logit NRMSE (%). Layer: fixed 64-image Conv2d/Linear diagnostic; Logit: full 10,000-image test set. BF16 reference; lower is better. Best values in each row are shown in bold.

compares the numerical error of the Baseline, DIMC-S-derived, LSAC OR+SXAFA-derived, and Proposed schemes under the same BF16 reference and CNN workloads. Unlike the previous local-RMSE evaluation, the revised comparison uses Layer NRMSE and Logit NRMSE so that approximation mechanisms with different arithmetic boundaries can be evaluated using a common numerical reference. The Proposed scheme achieves the lowest Layer NRMSE and Logit NRMSE among the four evaluated schemes for ResNet18, VGG16-BN, and AlexNet on both CIFAR-10 and CIFAR-100.

Relative to DIMC-S-derived, the Proposed scheme reduces Layer NRMSE by 61.85–80.55% and Logit NRMSE by 35.30–63.13%. Relative to LSAC OR+SXAFA-derived, the corresponding reductions are 28.43–58.64% and 8.14–33.75%, respectively. The layer-call NRMSE distributions show the same trend, with the Proposed scheme exhibiting the lowest median, P95, and maximum values in all six model–dataset combinations. Thus, the reduction in aggregate numerical error is consistently observed across the layer-wise error distribution.

The 256-case exhaustive analysis in Section 3.2 characterizes the structural residual behavior of the Proposed recovery logic, but it does not represent how often each local operand combination occurs in a trained CNN workload. To quantify workload-level behavior, the existing BF16 inference path was additionally instrumented to count the 2-bit local operands after exponent alignment for all 10,000 test images of CIFAR-10 and CIFAR-100 using ResNet18, VGG16-BN, and AlexNet. The instrumentation only observes the operands and does not alter the arithmetic path; the instrumented runs reproduced the previously obtained Proposed logits and Top-1 results.

Exceptional MUL is normalized by the number of individual local multiplier operations. Flagged Pair and Residual/Pair are normalized by the number of local pair operations scheduled in the fixed group-64 arithmetic datapath, including zero-padded lanes used to complete an incomplete group. Full Recovery/Flag and OR Saturation/Flag use flagged pairs as the denominator. The observed nonzero residuals (−2 and −4) are unscaled first-stage local arithmetic residuals before sign, positional weighting, and exponent scaling.

As shown in

Table 8. Workload-level occurrence and recovery statistics for the Proposed arithmetic unit.

Dataset	Model	Exceptional MUL (%)	Flagged Pair (%)	Full Recovery/Flag (%)	OR Saturation/Flag (%)	Residual/Pair (%)
CIFAR-10	ResNet18	0.427	0.842	87.324	12.676	0.107
CIFAR-10	VGG16-BN	0.368	0.726	88.528	11.472	0.083
CIFAR-10	AlexNet	0.638	1.254	85.715	14.285	0.179
CIFAR-100	ResNet18	0.427	0.841	87.087	12.913	0.109
CIFAR-100	VGG16-BN	0.405	0.799	87.860	12.140	0.097
CIFAR-100	AlexNet	0.584	1.128	80.503	19.497	0.220

Denominators: MUL = individual operations; Pair = scheduled pairs (including zero padding); Recovery/Saturation = flagged pairs. Residuals are unscaled local errors (−2/−4).

, exceptional 11₂ × 11₂ multiplier events occurred in 0.368–0.638% of individual multiplier operations, while at least one error flag was raised in 0.726–1.254% of scheduled local pair operations. Among flagged pairs, 80.50–88.53% were fully recovered through the bit-1 carry compensation, whereas 11.47–19.50% corresponded to OR saturation. Consequently, the empirical nonzero residual-event rate was 0.083–0.220% of scheduled local pairs. In all six model–dataset configurations, the residual-event count exactly matched the OR-saturation count, and all observed nonzero local residuals were limited to −2 or −4. Accordingly, the 2.734% value from the uniform 256-case evaluation is interpreted as an exhaustive-domain residual rate rather than the occurrence probability of residual errors in an actual CNN workload.

The full-workload layer-wise aggregation showed workload-dependent variation in local event frequency but no monotonic trend with network depth. When the three activation-mantissa processing cycles were grouped as XH, XM, and XL, the residual-event frequency increased from XH to XM to XL in all six evaluated model–dataset configurations. Because each activation-cycle bucket aggregates cross-products with WH, WM, and WL, this result is used only as an event-frequency trend and not as a direct measure of numerical significance. Sign, individual exponent shift, channel, accumulation depth, and zero/denormal category were not independently stratified; therefore, no conditional error-bias claim is made for these categories.

Table 9. Top-1 inference-accuracy comparison under the common BF16 workloads.

Dataset	Model	Baseline (%)	DIMC-S-Derived (%)	LSAC OR+SXAFA-Derived (%)	Proposed (%)
CIFAR-10	ResNet18	94.72	94.58	94.72	94.74
CIFAR-10	VGG16-BN	93.22	92.57	93.12	93.26
CIFAR-10	AlexNet	88.55	88.16	88.29	88.59
CIFAR-100	ResNet18	78.95	78.48	78.77	78.96
CIFAR-100	VGG16-BN	74.67	73.70	74.37	74.79
CIFAR-100	AlexNet	68.58	64.20	66.86	68.56

Top-1: full 10,000-image test set; higher is better. Best values in each row are shown in bold.

compares the Top-1 inference accuracy of the four schemes under the same workloads. The Proposed scheme achieves higher Top-1 accuracy than DIMC-S-derived and LSAC OR+SXAFA-derived in all six model–dataset combinations. Relative to the Baseline, the difference remains within −0.02 to +0.12 percentage points. Accordingly, the results are interpreted as reduced numerical distortion with inference accuracy comparable to the Baseline rather than as a general improvement in inference accuracy.

5. Discussion

Although this study directly evaluates the mantissa datapath of BF16 DCIM, the fundamental design objective of the proposed structure is not limited to a particular data format or CIM architecture. In various arithmetic units dominated by repeated MAC operations, multipliers and accumulation circuits are major contributors to area and power. Some conventional approximate-arithmetic methods combine circuit simplification with software-level processing, such as retraining, pruning, data mapping, or number formats designed for approximate arithmetic, to mitigate the resulting accuracy degradation [21,23,24]. These methods can provide high efficiency optimized for particular models and data distributions, but additional preprocessing and calibration may be required when they are applied to pretrained models or other input distributions. In contrast, this study aims to constrain the sign and occurrence condition of multiplication errors within the hardware and apply the same local compensation rule to every operation without separate software modification. Therefore, the main objective of this study is not merely to reduce error for a particular workload, but to explicitly control the relationship among error generation, detection, and compensation at the circuit level.

In the common-BF16 evaluation, the Proposed scheme exhibits lower Layer NRMSE and Logit NRMSE than the Baseline, DIMC-S-derived, and LSAC OR+SXAFA-derived schemes in all six model–dataset combinations, with the same trend observed across the layer-call NRMSE distributions. However, because the Top-1 difference relative to the Baseline remains within −0.02 to +0.12 percentage points, the numerical-error reduction is not interpreted as a general improvement in inference accuracy. The DIMC-S-derived and LSAC OR+SXAFA-derived results represent mechanism-level functional comparisons under the common BF16 workload.

The Proposed approximation–detection–compensation structure does not necessarily guarantee simultaneous improvements in area, power, and delay. The error-detection and compensation paths can introduce additional logic, wiring, and critical-path overhead [14,15,16,20]. At TT/1.0 V/25 °C, the Proposed local pair-arithmetic delay is 54.602 ps compared with 46.589 ps for the Baseline, an absolute increase of 8.013 ps and a relative increase of 17.20%. Across the five evaluated PVT conditions, the relative local delay overhead remains within 16.28–18.67%, with a maximum Proposed delay of 98.568 ps. These values characterize the local replacement boundary and are not measured complete-macro Fmax or throughput degradations. The published Baseline passing point of 205 MHz at 0.9 V [11] provides only a timing-scale reference: the nominal 8.013 ps increment is approximately 0.164% of the corresponding 4.878 ns clock period, and the Proposed design preserves the same three-cycle mantissa-processing schedule without adding a pipeline stage. Complete-macro critical-path timing, explicit next-stage loading, extracted routing parasitics, PVT-dependent power/energy, energy-delay product, and transistor-level Monte Carlo variation remain outside the direct measurement scope.

Despite these limitations, the directly measured local transistor count and average power are reduced by 14.81% and 28.56%, respectively, relative to the Baseline. The architecture-derived composition analysis further indicates an approximately 9.24% first-order hardware-cost reduction within the four-category composition reported for the published Baseline, but this value is an area proxy rather than a complete-macro post-layout measurement. The compensation is implemented by reusing the 1-bit flag in the existing carry path rather than by adding a separate multi-bit correction circuit; thus, the main benefit is the combined reduction in local circuit cost and BF16-referenced numerical distortion while maintaining inference accuracy comparable to the Baseline.

Future work should extend the current joint-design scope, which is limited to the multiplier and first adder stage, to the entire MAC datapath. For example, not only the approximate output value and the weight and position of the compensation bit, but also mantissa significance, adder-tree stage, accumulation depth, sign processing, and normalization could be included as joint exploration variables. It is also necessary to compare the current approach, which applies identical compensation at every position, with a selective approach that controls compensation according to the layer or cycle under the same hardware constraints. Such an extended exploration is not simply a matter of selecting the smallest multiplier or adder; rather, it must determine where errors should be introduced, through which signals they should be transferred, and at which stage they should be compensated to provide the most favorable balance between overall circuit cost and accuracy [17,19,25]. However, because the current results are limited to local arithmetic units in BF16 DCIM and CNNs based on CIFAR-10 and CIFAR-100, further verification is required to determine whether these design principles provide the same benefits in other MAC structures.

6. Conclusions

This study proposed an error-recoverable arithmetic structure that jointly approximates the 2-bit multiplier and first adder stage in BF16 digital compute-in-memory mantissa computation. The Proposed multiplier maps the exceptional 11 × 11 result to 0111, changing the Baseline error from +6 to −2 and fixing the product MSB to 0 so that the first-stage adder can be reduced from 4 bits to 3 bits. A lightweight flag detects the error-inducing condition and is directly reused in the existing bit-1 carry path to provide conditional compensation without a separate multi-bit correction circuit. Transistor-level evaluation of the common local arithmetic boundary showed 14.81% and 28.56% reductions in transistor count and average power, respectively, relative to the Baseline, while the nominal propagation delay increased by 17.20%; across the evaluated PVT conditions, the relative local delay overhead remained within 16.28–18.67%. The architecture-derived composition analysis gives an approximately 9.24% first-order hardware-cost proxy, which is not a complete-macro post-layout result. Under the common-BF16 evaluation, the Proposed scheme achieved the lowest Layer NRMSE and Logit NRMSE among the Baseline, DIMC-S-derived, LSAC OR+SXAFA-derived, and Proposed schemes for all six ResNet18, VGG16-BN, and AlexNet model–dataset combinations on CIFAR-10 and CIFAR-100. The Top-1 accuracy difference relative to the Baseline remained within −0.02 to +0.12 percentage points. Therefore, the Proposed structure provides a balanced hardware–accuracy design point that reduces local circuit cost and BF16-referenced numerical distortion while maintaining inference accuracy comparable to the Baseline, without retraining or data rearrangement. Future work should include post-layout parasitics, flag-routing load, complete-macro timing and energy evaluation, and an extended joint-design exploration covering higher adder-tree stages.