Reachability Analysis Method Using Abstraction and Refinement of Priced Probabilistic Timed Automaton and Its Application for Design Verification of Wireless Sensor Networks
Abstract
1. Introduction
- Regarding the expressive power of the model, there are differential equations that include time, probability, and cost, as well as combinations thereof; costed probabilistic timed automata possess the strongest expressive power but are complex.
- State reduction techniques include partial order reduction, symmetry reduction, and compositional methods that capture the structural characteristics of the system, as well as general-purpose symbolic model checking, abstraction refinement, bisimulation minimization, and approximation methods. In this research, focusing on simplifying and verifying complex costed stochastic temporal automata, we achieve rigorous verification of reachability for costed probabilistic timed automata using a model checking method that extends symbolic model checking with abstraction refinement.
- APMC (Approximate Probabilistic Model Checker) is a distributed model checker for fully probabilistic systems that uses a client/server computation model to distribute path generation and formula verification on a cluster of workstations [11]. The APMC approach uses an efficient Monte-Carlo method to approximate satisfaction probabilities of monotone properties over fully probabilistic transitions systems. The properties to be checked are expressed in LTL (Linear Temporal Logic). This study offers greater model expressiveness and verification capabilities than APMC; however, while it verifies reachability, its verification capabilities regarding temporal properties are inferior to those of APMC. Nevertheless, this study can verify reachability that incorporates temporal constraints, probability, and cost.
- Fortuna is the first and only tool for model checking priced probabilistic timed automata (PPTAs) [12]. Fortuna can handle the combination of real time, probabilistic and cost features. This is required to address key design trade-offs that arise in many practical applications such as the Zeroconf, Bluetooth, IEEE802.11 and Firewire protocols, protocols for sensor networks, and scheduling problems with failures. PPTAs are an extension of probabilistic timed automata (PTAs) with cost-rates and discrete cost increments on states [13]. Fortuna is able to compute the maximal probability by which a state can be reached under a certain cost-bound (and time-bound). This study presents an evolution of Fortuna using CEGAR to reduce the number of states.
- We perform predicate abstraction on both cost and time constraints simultaneously.
- Using the counterexample analysis method, we determine whether the counterexamples obtained by cost-bounded maximal probability reachability analysis on the abstract structure exist on the concrete structure or not. A counterexample analysis consists of two parts: path counterexample analysis and simultaneous execution counterexample analysis. A path counterexample analysis is performed to check whether the extracted counterexamples are executable on the corresponding real systems. On the other hand, a simultaneous execution counterexample analysis is performed to check whether the elements of those counterexamples can be executed according to the same adversary.
2. Priced Probabilistic Timed Automaton
2.1. Preliminaries of Priced Probabilistic Timed Automaton
2.2. Syntax of a Priced Probabilistic Timed Automaton
- L is a finite set of locations.
- is the initial location.
- is a finite set of clocks.
- is a function that assigns an invariant condition to each location.
- is a finite set of probabilistic transition relation.
- is s function that assigns a cost slope to each location.
2.3. Semantics of a Priced Probabilistic Timed Automaton
- is a set of states,
- is the initial state,
- is a timed probabilistic transition relation.
- Timed transition from state to t unit time:
- Discrete transition from state by probabilistic transition relation to:
3. Cost-Bounded Maximal Probability Reachability Analysis
4. Predicate Abstraction and Refinement
- We perform predicate abstraction on both cost and time constraints simultaneously.
- Using the counterexample analysis method, we determine whether the counterexamples obtained by cost-bounded maximal probability reachability analysis on the abstract structure exist on the concrete structure or not. A counterexample analysis consists of two parts: path counterexample analysis and simultaneous execution counterexample analysis. A path counterexample analysis is performed to check whether the extracted counterexamples are executable on the corresponding real systems. On the other hand, a simultaneous execution counterexample analysis is performed to check whether the elements of those counterexamples can be executed according to the same adversary.
4.1. Predicate Abstraction
4.2. Cost-Bounded Maximal Probability Reachability Analysis on Abstract Structure
4.3. Counterexample Analysis Method
4.3.1. Preliminaries
- operation: timed transition operationThe operation calculates the MP zones that are available for timed transitions to a given MP zone. The operation calculates the MP zones from which timed transitions are possible from a given MP zone. Note that the operation is defined in Definition 8.
- operation: discrete transition operationThe operation calculates the MP zones that can be transitioned to by discrete transitions to a certain MP zone. The operation calculates the MP zones that can be transitioned from a given MP zone by discrete transitions.
4.3.2. Counterexample Analysis
(Path Counterexample Analysis)
| Algorithm 1 Path counterexample analysis (Backward counterexample analysis) |
|
- (1)
- If the starting condition is (line 7), we consider this path to be a false counterexample (line 8) and divide and the MP zone that can transition from to .
- (2)
- Next, since it is considered that there are abstract and hidden timed transitions on the abstract state, we obtain the arrival condition (line 16) by the operation.
(Simultaneous Execution Counterexample Analysis)
- (1)
- First, we take one path from the set that has the common part of all paths and perform assignments true to its starting condition and reaching condition , which are initialized by assigning true (line 2–4). Let be the initial condition of arrival (line 6).
- (2)
- Next, starting from the one with the smallest length of the common part (line 7), the arrival and departure conditions are sequentially obtained.
- (a)
- In the reachability condition, for each path of the candidate counterexamples (line 8), we take the product of the reachability condition of the common part and the reachability condition of that path , which is the arrival condition of the path (line 10).
- (a-1)
- If the product is false, it is a false counterexample because it indicates that there is no common path on the timed probability system and outputs a predicate that splits and (line 11).
- (a-2)
- If the products not false, this product is newly set as the arrival condition of the common part (line 13), and then the time-transferable starting condition is obtained from this arrival condition (line 14).
- (b)
- Next, for each path of the candidate counterexamples (line 17), we similarly take the product of the starting condition of the common part and the starting condition of that path , which is the starting condition of the path (line 19).
- (b-1)
- If the product is false, we similarly judge it to be a false counterexample and output the predicate that splits and (line 20).
- (b-2)
- If the product is not false, this product is the new starting condition for the common part (line 22). Furthermore, from these starting conditions, we obtain the arrival conditions under which timed transitions and discrete transitions are possible (line 23–26). If the arrival and departure conditions are not false for all common parts, we can say that all paths can be executed by at least one adversary. In other words, we can say that the counterexample exists, so the “Reachable”, which is the solution of exists and verification, is output (line 31), and the verification is terminated.
4.4. Refinement
4.4.1. Path Counterexample Analysis
| Algorithm 2 Simultaneous execution counterexample analysis (forward counterexample analysis) |
|
4.4.2. Simultaneous Execution Counterexample Analysis
5. Priced Probabilistic Timed CEGAR
5.1. Overview
- Initial Abstraction:From a priced probabilistic timed automaton and a verification problem , we construct a timed probabilistic system and an initial predicate set , from which we construct an initial abstract structure from them.
- Reachability Analysis:Compute the maximum reachability probability to the target state on .
- Counterexample Analysis:For each element of the counterexample that has reached the target state by 2. reachability analysis, analyze whether it is reachable on the concrete structure by path counterexample analysis and simultaneous execution counterexample analysis.
- Refinement:From the results of 3. Counterexample Analysis, we obtain a set of predicates that partitions the abstract state so that there are no counterexamples obtained by 2. Reachability Analysis.
- Abstraction:From the set of predicates to which the predicate is added, we obtain a new abstract structure .
- Return to 2. Reachability Analysis.
5.2. Verification Example by Priced Probabilistic Timed CEGAR
5.3. Empirical Experiments and Discussions
- From Figure 10, it can be seen that the computation time and the memory used for verification increase exponentially with the number of CEGAR verification loops. The exponential increase may be due to the effect of the quantifier elimination ([19]) used in the implementation of the state set operation.
- Also, from Figure 11, the number of states shows a linear increase. Considering that the number of states of the finite state graph equivalent to the priced-removed probabilistic timed automaton is , which is multiplied by the number of states of the priced-added probabilistic timed automaton, the effect of state reduction is considered sufficient.
- The BOOST C++ Libraries. Fortuna only depends on header files from BOOST.
- The Parma Polyhedra Library (PPL version 0.10). A pre-compiled version is available for Linux.
- The GNU Multiple Precision Arithmetic Library, libraries gmp and gmpxx. These libraries are already installed on standard Linux distributions. They are needed only by PPL.
- The lp solve library version 5.5.
5.4. Discussion of Theoretical Aspects
6. Conclusions
Funding
Institutional Review Board Statement
Informed Consent Statement
Data Availability Statement
Acknowledgments
Conflicts of Interest
References
- Bohnenkamp, H.; van der Stok, P.; Hermanns, H.; Vaandrager, F. Cost-optimization of the ipv4 zeroconf protocol. In Proceedings of the International Conference on Dependable Systems and Networks, San Francisco, CA, USA, 22–25 June 2003; pp. 531–540. [Google Scholar]
- Berendsen, J.; Gebremichael, B.; Vaandrager, F.W.; Zhang, M. Formal specification and analysis of zeroconf using uppaalS. ACM Trans. Embed. Comput. Syst. 2011, 10, 34. [Google Scholar] [CrossRef]
- Katoen, J.P.; Jansen, D.N.; Berendsen, J. Probably on time and within budget on reachability in priced probabilistic timed automata. In Proceedings of the Third International Conference on the Quantitative Evaluation of Systems—(QEST’06), Riverside, CA, USA, 11–14 September 2006; pp. 311–320. [Google Scholar]
- Clarke, E.M.; Grumberg, O.; Jha, S.; Lu, Y.; Veith, H. Counterexample-guided abstraction refinement for symbolic model checking. J. ACM 2003, 50, 752–794. [Google Scholar] [CrossRef]
- Yamane, S.; Shimizu, T. Development of probabilistic timed CEGAR. In Proceedings of the 2014 2nd International Conference on Systems and Informatics (ICSAI 2014), Shanghai, China, 15–17 November 2014; pp. 482–491. [Google Scholar]
- Mouradian, A.; Auge-Blum, I. Modeling local broadcast behavior of wireless sensor networks with timed automata for model checking of WCTT. In Proceedings of the 2nd International Workshop on Worst-Case Traversal Time, San Juan, PR, USA, 4 December 2012; pp. 23–30. [Google Scholar]
- Zhang, F.; Bu, L.; Wang, L.; Zhao, J.; Chen, X.; Zhang, T.; Li, X. Modeling and Evaluation of Wireless Sensor Network Protocols by Stochastic Timed Automata. Electron. Notes Theor. Comput. Sci. 2013, 296, 261–277. [Google Scholar] [CrossRef]
- Ju, H.; Zhang, R. Throughput Maximization in Wireless Powered Communication Networks. IEEE Trans. Wirel. Commun. 2013, 13, 418–428. [Google Scholar] [CrossRef]
- Santi, P. Topology Control in Wireless Ad Hoc and Sensor Networks. ACM Comput. Surv. 2005, 37, 164–194. [Google Scholar] [CrossRef]
- Clarke, E.M.; Henzinger, T.A.; Veith, H.; Bloem, R. Handbook of Model Checking; Springer: Berlin/Heidelberg, Germany, 2018. [Google Scholar]
- APMC: Approximate Probabilistic Model Checker. Available online: https://github.com/ix-labs/apmc (accessed on 9 May 2026).
- The Fortuna Model Checker. Available online: https://www.cs.ru.nl/J.Berendsen/fortuna/ (accessed on 10 May 2026).
- Berendsen, J.; Jansen, D.N.; Vaandrager, F.W. Fortuna: Model Checking Priced Probabilistic Timed Automata. In Proceedings of the 2010 Seventh International Conference on the Quantitative Evaluation of Systems, Williamsburg, VA, USA, 15–18 September 2010; pp. 273–281. [Google Scholar]
- Yamane, S. Specification and Verification Method of Parallel Hierarchical Timed Automata by Predicate Abstraction and Refinement. IEEE Access 2025, 13, 90017–90033. [Google Scholar] [CrossRef]
- Yamane, S.; Kamide, H.; Wu, Y. Verifying Reachability with Real-Time Properties of Embedded Assembly Programs Based on Lazy Abstraction and Refinement. IEEE Access 2025, 13, 207987–208006. [Google Scholar] [CrossRef]
- Kwiatkowska, M.; Norman, G.; Sproston, J.; Wang, F. Symbolic model checking for probabilistic timed automata. Inf. Comput. 2007, 205, 1027–1077. [Google Scholar] [CrossRef]
- Moller, M.O.; Rues, H.; Sorea, M. Predicate Abstraction for Dense Real-Time Systems. Electron. Notes Theor. Comput. Sci. 2002, 65, 1–30. [Google Scholar] [CrossRef]
- Han, T.; Katoen, T.J.P. Counterexamples in probabilistic model checking. In LNCS 4424; Springer: Berlin/Heidelberg, Germany, 2007; pp. 72–86. [Google Scholar]
- Quantifier Elimination. Available online: https://mathworld.wolfram.com/QuantifierElimination.html (accessed on 10 May 2026).











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Yamane, S. Reachability Analysis Method Using Abstraction and Refinement of Priced Probabilistic Timed Automaton and Its Application for Design Verification of Wireless Sensor Networks. Electronics 2026, 15, 2366. https://doi.org/10.3390/electronics15112366
Yamane S. Reachability Analysis Method Using Abstraction and Refinement of Priced Probabilistic Timed Automaton and Its Application for Design Verification of Wireless Sensor Networks. Electronics. 2026; 15(11):2366. https://doi.org/10.3390/electronics15112366
Chicago/Turabian StyleYamane, Satoshi. 2026. "Reachability Analysis Method Using Abstraction and Refinement of Priced Probabilistic Timed Automaton and Its Application for Design Verification of Wireless Sensor Networks" Electronics 15, no. 11: 2366. https://doi.org/10.3390/electronics15112366
APA StyleYamane, S. (2026). Reachability Analysis Method Using Abstraction and Refinement of Priced Probabilistic Timed Automaton and Its Application for Design Verification of Wireless Sensor Networks. Electronics, 15(11), 2366. https://doi.org/10.3390/electronics15112366

