A Design Methodology for RF/mmWave LNAs in 22 nm FD-SOI with Cross-Coupling-Aware Nested Inductors and On-Chip Baluns

Abstract

In this work, a layout-level design methodology is presented for Low-Noise Amplifiers (LNAs), targeting a wide frequency spectrum from RF to millimeter-wave (mmWave) bands, and implemented using a 22 nmFDSOI CMOS process. A nested inductor structure is introduced at RF frequencies to reduce silicon footprint, with magnetic crosstalk effects characterized through electromagnetic (EM) simulations using Ansys^® RaptorX, Release 2024 R2, ANSYS, Inc. and integrated into the design process. Single-ended LNA architectures are employed for RF bands, while at mmWave frequencies, a differential topology is adopted to enhance linearity and enable simultaneous input and output impedance matching. An EM-based verification flow is applied across all designs to ensure RF/mmWave design flow compatibility, simulation accuracy, and enhanced performance. The proposed designs are evaluated using key metrics including input/output matching, reverse isolation, forward gain, noise figure, linearity ($I{P}_1,I{P}_3$), stability factor, power consumption, and total chip area to quantify the efficiency of the proposed methodology. The simulation results demonstrate that nested inductors are highly effective for area reduction in RF LNAs, while differential topologies are more suitable for mmWave designs, providing a unified framework for area-efficient and high performance LNA implementation.

1. Introduction

The rapid growth of wireless communication technologies, fueled by the rise of 5G, emerging 6G standards, and the widespread adoption of IoT, has created a strong demand for highly integrated transceiver modules. At present, almost every modern electronic device—from smartphones and wearables to industrial sensors and automotive radar systems—requires an RF front-end capable of reliable wireless communication. In a typical receiver chain, the Low-Noise Amplifier (LNA) is a critical building block, as it amplifies the extremely weak signal captured by the antenna while introducing minimal additional noise. This ensures that the signal level is sufficient for proper processing by subsequent stages such as mixers and analog-to-digital converters, as presented in Figure 1.

The rising cost of silicon fabrication has made layout area optimization a critical design factor, as production cost scales directly with chip area. This is particularly important for LNAs, since on-chip passive devices such as inductors occupy a large portion of the layout [1]. Moreover, LNAs support a wide range of operating frequencies, from low RF bands used in communication protocols such as Zigbee, Bluetooth, and Wi-Fi, to the mmWave frequencies required for future high-data-rate 6G applications [2]. At these operating frequencies, layout parasitics have a significant impact on circuit performance, affecting impedance matching, forward gain, and even stability. This makes the use of electromagnetic (EM) extraction tools essential for accurately modeling passive devices and their interconnects [3].

This work addresses these challenges through a comprehensive layout-level design and verification framework for LNAs. At RF frequencies, a nested inductor structure is introduced to reduce silicon area while quantifying the magnetic coupling between inductors. For mmWave operation, a differential LNA employing on-chip baluns is designed using the methodological approach outlined in a machine learning-based automation framework [4] to achieve optimized performance. Finally, an EM-based verification approach is utilized [5] to ensure consistency between schematic and layout across all designs. The methodology is validated through a complete set of performance metrics, demonstrating that the proposed approach enables area-efficient and reliable LNA design from RF to mmWave applications [6,7].

2. Analytical Framework of LNA Topologies and Electromagnetic Crosstalk Characterization

Two distinct LNA topologies were adopted to address different frequency bands, each offering unique advantages. At RF frequencies, a single-stage cascode architecture with inductive degeneration was selected, as depicted in Figure 2, owing to its design simplicity and well established analytical foundation [8,9,10].

For mmWave frequencies, a differential topology was adopted, employing on-chip baluns for impedance matching and capacitive cross-coupling networks to neutralize parasitic gate-to-drain capacitances [11]. The design parameters were derived using the methodology introduced in the machine learning-based framework [4], which provided systematic parameter optimization and reduced the overall design effort.

2.1. Single-Ended Cascode LNA with Inductive Load and Source Degeneration

The cascode common-source topology is widely employed in RF LNA design due to its combination of high gain, input-output isolation, and favorable high-frequency behavior. The isolation provided by the cascode device suppresses the Miller effect, preventing the gate-drain capacitance ($C_{gd}$) of the input transistor ($M_1$) from being multiplied by the stage gain. Without this configuration, the effective input capacitance would increase significantly, making impedance matching and stable operation nearly impossible [12]. In the following subsections, a detailed small-signal analysis of the input and output impedance is presented, followed by gain characterization and an evaluation of the noise figure performance of the proposed design.

2.1.1. Small-Signal Input/Output Impedance and Gain Characterization

The small signal input impedance of the amplifier can be expressed as:

$$Z_{in}={\displaystyle \frac{g_{m\left(M1\right)}{L}_s}{C_{gs}}}+i\left[\omega (L_s+L_g)-{\displaystyle \frac{1}{\omega C_{gs}}}\right]$$

(1)

where $g_{m\left(M1\right)}$ is the transconductance of the input transistor, $L_s$ is the source degeneration inductor, $L_g$ is the gate inductor, $C_{gs}$ is the intrinsic gate-to-source capacitance, and $\omega$ is the input signal frequency [8,9]. This relation highlights the dual role of source degeneration, tuning the real part of the impedance through $g_{m1}{L}_s$ while providing flexibility in imaginary part compensation.

The output impedance arises from the parallel combination of the cascode device resistance, the load inductor, and the output capacitance, which together form a frequency-selective high impedance:

$$Z_{out}=g_{m\left(M2\right)}{r}_{0\left(M1\right)}{r}_{0\left(M2\right)}\left|\right|{\displaystyle \frac{1}{i\omega C_{gs}}}\left|\right|i\omega L_d$$

(2)

where $g_{m\left(M2\right)}$ is the transconductance of the cascode transistor; $r_{0\left(M1\right)}$ and $r_{0\left(M2\right)}$ are the output resistances of the transistors $M_1$ and $M_2$; and $L_d$ is the load inductor [8,9]. Unlike a resistive load, the inductor sustains negligible DC voltage drop, preserving voltage headroom [12]. Moreover, the equivalent series resistance of the inductor allows fine tuning of the real part of the output impedance, while additional capacitive loading at the output node provides an extra degree of tuning flexibility. The overall voltage gain can be expressed as:

$$A_v=g_{m\left(M1\right)}·Z_{out}$$

(3)

It should be noted that this expression assumes an ideal inductor. In practice, the finite quality factor of the inductor introduces an equivalent parallel resistance, which contributes to the real part of $Z_{out}$ and slightly degrades the achievable gain. In this configuration, a capacitor may be added in parallel with the load inductor to provide output matching, as illustrated in Figure 3, where the equivalent parallel resistance of $L_d$ is also depicted. In this case, the equivalent output impedance of the circuit can be expressed as:

$$Z_{out}^{\prime }=g_{m\left(M2\right)}{r}_{0\left(M1\right)}{r}_{0\left(M2\right)}\left|\right|{\displaystyle \frac{1}{i\omega C_{gs}}}\left|\right|i\omega L_d\left|\right|{\displaystyle \frac{1}{i\omega C_L}}\left|\right|R_p$$

(4)

where $C_L$ is the load capacitor and $R_p$ represents the effective parallel resistance. In practice, $R_p$ accounts for the finite quality factor of the inductor as well as any additional resistive elements introduced in parallel at the output node.

2.1.2. Noise Figure Evaluation

Maintaining a low noise figure performance ($NF$) is of paramount importance, since the input signal is typically very weak. The noise figure is defined as the degradation in signal-to-noise ratio ($SNR$) from the input to the output of the amplifier:

$$NF={\displaystyle \frac{SN{R}_{in}}{SN{R}_{out}}}$$

(5)

A higher NF implies that the circuit introduces additional noise on top of the already weak input signal, which can severely compromise the sensitivity of the receiver. The active devices in the amplifier are the dominant noise contributors, and their impact depends strongly on biasing and device geometry. In MOSFETs, there exists a specific bias point at which the device generates the minimum possible noise contribution. This “sweet spot” is determined by both the transistor dimensions (W/L) and the operating current density. Physically it corresponds to the condition where the trade-off between thermal channel noise and induced gate noise is optimized [13].

The noise figure of an amplifier can be separated into two contributions: a term that depends only on the device technology and biasing conditions, and a term that is affected by the source impedance presented to the circuit. The first term ($N{F}_{min}$) represents the lowest achievable noise figure of the device, while the second quantifies the penalty introduced when the source admittance deviated from the optimum value [14].

$$NF=N{F}_{min}+{\displaystyle \frac{R_n}{G_s}}{|Y_s-Y_{s,opt}|}^2$$

(6)

where $R_n$ is the equivalent noise resistance, $G_s$ is the source conductance, $Y_s$ is the source admittance, and $Y_{s,opt}$ is the optimum source admittance for minimum noise. When the source is tuned such that $Y_s=Y_{s,opt}$, the matching dependent term vanishes, and the noise performance is determined solely by $N{F}_{min}$. By evaluating the $N{F}_{min}$ parameter across different sizing options for the input transistor $M_1$ and the biasing device $M_3$, together with adjustments of the reference resistor $R_{ref}$ that controls the current in the bias branch, the active device dimensions can be optimized directly for minimum noise [9].

The resistor $R_1$ contributes to raising the input impedance, while the input coupling capacitor isolates the DC bias point of the core transistor ($M_1$) from the antenna’s $50 \mathrm{\Omega }$ source. The output impedance is typically not matched to $50 \mathrm{\Omega }$ but rather to the subsequent mixer stage [15]. For this reason, $C_2$ is often treated as an external matching element rather than a fundamental part of the LNA topology.

2.2. Single-Stage Differential LNA with Transformer-Based Impedance Matching

As shown in Figure 4, the proposed topology consists of a single-stage differential LNA that employs balanced-to-unbalanced transformers at both the input and output nodes.

This architecture was selected not only for the inherent advantages of a differential design, such as improved linearity and common-mode noise rejection, but also because an established automated framework exists in the literature [4] for determining its design parameters. The availability of this framework allows for a more systematic and reliable selection of component values, ensuring accurate impedance matching using fully integrated on-chip passive elements without the need for external networks.

2.2.1. Impedance Matching Networks Analysis

This topology shares many similarities with the single-ended LNA discussed in the previous section, with the key difference being the absence of the source degeneration inductor $L_{deg}$. In this design, the use of balanced-to-unbalanced transformers and coupling capacitors allows the input and output impedances to be tuned independently, eliminating the need for source degeneration. The input matching network consists of the input coupling capacitor $C_{in}$ and the input balun, while the output matching network is formed by capacitors $C_1$ and $C_2$ in combination with the output balun. To fully optimize the matching, parametric sweeps of these design variables are carried out and evaluated using Smith Chart visualizations as presented in Figure 5 [16].

For the input stage, a stacked balun is employed to achieve impedance matching, as further explained in a later section. Sweeping the inner diameter of the input balun at the specific frequency of interest, adjusts the real part of the input impedance $Z_{in}$, aligning it with 50 $\mathrm{\Omega }$. This corresponds to the center of the Smith Chart, which is normalized to the antenna source impedance, typically $50 \mathrm{\Omega }$. In a stacked configuration, the inner diameter is the sole parameter governing the primary and secondary inductances ($L_p$ and $L_s$), and thereby the input matching. Turn spacing is inherently absent due to the vertical stacking, while the turn width is maximized to reduce parasitic resistance and sustain a high Q factor. Once the real part is fixed, sweeping the input coupling capacitor $C_{in}$ is used to tune the imaginary part of $Z_{in}$ to zero, ensuring complete impedance matching at the input.

$$for Re\left(Z_{in}\right)=50 \mathrm{\Omega } \to ID sweep$$

(7)

$$for Im\left(Z_{in}\right)=0 \mathrm{\Omega } \to C_{in} sweep$$

(8)

where $ID$ is the inner diameter of the input transformer.

A similar procedure is applied to the output impedance $Z_{out}$. For a fixed inner diameter of the output balun, capacitor $C_1$ is swept to set the real part of $Z_{out}$ to $50 \mathrm{\Omega }$, while capacitor $C_2$ is adjusted to cancel the imaginary part, driving it to zero.

$$for Re\left(Y_{out}\right)={\displaystyle \frac{1}{50}} {\mathrm{\Omega }}^{-1} \to C_1 sweep$$

(9)

$$for Im\left(Y_{out}\right)=0 {\mathrm{\Omega }}^{-1} \to C_2 sweep$$

(10)

This sequential tuning process ensures that both the input and output impedances are precisely matched to their respective ports, enabling maximum power transfer and stable LNA operation.

2.2.2. Co-Optimization of Noise Figure and Layout Footprint

The noise figure ($NF$) of the differential LNA can be optimized using the same approach as in the single ended design, by targeting the minimum noise figure parameter, ($N{F}_{min}$) as expressed in (6). In this implementation, a fixed bias voltage $V_b$ is applied directly to the gates of the core transistors instead of employing a current mirror for bias generation, which simplifies the overall design. Therefore, achieving the optimal noise performance requires a parametric sweep of both the bias voltage $V_b$ and the sizing of the input transistors $M_1$ and $M_2$.

However, to fully exploit the noise optimization potential, the sizing ratio between the cascode transistor and the input device, defined as $W_{casc}/W_{inp}$ must also be carefully considered. The literature has shown that superior noise performance can be achieved when the cascode transistor width is three to four times larger than that of the input transistor [4]. While this configuration minimizes the $N{F}_{min}$, it significantly increases the overall layout footprint. Selecting a ratio of approximately two provides a good compromise, yielding low noise performance while maintaining a more compact chip area. This trade-off between noise figure improvement and silicon area efficiency must therefore be carefully balanced during the design process.

2.2.3. Gain Enhancement Through Cross-Coupled Neutralization

At RF and mmWave frequencies, the intrinsic gate-to-drain capacitance ($C_{gd}$) of MOSFET devices create a local feedback path from the drain nodes back to their gates. In differential CS LNAs the input signal is applied to those gates, leading to degradation of the amplifier’s gain and instability issues. This occurs because variations in the drain voltage are capacitively coupled back to the gate, unintentionally modulating the transistor’s input signal [17]. The neutralization technique introduces an external capacitance in such a way that it behaves as a negative capacitance, effectively canceling the intrinsic ($C_{gd}$). Although this is difficult to implement in single-ended topologies, it can be naturally realized in differential designs, where the two drain nodes naturally carry signals that are 180° out of phase. By cross-connecting a capacitor between the drain of each transistor and the gate of the opposite transistor, the voltage swing from one side is coupled into the opposite gate with inverted polarity. This inverted coupling produces an ac current that is equal in magnitude but opposite in direction to the feedback current generated by $C_{gd}$. As a result, the two effects cancel each other, and the net feedback capacitance approaches zero. This cancellation not only prevents gain loss but also improves stability, making this technique particularly advantageous for high-frequency differential LNA and PA designs where parasitic capacitances are dominant [18].

The effect described above can be clearly understood by constructing the small-signal equivalent circuit of the core transistors together with the cross-coupling capacitors, as illustrated in Figure 6.

The cross-coupled capacitors not only mitigate the stability issues introduced by the parasitic $C_{gd}$ but can also be utilized to enhance the amplifier’s gain. This behavior can be analyzed systemically through Y-parameter characterization. Three key metrics are employed in this analysis: the Maximum Available Gain ($G_{max}$), the Maximum Stable Gain ($G_{msg}$) and the Rollet’s Stability Factor ($k_f$). The parameter $G_{max}$ represents the maximum power gain achievable when both the input and output of the device are simultaneously matched for maximum power transfer and is expressed as [11,19]:

$$G_{max}={\displaystyle \frac{|Y_{21}-Y_{12}{|}^2}{4R\left(Y_{11}\right)R\left(Y_{22}\right)-R\left(Y_{12}\right)R\left(Y_{21}\right)}}=G_{msg}(k_f-\sqrt{K_f^2-1})$$

(11)

In contrast, $G_{msg}$ corresponds to the highest gain attainable while ensuring the circuit remains stable, without necessarily achieving simultaneous matching at both ports and is expressed as [19,20]:

$$G_{msg}={\displaystyle \frac{|Y_{21}|}{|Y_{12}|}}=\sqrt{{\displaystyle \frac{g_m^2}{{\omega }^2(C_{gd}-C_n)}}+1}$$

(12)

where $g_m$ is the transconductance of the amplifier and $\omega$ the angular frequency of the input signal. Finally, the Rollet’s factor $K_f$ is a widely used stability metric that indicates whether the circuit is unconditionally stable ($K_f>1$) or conditionally stable ($K_f<1$) and is expressed as [19,20]:

$$K_f={\displaystyle \frac{2R\left(Y_{11}\right)R\left(Y_{22}\right)-R\left(Y_{12}{Y}_{21}\right)}{|Y_{12}{Y}_{21}|}}$$

(13)

As illustrated in Figure 7, the stability factor $k_f$ and the maximum stable gain $G_{msg}$ both reach their peak values when the neutralization capacitance $C_n$ is equal to the intrinsic $C_{gd}$, as Equation (12) indicates, corresponding to complete neutralization of the gate-to-drain parasitic capacitance. However, the figure also shows that $G_{max}$ continues to increase beyond this point as $C_n$ is further increased, up until $k_f$ approached unity. This indicates that over-neutralization can be employed to achieve additional gain improvement, provided that the design remains sufficiently far from the marginal stability region near $K_f=1$ [18]. Operating too close to this limit is undesirable, as even small variations in the input to output impedance can lead to oscillations and circuit instability.

2.3. Electromagnetic RLCk Extraction for Mutual Coupling and Parasitic Inductance Modeling

In the previous subsections, two different design methodologies of LNAs were introduced and analyzed. While these schematic-level approaches allow for efficient tuning and optimization of the amplifier’s performance, they do not fully capture the challenges encountered during the physical layout implementation of RF and mmWave circuits. At these higher frequencies, layout parasitics play a dominant role in determining the overall behavior of the system.

Standard RC extraction tools, commonly used in base-band and low-frequency analog circuits, are generally sufficient for modeling resistive and capacitive parasitic effects. However, in RF and mmWave designs that employ on-chip transformers and inductors, these tools are no longer adequate. The metal interconnects used to route signals to and from these passive components exhibit parasitic inductance, which increases with frequency and alters the circuit’s behavior. The reactance of an inductor is given by:

$$X_L=i2\pi fL$$

(14)

where f is the operating frequency and L is the inductance of the metal trace. As frequency increases, the reactance $X_L$, rises proportionally, meaning that even small lengths of metal routing can significantly impact the signal path [21]. This effect cannot be properly captured by standard RC extraction flows. In addition to unintended parasitic inductance, mutual coupling between adjacent interconnects and between the traces of multi-port components such as baluns and transformers must also be considered. This coupling is described by the mutual coupling coefficient k, defined and characterized as [22,23]:

$$k={\displaystyle \frac{M}{\sqrt{L_1{L}_2}}}=\sqrt{{\displaystyle \frac{Im\left(Z_{12}\right)·Im\left(Z_{21}\right)}{Im\left(Z_{11}\right)·Im\left(Z_{22}\right)}}}$$

(15)

where M is the mutual inductance between two inductors and $L_1$, $L_2$ are their self-inductances. A coupling factor of $k=0$ indicates no magnetic interaction, whereas $k=1$ represents perfect magnetic coupling. At high frequencies, nearby conductors can introduce non-negligible mutual inductance, which can alter impedance matching and degrade overall circuit performance.

While PCELL-based passive component models provided by the foundry are typically well-characterized and accurate on their own, they do not account for the custom routing interconnects implemented by the designer, as illustrated in Figure 8. Since these signal paths vary for each design, they must be explicitly included in the simulation environment to ensure proper prediction of the circuit’s performance. To demonstrate this necessity, the same inductor and its surrounding interconnects are extracted using two different methods: standard RC extraction and electromagnetic (EM) RLCk extraction using Ansys^® RaptorX, Release 2024 R2, ANSYS, Inc., Canonsburg, PA, USA [24]. To enable such comparisons, the key metrics of inductance L and quality factor Q are derived using Y-parameter measurements as commonly applies in passive component characterization. The inductance and quality factor can be directly extracted from the simulated input admittance using [23,25]:

$$L\left(f\right)={\displaystyle \frac{Im\left(\frac{1}{Y_{11}}\right)}{2\pi f}} Q={\displaystyle \frac{\omega L}{R}}=-{\displaystyle \frac{Im\left(Y_{11}\right)}{Re\left(Y_{11}\right)}}$$

(16)

where $\omega$ is the angular frequency, L is the inductance and R represents the series resistance of the inductor or interconnect path.

As illustrated in Figure 9, the standard RC extraction significantly underestimates the effects of parasitic inductance and mutual coupling, resulting in discrepancies in both Q and L when compared to the EM RLCk results. This highlights the necessity of incorporating EM-based extraction into the design flow to ensure accurate modeling and reliable tape-out of RF and mmWave circuits.

3. Magnetic Coupling Evaluation of Balun and Nested Inductor Structures

Balanced-to-unbalanced transformers—or baluns—are essential components in RF and mmWave front-end designs, particularly when interfacing single-ended sources, such as antennas, with differential circuits like Low Noise Amplifiers or Power Amplifiers [26]. Structurally, a balun consists of two tightly coupled inductors, whose strong magnetic interaction enables it to perform several functions. Its primary role is to convert a single-ended signal into two differential signals, while simultaneously providing impedance transformation between the source and the differential load. In practice, such perfect balance occurs only under ideal coupling conditions ($k=1$). Since antennas inherently operate as single-ended sources, the balun is typically placed at the very beginning of the LNA signal chain, where it plays a critical role in defining the input impedance of the receiver front end. Through Smith Chart analysis, the behavior of the balun can be characterized and the required matching network can be systemically designed to ensure maximum power transfer and proper impedance transformation for the overall system [27].

This functionality is achieved through strong magnetic coupling between the transformer windings. In baluns, the mutual coupling coefficient between k is intentionally designed to be as high as possible to maximize power transfer and achieve efficient impedance matching. Using Y-parameter characterization (Equations (15) and (16)) the behavior of a balun can be described in terms of its self-inductances $L_1$, $L_2$ and the mutual inductance M, as depicted in Figure 10.

In contrast, the nested inductor structure introduced in this work is designed with the opposite goal: to minimize magnetic coupling between two independent inductors, as illustrated in Figure 11. In many analog and RF circuits, particularly single-ended LNAs, inductors are among the largest area-consuming components on silicon [28,29,30]. Placing two conventional inductors side by side consumes a substantial amount of Silicon area, limiting integration density, and increasing cost. The nested configuration addresses this issue by placing one inductor physically inside the other, with the smaller inductor positioned at the center of the larger one. In nested inductor structures, compliance with the respective DRC rules of the selected process is required, while careful spacing between windings ensures electromagnetic isolation and reduces the mutual coupling coefficient k to a negligible level. This design strategy allows both inductors to maintain their independent electrical characteristics slightly altered, while reducing overall occupied silicon area.

Although baluns and nested inductor structures are both composed of two inductors and can be described using the same characterization framework, they serve entirely different purposes in RF design. Baluns are intentionally designed with a high coupling coefficient k to enable efficient single-ended to differential signal conversion, while nested inductor configurations are optimized to minimize magnetic coupling, allowing two inductors to operate independently while significantly reducing the silicon area required. By suppressing coupling rather that exploiting it, the nested structure provides a practical solution for area-constrained RFIC designs where inductors traditionally occupy the largest proportion of chip area.

To provide a unified view of how the above structures are incorporated into the complete LNA development flow, Figure 12 summarizes the proposed EM-aware design methodology adopted in this work.

The flowchart serves as an overview of the design choices that follow in the next sections, highlighting the different paths taken depending on whether the target operation frequency lies in the RF or the mmWave range, and clarifies how each passive structure is employed within the corresponding branch.

For RF operation, the methodology begins with a schematic-level single-ended LNA design, followed by EM extraction of all passive circuitry and iterative re-tuning under layout-dependent parasitics. In this branch, the nested inductor structure is introduced when the area targets cannot be met using separate inductors, and its EM-extracted inductance and quality-factor values are used to re-optimize the circuit while simultaneously satisfying both electrical and area constraints.

For mmWave operation, the methodology proceeds through a differential schematic design employing ideal baluns—structures that exploit strong mutual coupling. In this branch, the balun is the key passive structure, and the ideal model is subsequently replaced by its EM-characterized counterpart; the circuit is then re-tuned using the updated primary and secondary inductances and their associated quality factors, ensuring that performance and area specifications are met under realistic electromagnetic conditions.

4. Nested Inductor Implementation in Single-Ended LNAs

To validate the proposed methodology, this section focuses on its application to three single-ended LNA designs targeting different frequency bands of 2.4 GHz, 5 GHz and 10 GHz. The selection of these three frequency bands is motivated by their relevance in modern wireless communications systems, as they encompass both low-GHz applications, and higher-frequency RF front end scenarios [31,32]. By spanning a wide frequency range, the methodology is validated not only in the context of compact, low frequency designs, but also under conditions where passive device parasitics become increasingly dominant. This way, the evaluation provides insight into how the proposed nested inductor concept scales with frequency, and whether its advantages in area reduction and isolation can be consistently maintained. Furthermore, the sequential analysis enables a clear distinction between the direct effect of nesting, observed prior to re-tuning, and the performance improvements achieved once the design is fully optimized. For each frequency, three layout variants are implemented:

• a standard layout following conventional design practices,
• a nested inductor layout to evaluate the direct impact of magnetic coupling reduction on circuit performance, and
• an optimized inductor layout where the circuit is re-tuned after EM extraction to fully exploit the benefits of compact structure.

This step-by-step comparison highlights the effect of the proposed structure on key performance metrics, providing a comprehensive evaluation of the methodology under different operating conditions.

4.1. Standard and Nested LNA Designs

Following the LNA design methodology described in [9], the initial design parameters were derived to ensure adequate performance across three representative operating frequencies −2.4 GHz, 5 GHz, and 10 GHz-covering low, mid, and high RF bands. These frequencies allow the evaluation of the methodology under different inductance values, matching conditions, and passive sensitivities. Post-layout simulations were performed using the Ansys^® RaptorX, Release 2024 R2, ANSYS, Inc. RLCk extraction tool. For the 2.4 GHz design, a parallel RC network was added across the inductive load to tune the output impedance to 50 $\mathrm{\Omega }$, a step taken solely for optimization and evaluation. For the 5 GHz and 10 GHz LNAs, no output matching was applied, as their outputs were intended to directly interface with subsequent blocks. The final design parameters for all three frequencies are listed in

Table 1. Design parameters for the single-ended LNAs across different operating frequencies.

Design Parameter	2.4 GHz	5 GHz	10 GHz
$V_{DD}$	0.8 V	0.8 V	0.8 V
${(W/L)}_{M1}$	400/0.07 μm	80/0.07 μm	60/0.07 μm
${(W/L)}_{M2}$	400/0.04 μm	400/0.07 μm	400/0.07 μm
${(W/L)}_{M3}$	16/0.07 μm	20/0.07 μm	5/0.02 μm
$L_d$	1.4 nH	1.1 nH	0.9 nH
$L_{deg}$	78 pH	33 pH	89 pH
$L_g$	9.6 nH	7.5 nH	2.9 nH
$R_{ref}$	210 $\mathrm{\Omega }$	65 $\mathrm{\Omega }$	60 $\mathrm{\Omega }$
$R_1$	5.1 k$\mathrm{\Omega }$	1.3 k$\mathrm{\Omega }$	3.6 k$\mathrm{\Omega }$
$R_{out}$	70 $\mathrm{\Omega }$	—	—
$C_{out}$	2.4 pF	—	—

.

After confirming through post-layout simulations that the standard designs for each frequency band operated effectively and met industry-standard performance, the nested inductor configuration was subsequently implemented without altering any design parameters. In this step, the source degeneration inductor ($L_{deg}$) was embedded within the load inductor ($L_d$), resulting in a more compact structure. The placement of $L_{deg}$ was carried out at the geometric center of the $L_d$ layout. Positioning the smaller inductor within the central region of the larger structure ensures that the traces of the two inductors remain as distant as possible along their peripheries, thereby reducing the strength of magnetic coupling. Since the mutual coupling coefficient k decreases with increasing separation between current-carrying conductors, this arrangement effectively minimizes unwanted magnetic coupling while maintaining the compactness of the nested configuration. In this manner, the nested implementation balances the competing objectives of silicon area reduction and electromagnetic isolation. The corresponding layouts are shown in Figure 13 where subfigures (a)–(c) illustrate the 2.4 GHz, 5 GHz, and 10 GHz designs, respectively.

This implementation allowed for a direct evaluation of the impact of magnetic coupling and area reduction on circuit performance across different operating frequencies. All critical performance metrics of the three single-ended LNAs were evaluated for both the standard and nested implementations. It should be noted that all results presented in this study are obtained from full-wave EM simulations, where all passive structures and interconnects are EM-extracted, while the active devices are modeled using the hardware-characterized PCells provided by the PDK. These results are summarized in

Table 2. Simulated performance metrics of the single-ended LNAs before and after nesting.

Performance Metric	2.4 GHz		5 GHz		10 GHz
	Standard	Nested	Standard	Nested	Standard	Nested
Silicon Footprint (mm2)	0.063	0.045	0.045	0.024	0.035	0.022
$S_{11}$ (dB)	−33.8	−19.5	−24.7	−9.0	−45.0	−11.5
$S_{21}$ (dB)	14.5	13.5	15.2	13.4	13.1	10.9
$S_{12}$ (dB)	−48.1	−38.2	−47.4	−25.4	−38.6	−26.6
$S_{22}$ (dB)	−27.4	−17.0	−0.7	−0.5	−0.9	−2.3
Noise Figure (dB)	3.7	3.0	3.8	3.3	3.1	2.9
IP1 (dBm)	−15.2	−13.0	−16.0	−16.9	−15.4	−11.6
IP3 (dBm)	−6.2	−3.6	−9.0	−10.3	−7.5	−3.7
Power Dissipation (mW)	9.8	10.0	7.3	5.1	5.8	6.2

, where each frequency band includes two columns representing the performance before and after nesting. The metrics reported include the silicon footprint, S-Parameters ($S_{11} S_{21} S_{12} S_{22}$), noise figure ($NF$), 1 dB compression point ($IP1$), third-order intercept point ($IP3$), and power dissipation, providing a comprehensive view of the nesting impact on LNA performance.

The above results, indicate a consistent degradation in key small-signal parameters across all three designs when transitioning from the standard to the nested configuration. Specifically, the input matching ($S_{11}$) shows noticeable degradation for all frequency bands, with the 2.4 GHz design additionally exhibiting output matching ($S_{22}$) deterioration. Similarly, a reduction in forward gain ($S_{21}$) and reverse isolation ($S_{12}$) is observed in every case, reflecting the adverse impact of employing the nested inductor topology. Conversely, a slight improvement in the noise figure ($NF$) is consistently observed across all frequencies, suggesting a marginal benefit in terms of noise performance. In contrast, linearity metrics such as 1 dB compression point ($IP1$) and third-order intercept point ($IP3$) do not exhibit a clear trend, with variations depending on the specific design and frequency. Similarly, power dissipation remains largely inconsistent, showing no systematic correlation with the nesting approach. From an area-efficiency perspective, significant reductions in silicon footprint are achieved. The 2.4 GHz and 5 GHz LNAs each demonstrate approximately 0.02 mm² of area savings ($25\%$ and $45\%$, respectively), while the 10 GHz design achieves a more modest reduction of roughly 0.013 mm² ($40\%)$. These results highlight the trade-off between area efficiency and performance degradation, underscoring the need for the optimization methodology discussed in the following sections.

4.2. Impact of Nesting on Inductor Performance via Y-Parameter Analysis

In order to mitigate the performance degradation observed in the previous subsection, and to enable the design of efficient circuits using the proposed nested topology, it is essential to accurately characterize the inductors after nesting. Since the physical proximity of $L_d$ and $L_{deg}$ alters their electromagnetic coupling characteristics, their effective inductance and quality factor can no longer be assumed to match the values defined during the schematic-level design [33]. This characterization is performed through Y-parameter EM simulations, following the framework introduced in previous section, which allow the extraction of the frequency dependent inductance and quality factor for both the standard and nested configurations. The resulting comparison, illustrated in Figure 14, highlights the deviations in inductance and Q factor introduced by each nested implementation. It is observed that the discrepancies between the standard and nested configurations for both $L_d$ and $L_{deg}$ in terms of inductance and quality factor, remain minimal at RF frequencies. For all cases, significant deviations become evident only at higher frequencies, typically above 30 GHz, where the effects of magnetic coupling become more pronounced.

A key observation is the shift in self-resonance frequency [34,35]. In the standard configuration, the self-resonance of $L_{deg}$ occurs at very high frequencies for the 2.4 GHz, 5 GHz, 10 GHz implementations. By contrast, when nesting is applied, a pronounced deviation in the effective inductance occurs at approximately 30 GHz. At the same frequency, the quality factor also changes, yet it does not transition into negative values as would be expected for an inductor entering its capacitive region [36]. This indicates that the inductive and capacitive coupling between the nested inductors, introduces a parasitic resonance mechanism that shifts the inductance uncontrollably. Although the effect is less pronounced, a related trend is observed for $L_d$, where the self-resonance frequency is reduced in the nested case compared to the standalone inductor. This phenomenon is explained by the fact that magnetic coupling effectively increases the total inductance, while the associated parasitic capacitance remains constant, thus lowering the resonance frequency [37]. Regarding the quality factor (Q), the differences at RF frequencies are relatively small, since the equivalent series resistance of each metal trace remains essentially unchanged by the nesting process. Instead, the variations in Q arise from the change in effective inductance, as Equation (16) indicates [38]. However at mm-Wave frequencies, the deviations become significant, indicating that the nested topology has a stronger impact on the loss behavior of the inductors as frequency increases.

4.3. Optimization of Nested Inductor LNAs for Performance Enhancement

Following the evaluation of the performance degradation introduced by magnetic crosstalk in the nested configurations, a layout-level re-optimization process was undertaken to restore and enhance circuit performance. The updated design parameters are presented in

Table 3. Initial and re-tuned EM simulated values of design parameters for each operating frequency.

Design Parameter	2.4 GHz		5 GHz		10 GHz
	Initial	Re-Tuned	Initial	Re-Tuned	Initial	Re-Tuned
$L_{deg}$ (pH)	78	49	33	64	89	21
$L_g$ (nH)	9.6	8.5	7.5	17.0	2.9	2.8
$R_1$ (k$\mathrm{\Omega }$)	5.1	—	1.3	—	3.6	740 $\mathrm{\Omega }$

.

Since the original design parameters are no longer sufficient to achieve industry-standard specifications, the circuits were post-layout re-tuned by adjusting key passive component values while maintaining the same active device sizing and biasing conditions. This process was guided by full EM-extracted simulations, ensuring that the final proposed designs reflect realistic parasitic performance. The proposed layout for each frequency band is presented in Figure 15.

The evolution of the matching networks can be effectively visualized using Smith Charts, which plot the frequency-swept input/output impedance of the circuits. Since Smith Charts are normalized to 50 $\mathrm{\Omega }$, the proximity of the target frequency point to the center of the chart directly reflects the quality of the matching, with points closer to the center indicating improved impedance matching performance. Utilizing Smith Charts provides a clear visualization of the degradation in matching caused by crosstalk, as well as the restoration achieved through the re-optimization process. These visualizations are shown in Figure 16, where sub-figures (a)–(c) correspond to the 2.4 GHz, 5 GHz, and 10 GHz designs, respectively. After demonstrating the restoration of proper matching through Smith Chart analysis, the final performance metrics of the optimized nested designs were evaluated to verify their compliance with industry-standard specifications. The results presented in

Table 4. Final simulated performance metrics of the proposed nested single-ended LNAs.

Performance Metric	2.4 GHz	5 GHz	10 GHz
Silicon Footprint (mm2)	0.047	0.025	0.021
$S_{11}$ (dB)	−31.5	−23.8	−23.4
$S_{21}$ (dB)	16.9	12.9	11.9
$S_{12}$ (dB)	−41.3	−26.5	−29.9
$S_{22}$ (dB)	−30.2	−3.2	−1.2
Noise Figure (dB)	2.8	2.9	3.1
IP1 (dBm)	−14.5	−16.6	−13.6
IP3 (dBm)	−6.5	−9.7	−5.9
Power Dissipation (mW)	13.2	6.3	5.4

include the same key performance metrics previously reported for the standard and non-optimized nested designs, enabling a direct and consistent comparison across all stages of the design process.

Figure 17 provides a visual comparison of performance metrics between the standard and the optimized nested design, where the proposed implementation is represented by solid lines and the standard design by dashed lines. The three subfigures correspond to different target frequencies: (a) 2.4 GHz, (b) 5 GHz, (c) 10 GHz.

Across all three optimized designs, the matching parameters that were specifically targeted during re-optimization exhibit excellent performance, with return loss values better than −20 dB, corresponding to more than 99% power transfer efficiency. The forward gain remains consistently above 11 dB, with the optimized 2.4 GHz design reaching a maximum of 16.8 dB, while the noise figure stays stable at approximately 3 dB across all frequency bands. Both linearity metrics and power dissipation show minimal variation compared to the standard designs, indicating that the proposed re-optimization process restores performance without introducing additional trade-offs. The only parameter exhibiting notable variation is the reverse isolation, which highlights the importance of thoroughly verifying the stability of the circuits.

In Figure 18, the stability factor ($K_f$) for all three optimized designs is presented across a frequency band centered at the operation frequency. The stability factor, is a key indicator of unconditional stability, with values of $K_f>1$ across the entire frequency range confirming that no oscillations will occur under any source or load conditions. It is evident that all the proposed designs maintain unconditional stability, enduring reliable and robust operation even after the layout-level re-optimization process. Overall, this leads to the conclusion that utilizing the nested inductor structure offers a highly effective means of significantly reducing silicon area, thereby lowering production costs, while preserving all the key performance benefits of the standard designs.

4.4. Frequency-Dependent Applicability of Nested Inductor Structures

To better understand the practical applicability of the proposed nested inductor methodology, it is essential to analyze how its effectiveness changes across different frequency ranges. As the operating frequency increases, the physical dimensions of the inductors decrease, and consequently the overall layout area is also reduced, since at lower frequencies the inductors constitute the most area-consuming components of the design. The impact of this frequency scaling on the total occupied silicon area is observed in Table 2. This behavior is explained by the fact that higher frequencies are associated with larger MOSFET parasitic capacitances, and to maintain the desired resonance condition, the inductance value must be proportionally reduced [39]. Reduced inductance values directly translate into physically smaller inductors, since achieving lower inductance requires fewer turns and a smaller inner diameter. In spiral geometries, the inductance scales down with the number of turns and the inner diameter of the structure [40], meaning that lowering the target inductance naturally leads to a more compact footprint. At high frequencies the turn width is typically maximized in order to reduce the parasitic series resistance and maintain an adequate Q factor, thus making the inner diameter and the number of turns the dominant factor in area scaling. As a result, the overall occupied silicon area decreases substantially with frequency, since inductors no longer dominate the circuit layout. This trend is illustrated in Figure 19a, where the silicon area is observed to reduce with increasing frequency in both standard and nested designs. Furthermore, the reduced physical dimensions limit the feasibility of applying the nested methodology at mmWave frequencies, since inductors of comparable size cannot be effectively nested within each other. A possible alternative would be to place one inductor on a lower metal layer; however, this stacked-like configuration increases magnetic coupling and introduces higher parasitic resistance due to reduced thickness of lower metals, ultimately degrading the Q factor. Furthermore, as the target frequency increases, mutual coupling effects between closely spaced inductors become significantly stronger, reaching a peak, and then transition to a capacitive behavior, as shown in Figure 19b. The resulting electromagnetic interactions can heavily alter the effective behavior of the inductors, making the post-layout re-tuning process less effective or, in some cases, insufficient to fully restore the desired performance.

Table 5. Percentage of total layout area occupied by inductors in the standard LNA designs and the corresponding area reduction due to nesting.

Frequency	Inductor Area (%)	Area Reduction (%)
2.4 GHz	48.1	25.4
5 GHz	43.0	44.4
10 GHz	41.5	40.0

presents the percentage of silicon area occupied by inductors in the standard designs, which decreases as frequency increases, along with the corresponding percentage of area reduction achieved through nesting.

The relative area reduction achieved by the nested design is less pronounced at 2.4 GHz compared to the 5 GHz and 10 GHz cases as seen in Table 5. This difference arises from the flexibility offered by the nested approach, which allows the designer to customize the layout to accommodate the surrounding circuitry. In the 2.4 GHz implementation, a different nested layout configuration was adopted (Figure 15), whereas the 5 GHz and 10 GHz designs share a more uniform structure. An alternative layout arrangement of the 2.4 GHz nested design, could yield higher footprint efficiency and thereby further enhance the area reduction percentage. This adaptability represents a key advantage of the nested methodology, as it allows the two inductors to be treated as a single structural entity while still preserving their electrical independence, enabling greater flexibility in layout customization.

The preceding analysis lead to an important conclusion: while the nested inductor methodology provides substantial area savings at RF frequencies, its benefits diminish as frequency increases. At mmWave frequencies, where inductors occupy a smaller portion of the total area and electromagnetic coupling is more dominant, the technique becomes less efficient and harder to implement reliably.

5. Differential LNA Design for mmWave Frequencies

The previous sections have demonstrated that while the nested inductor methodology provides substantial area savings and excellent performance at low- and mid-RF frequencies, its efficiency gradually diminishes as the operating frequency increases. To address the challenges, the design methodology must shift toward topologies that inherently exploit strong coupling rather than attempting to minimize it. Balun-based topologies, which rely on high magnetic coupling between windings, become highly advantageous at these frequencies. In this context, the focus of the design moves from area efficiency to performance maximization. The following sections presents the design procedure of a 33 GHz differential LNA, specifically tailored for millimeter-wave applications employing strongly coupled inductors such as baluns. The proposed design’s input and output impedances are matched to 50 $\mathrm{\Omega }$ to illustrate the tuning effectiveness of this topology.

5.1. Evaluation of Balun Electromagnetic Behavior

To ensure optimal performance of the proposed differential LNA at millimeter-wave frequency, it is essential to accurately characterize the baluns that form the input and output matching networks. Unlike simple inductors, baluns are inherently coupled structures, consisting of a primary winding, a secondary winding, and the mutual magnetic flux linking them [41]. Their behavior is strongly frequency dependent, with parameters such as the self-inductance of the primary ($L_p$) and secondary ($L_s$) coils, as well as the mutual coupling coefficient (k), varying significantly across the operating band. Two common balun topologies, shown in Figure 20, are typically considered for millimeter-wave designs: the stacked balun and the interleaved balun. In the stacked configuration, one inductor is placed directly above the other on a separate metal layer, with the primary coil implemented on an upper metal layer and the secondary on a lower one. In contrast, the interleaved configuration consists of two interwoven coils, where the windings are perplexed and arranged concentrically. Beyond the inner diameter, which has the strongest influence on the self-inductance values, other geometric parameters play a critical role in defining the balun behavior. These include the metal trace width of each turn and, for interleaved designs specifically, the spacing between adjacent turns.

For the input stage, a stacked balun was selected to minimize input insertion loss. This choice is motivated by the fact that vertically overlapping windings provide stronger magnetic coupling compared to interleaved structures [42]. Stacked configurations also require less conductor length to achieve the same primary and secondary inductance, since coupling efficiency is enhanced through vertical overlap. The shorter trace length directly reduces parasitic series resistance and contributes to lower insertion loss. To further mitigate parasitic capacitance between the primary and secondary coils, the minimum allowable metal width should be employed, which is crucial for preserving high frequency performance. Although stacked configurations inherently introduce higher inter-winding capacitance, the benefits of tighter coupling and reduced parasitic resistance dominate at the operating frequency [43].

For the output stage, an interleaved balun is employed to extend the usable frequency range. Interleaved baluns exhibit lower inter-winding capacitance compared to stacked configurations, since the primary and secondary coils are arranged laterally than vertically. This reduction in parasitic capacitance shifts the self-resonance frequency to higher values, which is particularly beneficial for maintaining performance at mmWave frequencies, even though it comes at the expense of weaker magnetic coupling. Furthermore, the reduced parasitic capacitance allows the real and imaginary parts of the output impedance to be accurately tuned using only the external matching capacitors $C_1$ and $C_2$. Maximizing the turn width reduces parasitic series resistance and thereby improves the quality factor, while increasing the spacing between adjacent turns leads to higher effective inductance of primary and secondary coils. Interleaved balun geometries are particularly beneficial in output baluns, since the secondary coil operates as an inductive load and contributes directly to gain enhancement in differential LNAs.

The preceding discussion can be illustrated by comparing the key parameters of stacked and interleaved baluns designed with the same inner diameter. The EM-extracted primary and secondary inductances are presented in Figure 21, which demonstrate that the interleaved balun exhibits a substantially higher self-resonance frequency, attributed to the significantly lower capacitive coupling between adjacent traces.

The frequency-dependent mutual coupling coefficient (k) is also plotted, showing that the stacked configuration achieves stronger magnetic coupling than the interleaved counterpart, while both exhibit significantly higher coupling compared to nested inductor structures within the frequency range of interest. During the design process, variations in the inner diameter directly influence the extracted values of $L_s$, $L_p$ and k. Excessive coupling in the output stage can limit the achievable gain bandwidth of the amplifier, as it tightly binds the real and imaginary parts of the output impedance. When the output coupling coefficient becomes excessively high, the gain-bandwidth tradeoff is further compromised [44]. This flexibility in tuning the output balun coupling provides an additional degree of freedom for optimizing the overall performance of the differential LNA.

5.2. Layout Implementation and Performance Evaluation

Following the methodology described in the machine learning-based design framework for differential mmWave LNAs [4], the initial design parameters were first defined at the schematic level. These parameters provided a solid starting point for achieving proper impedance matching, noise optimization, and gain requirements, before layout implementation. Once the layout was completed, full electromagnetic post-layout simulations were performed to capture the effects of layout-dependent parasitics, including interconnect self-inductance and mutual coupling between metal traces. In this architecture, the $S_{11}$ and $S_{21}$ bandwidths do not necessarily coincide, as they are determined by different physical constraints. The broader the $S_{11}$ bandwidth results from the magnetic coupling in the input balun, which slightly shapes the input impedance and naturally widens the matching range. In contrast, the the $S_{21}$ bandwidth is limited by the frequency-dependent Q-factor of the output resonant network, whose effective loading is set by the secondary winding of the output balun. Such separation between input matching and gain bandwidth is typical in narrow-band, high-Q mmWave LNAs and reflects the trade-off between matching robustness and resonant-network gain performance. Based on these results, the original design parameters were adjusted to compensate for the additional parasitic effects, ensuring that the final implementation closely aligned with the intended performance goals. The final set of parameters are summarized in

Table 6. Final design parameters for the 33 GHz differential LNA.

Design Parameter	Value (Unit)
$V_{DD}$	0.8 V
$V_B$	0.45 V
${(W/L)}_{M1}$	180/0.02 μm
${(W/L)}_{M2}$	180/0.02 μm
${(W/L)}_{M1C}$	360/0.02 μm
${(W/L)}_{M2C}$	360/0.02 μm
$C_N$	70 fF
$C_{IN}$	90 fF
$C_1$	45 fF
$C_2$	160 fF
R	125 $\mathrm{\Omega }$
Inner Diameter of Input Balun	26 μm
Inner Diameter of Output Balun	60 μm

.

The optimized implementation of the proposed differential LNA is shown in Figure 22. The layout integrates the input and output baluns, matching networks, neutralization capacitors, and active devices, in a compact structure optimized for millimeter-wave operation. Special attention was given to symmetry, ground routing, and minimization of parasitic coupling, ensuring robust high-frequency performance and accurate differential signal handling. The design was evaluated using the same performance metrics as the single-ended LNAs, with the results summarized in

Table 7. Post-layout simulated performance metrics of the proposed 33 GHz differential LNA.

Performance Metric	33 GHz Differential LNA
$S_{11}$ (dB)	−23.7
$S_{21}$ (dB)	16.0
$S_{12}$ (dB)	−37.8
$S_{22}$ (dB)	−20.7
Noise Figure (dB)	3.9
IP1 (dBm)	−26.9
IP3 (dBm)	−13.2
Power Dissipation (mW)	64.4
Silicon Footprint (mm2)	0.047

, including forward gain, return losses, noise figure, linearity indicators, power consumption, and occupied area.

The matching efficiency of the design can be further evaluated in Figure 23, where the Smith Chart illustrates the frequency sweep of the input impedance and output admittance, clearly demonstrating the quality of the matching networks across the operating band.

The RLCk-aware responses are illustrated in Figure 24, where (a) illustrates the S-parameters and Noise Figure and (b) depicts the stability factor of the proposed LNA.

The post-layout simulation results indicate that the proposed 33 GHz differential LNA achieves input and output return losses below −20 dB, demonstrating effective impedance matching at both ports. The circuit also exhibits unconditional stability across the frequency range of interest with a stability factor $K_f>1$. The forward gain is simulated at 16 dB, while the noise figure is 3.9 dB, which is within acceptable limits for this frequency range. Both linearity and power dissipation remain constrained. The relatively high power consumption arises from the large W/L ratios required, which increase the DC current. Using a longer channel length (e.g., 70 nm) would permit narrower devices with the same balun-based tuning, thereby reducing current and power dissipation. In addition, the 0.8 V supply limits voltage headroom and constrains linearity, while short-channel effects combined with high current density further contribute to non-linear behavior.

5.3. Performance Benchmarking

To validate the effectiveness of the proposed design methodology,

Table 8. Comparison with State of the Art for the Proposed LNAs.

Metric	[45]	This Work	[9]	This Work	[46]	This Work	[47]	This Work
Results	Meas	Sim	Sim	Sim	Meas	Sim	Meas	Sim
Tech. Node	22 nm	22 nm	65 nm	22 nm	65 nm	22 nm	22 nm	22 nm
Vdd (V)	1	0.8	1.2	0.8	1	0.8	1.6	0.8
Freq. (GHz)	2.1–5.2	2.4	4.0–6.5	5.0	8–12.2	10.0	28/38	33.0
$S_{21}$ (dB)	12.7–15.7	16.9	15.6	12.9	28.5	11.9	22.4	16.0
NF (dB)	1.5–2	2.8	2.7	2.9	1.61–2.17	3.1	3.6–4.9	3.9
Power (mW)	16	13.2	22	6.3	22	5.4	13.6	64.4
IP3 (dBm)	−6	−6.5	2.5	−9.7	−19	−5.9	−10.3	−13.2
Area (mm2)	0.380	0.047	0.21	0.025	0.187	0.021	0.310	0.047
$Fo{M}_1 \left({\displaystyle \frac{\mathrm{GHz}}{{\mathrm{mm}}^2}}\right)$	8.44	16.2	34.7	46.2	1.26	259.5	11.93	5.72

summarizes a comparison with recently reported CMOS LNAs operating in comparable frequency ranges and implemented in similar process nodes. The comparison is based on the following figure of merit (FoM) [9]:

$${\mathrm{FoM}}_1={\displaystyle \frac{S_{21} \left(\mathrm{dB}\right)\times IP3\left(\mathrm{mW}\right)\times f_0 \left(\mathrm{GHz}\right)}{|NF-1|\times P_{\mathrm{DC}} \left(\mathrm{mW}\right)\times \mathrm{Area} \left({\mathrm{mm}}^2\right)}} \left({\displaystyle \frac{\mathrm{GHz}}{{\mathrm{mm}}^2}}\right)$$

(17)

where NF and IP3 are expressed in linear scale, corresponding to the linear noise factor ($NF={10}^{{\displaystyle \frac{N{F}_{db}}{10}}}$) and the linear power representation of the third-order intercept point, respectively. Incorporating the area term in the FoM formulation ensures that the evaluation reflects the compactness and integration efficiency achieved through the proposed layout optimization methodology. Based on EM simulation results, this figure of merit captures the combined trade-off among gain, linearity, operating frequency, power consumption, and silicon area, thereby providing a single quantitative indicator of overall LNA performance efficiency. A higher FoM corresponds to a design that delivers stronger RF performance per unit power and per unit area. The proposed LNA designs, occupy a notably smaller silicon area compared to recently reported designs in similar technology nodes. At the same time, the remaining performance metrics -gain, noise figure, linearity, and power consumption- remain within ranges that are consistent with contemporary state-of-the-art LNAs.

6. Conclusions and Future Work

This work systematically analyzes and mitigates magnetic-coupling and crosstalk effects in compact RFIC layouts where inductors are placed in close proximity through a fully EM-aware design framework, enabling accurate prediction and control of these phenomena. A set of layout-level design methodologies was proposed and validated through RF single-ended LNA implementations and a 33 GHz differential LNA design, all targeting low-area, high-performance front-end circuits. These methodologies focused on optimizing noise figure, forward gain, and impedance matching, while simultaneously minimizing silicon area through careful passive component layout. The Ansys^® RaptorX, Release 2024 R2, ANSYS, Inc. RLCk extraction tool was used in all designs to capture the complete RLCk parasitics of passives and interconnects to ensure accurate post-layout simulation and reliable verification of the proposed circuits.

The proposed methodology initially employed different inductor configurations, including standard, nested, and optimized nested layouts, demonstrating that optimized nested inductors provide significant silicon savings, with an almost $50\%$ area reduction in the overall chip footprint compared to the standard designs, while keeping magnetic coupling under control. Impedance matching remained robust, with input and output return losses corresponding to $99\%$ matching efficiency across the target frequency bands. In several cases, the nested configuration not only preserved isolation but also enhanced circuit performance, delivering higher forward gain (up to 16.9 dB) and improved noise figure (as low as 2.8 dB) relative to conventional layouts. At millimeter-wave frequencies, the use of balun-based topologies further enabled independent input and output matching while maintaining high matching efficiency, forward gain exceeding 15 dB, and noise figure around 4 dB, all within a compact layout tailored for dense integration. This verification flow demonstrates that low-area, high performance LNAs can be achieved through layout-level methodologies, even under the integration and coupling challenges of mmWave design. Nested inductor structures prove most effective at lower RF frequencies, while balun-based solutions are preferable at higher frequency bands, providing a clear pathway to balance performance and area in future RFICs.

Future research will focus on hardware-based validation of the proposed methodology. Die-level, on-wafer characterization of representative LNA implementations will be carried out using GSG (Ground-Signal-Ground) pad structures for single-ended circuits and GSGSG pad structures for differential designs, enabling accurate probe VNA measurements. Standalone versions of both nested and conventional inductors will also be fabricated using dedicated test structures, allowing direct comparison between silicon measurements and EM-based predictions—an essential step for verfication in the RF and mmWave frequency range. These on-wafer measurements will further enable the assessment of second-order effects that are difficult to fully capture in simulation, such as substrate coupling, process-induced variability, and to evaluate their impact on noise figure, gain, and overall FoM. Beyond measurement-oriented validation, the methodology will be extended to additional RF and mmWave front-end circuits, including mixers, VCOs, and phase shifters, where mutual coupling and layout-induced parasitics must also be carefully addressed.