Design and Optimization of LTCC Broadband Interconnect Structures for Bare-Chip Integration

Abstract

In bare-die integration based on low-temperature co-fired ceramic (LTCC) multilayer interconnects, broadband signal transmission is often limited by impedance mismatch, parasitic effects introduced by gold-wire bonding, and discontinuities in interlayer transitions. These issues collectively form major bottlenecks for achieving low-loss and wideband interconnections in high-frequency LTCC modules. To address these challenges, this paper proposes a multi-layer collaborative optimization framework for LTCC bare-die interconnects operating from 1 to 20 GHz. The proposed framework jointly considers impedance matching, bonding parameter optimization, and interlayer transition enhancement to achieve broadband and high-performance signal transmission. First, two T-type microstrip matching networks are designed based on the complex input impedance of the bare die, and their parameters are optimized using ADS (an integrated circuit design software, version 2020). Second, a microstrip–gold-wire bond–bare-die interconnect model is established to analyze bonding-induced parasitic effects, revealing that a bond center spacing of 0.12 mm provides optimal high-frequency performance. Third, for the stripline–via–microstrip transition, a coaxial-like via structure combined with a square defected ground structure (DGS) is introduced to improve impedance continuity and electromagnetic field confinement. Full-path cascaded simulations demonstrate that the proposed interconnect achieves a return loss better than −23.1 dB and an insertion loss below 0.45 dB across the 1–20 GHz frequency range. Compared with conventional LTCC interconnect structures, the proposed method improves return loss by more than 7 dB and reduces insertion loss by approximately 0.12 dB. The results confirm the effectiveness of the proposed collaborative optimization strategy and provide reusable design guidelines for broadband bare-die integration in high-frequency LTCC multilayer modules.

1. Introduction

With the rapid development of high-frequency communication systems, millimeter-wave sensing, and multi-chip module (MCM) packaging technologies, the demand for compact, broadband, and low-loss interconnect structures continues to increase. Low-temperature co-fired ceramic (LTCC) technology has emerged as a key platform for realizing high-density multilayer microwave systems due to its excellent dielectric stability, flexible multilayer routing capability, and compatibility with the integration of passive and active components [1]. In LTCC-based high-frequency modules, bare-die integration is widely adopted to further reduce system footprint and minimize packaging parasitics. However, achieving broadband, low-loss, and highly stable bare-die interconnections within LTCC multilayer environments remains a significant challenge.

In practical LTCC bare die assembly, multiple factors can cause significant degradation of broadband signal integrity. Impedance mismatch between the bare-die input and transmission lines can significantly degrade signal transmission performance. Parasitic inductance and capacitance introduced by gold-wire bonding can produce noticeable resonance at high frequencies. Discontinuities in interlayer transition structures cause return path interruptions, increased radiation, and elevated insertion loss [2,3,4]. In response, numerous scholars have employed various methodologies to investigate the transmission performance and structural characteristics of transmission lines. In [5], a bonding-wire circuit with a fifth-order low-pass filter as an interconnect prototype is designed to extend the operating bandwidth. In [6], a low-loss, low-cost vertical interconnect solution for the S-band was designed using a coaxial-like vertical interconnect structure based on HTCC technology. In [7], by adding ground vias around signal vias, transmission performance is enhanced through increased signal return paths and reduced signal reflections. In [8], vertical interconnections on LTCC substrates are achieved using BGA and coaxial structures, with tapered lines compensating for BGA discontinuities. Multiple researchers have employed various methods to significantly enhance the RF characteristics of structures such as transmission lines bonded to gold wires and striplines connected to connectors. Although notable progress has been achieved, two critical limitations remain. First, most existing studies focus on optimizing individual submodules—such as impedance matching networks, bonding structures, or vertical transitions—while lacking a collaborative optimization framework that simultaneously considers their combined effects. Second, end-to-end broadband interconnect design for bare-die integration, particularly across a wide frequency range exceeding one decade, has not been sufficiently addressed. As a result, performance degradation often occurs when individually optimized substructures are cascaded in practical systems. To address these issues, this paper proposes a multi-layer collaborative optimization design framework for LTCC broadband bare-die interconnect structures operating from 1 to 20 GHz. Its main contributions are as follows:

• A T-type microstrip matching network is constructed based on the complex impedance input of a bare chip, and matching is optimized by comparing two matching circuits.
• Bonded Interconnect Layer: Establish a microstrip–gold-wire bond–bare die interconnect model, analyze bonding parasitic mechanisms, and determine the optimal bond center spacing to suppress parasitic inductance imbalance.
• A coaxial-like via structure combined with a square defected ground structure (DGS) is proposed to enhance impedance continuity and electromagnetic field confinement in stripline–via–microstrip transitions.
• Full-path verification: Full-wave cascaded simulations in HFSS are performed to validate the broadband performance of the proposed interconnect architecture. The designed interconnect structure achieves S₁₁ < −23.1 dB and S₂₁ < 0.45 dB across the 1–20 GHz frequency range, demonstrating significant advantages over conventional structures.

2. Proposed Methods

2.1. Matching Network Design

In microwave circuit design, impedance matching is a critical step for ensuring efficient signal transmission. When impedance mismatch occurs between the transmission line and the load (such as a bare chip), signal reflection occurs, leading to reduced signal power transmission efficiency and degraded signal integrity [9,10]. The input impedance of bare chips often deviates from the standard 50 Ω transmission line value, necessitating the construction of appropriate impedance matching circuits to optimize performance. A well-designed matching circuit can maximize power transfer, improve system bandwidth characteristics, enhance signal transmission quality, and reduce system noise.

In LTCC processes, layouts are compact, and lumped matching components struggle to guarantee precise parameters and low-loss characteristics at high frequencies. Moreover, their parasitic inductance and capacitance significantly degrade broadband performance. Therefore, this study employs a systematic workflow of “L-type lumped matching circuit-transmission line equivalent-full-wave optimization” to achieve impedance matching using two microstrip lines instead of lumped components.

First, an L-type matching network is designed based on the measured complex input impedance of the bare die. Subsequently, transmission line theory is applied to convert this circuit into a microstrip structure feasible for LTCC fabrication, thereby forming a T-type matching network with physically interpretable characteristics. This approach provides a clear physical interpretation of the matching parameters and serves as a reliable initial structure for subsequent full-wave optimization. The L-type matching network employs a two-component topology using discrete elements to form a dual-element network. This network utilizes inductors and capacitors to transform the load impedance into any desired impedance, achieving impedance matching. Since this paper requires equivalent modeling of lumped elements as microstrip lines, Figure 1a,b present two connection configurations for the L-type network based on series inductors and parallel capacitors. Viewed from the bare die toward the input port, the two configurations achieve 50 Ω matching by either connecting the capacitor in parallel followed by the inductor in series, or by connecting the inductor in series followed by the capacitor in parallel.

According to transmission line theory [11], the input impedance of a transmission line is expressed as:

$$\begin{array}{c}{Z}_{in}\left(L\right)=R_{in}+j{X}_{in}=Z_0{\displaystyle \frac{Z_L+j{Z}_0\tan \left(\beta L\right)}{Z_0+j{Z}_L\tan \left(\beta L\right)}}\end{array}$$

(1)

In the formula, Z_in denotes the input impedance; Z₀ and Z_L represent the characteristic impedance and load impedance, respectively; L is the transmission line length.

A series inductor can be equivalently modeled as a short microstrip line segment with high characteristic impedance, while a parallel capacitor can be equivalently modeled as a short microstrip line segment with low characteristic impedance. According to Equation (2), the series inductor and parallel capacitor are equivalently modeled using high-impedance and low-impedance microstrip lines, respectively.

$$\begin{array}{c}\left\{\begin{array}{c}{L}_{gL}={\displaystyle \frac{{\lambda }_{gL}}{2\pi }}\arcsin \left({\displaystyle \frac{{\omega }_{c}L}{Z_{oL}}}\right)\\ \\ L_{gC}={\displaystyle \frac{{\lambda }_{gC}}{2\pi }}\arcsin \left({\omega }_{c}C{Z}_{oC}\right)\hspace{0.25em}\end{array}\right.\end{array}$$

(2)

In the equation, ω_c represents the cutoff frequency, λ_gL and λ_gC denote the wavelengths of the high-impedance line guided wave, while Z_oL and Z_oC correspond to the characteristic impedances of the high- and low-impedance lines. This configuration forms a T-shaped matching network composed of two segments of microstrip lines with differing widths and impedances, yielding its initial geometric parameters W1, L1, W2, and L2.

Considering that gold-wire bonding introduces additional parasitic inductance and loss in actual structures, this study modeled the bonding wire as a three-dimensional arc and incorporated it alongside the LTCC multilayer structure into HFSS full-wave simulation. Based on this, parameter scans and co-optimization were performed to further adjust W1, W2, L1, and L2, enabling the final structure to achieve deeper return loss and a flatter insertion loss curve across the 1–20 GHz frequency range.

2.2. Coaxial-like Structure

Vertical signal interconnections play a critical role in multilayer LTCC components by enabling signal routing between different layers while reducing surface-level congestion. Internal striplines are commonly used to suppress electromagnetic interference and radiation. However, at high frequencies, discontinuities introduced by vertical vias significantly degrade signal integrity, leading to increased reflection and insertion loss. Therefore, careful design and optimization of vertical via structures are essential for broadband LTCC interconnects.

Coaxial-like via structures are widely adopted in LTCC substrates to improve high-frequency vertical interconnect performance. As illustrated in Figure 2, the structure consists of a central signal via surrounded by an array of ground vias, forming a configuration analogous to a coaxial transmission line. The surrounding ground vias provide a continuous return path, confine the electromagnetic field, and reduce radiation loss and crosstalk. In practice, the number and spacing of the surrounding ground vias must be carefully selected. Typically, at least four ground vias are required to achieve effective shielding. Excessively large spacing between ground vias weakens the shielding effect, whereas overly dense via arrays complicate fabrication and may violate LTCC manufacturing constraints. Consequently, a balanced design is necessary to achieve both electromagnetic performance and process feasibility.

2.3. Defect Ground Structure

Defect Ground Structure (DGS) involves etching one or more defect structures onto the reference ground plane of a planar microwave transmission line. This alters the effective chiplectric constant of the circuit substrate across different regions, significantly enhancing the distributed capacitance and inductance of the transmission line. Consequently, the transmission characteristics exhibit bandgap effects, high equivalent impedance, and slow-wave properties. Since its inception, the DGS has garnered increasing attention from scholars and experts due to its bandgap transmission characteristics, coupled with its simplicity in design and ease of integration. Consequently, it has emerged as a research hotspot in microwave circuit design [12].

The shape, dimensions, and effective chiplectric constant of the medium substrate all significantly influence the circuit characteristics of defect-state structures. Since Park first proposed the dumbbell-shaped DGS, various DGS designs have been developed [13], including periodic and non-periodic, symmetric and asymmetric configurations, as shown in Figure 3.

3. Simulation Study

3.1. T-Type Matching Network Design

In LTCC multilayer structures, the available area around the chip is strictly limited. If large series inductors or parallel capacitors are used, they will be converted into longer or wider microstrip segments during transmission line equivalent processes. This significantly increases the layout area and disrupts local impedance continuity. Therefore, in this design, the inductance and capacitance values required for the matching network must be kept within a small range to ensure that their equivalent microstrip segments can be realized within a limited area. Despite these constraints on L/C values, effective compensation for the bare-chip impedance can still be achieved within limited dimensions by rationally selecting combinations of series inductance and parallel capacitance. This approach, coupled with a T-shaped structure design for high- and low-impedance microstrip segments, enables good matching to 50 Ω across the 1–20 GHz range. Consequently, both dimensional feasibility and broadband matching performance requirements are simultaneously satisfied.

Under these constraints, effective impedance compensation for the bare die can still be achieved by properly selecting combinations of series inductance and shunt capacitance. Figure 4 illustrates the Smith chart-based matching process for transforming the bare-die load impedance ($Z_L=41.2+j5.4 \mathrm{\Omega }$) to 50 Ω at a center frequency of 10 GHz using two L-type matching topologies with relatively small lumped element values.

Subsequently, based on the transmission line equivalence relations, the two structures in Figure 2 were transformed: the series inductance was converted into a high-impedance microstrip segment, and the parallel capacitance was converted into a low-impedance microstrip segment. This resulted in T-type microstrip matching networks with different parameters. To compare the matching performance of the two networks across the 1–20 GHz frequency range, simulations of both T-type networks were conducted in ADS. The simulation results and dimensional diagrams for the equivalent T-type microstrip structures are shown in Figure 5 and Figure 6, respectively.

As shown in Figure 6b, the configuration in which the series inductive segment precedes the shunt capacitive segment exhibits superior broadband matching performance compared with the alternative topology. This structure provides deeper return loss and improved impedance stability across the operating band, and is therefore selected as the initial T-type matching network for subsequent full-wave optimization. Although ADS simulation results are favorable, these are obtained under ideal conditions without accounting for multiple influencing factors in actual board-level applications. In engineering practice, when matching circuits are integrated into complete systems, practical factors such as gold-wire bonding effects and multilayer board structural characteristics significantly impact RF performance. To ensure overall system performance, precise modeling and simulation analysis of actual board-level structures are conducted using 3D electromagnetic field simulation tools like ANSYS HFSS (version 2023 R1). This co-simulation approach more accurately reflects the matching circuit’s behavior in real operating environments, providing reliable validation for design verification.

3.2. Optimized Design for Microstrip–Gold-Wire Bonding–Bare-Chip Interconnections

To reduce design complexity, avoid global performance degradation caused by local optimization, and ensure impedance continuity and signal integrity across all levels through collaborative analysis, this paper employs a hierarchical optimization approach. The overall structure is decomposed into microstrip–wire bond–bare die (MSL-bare die) and stripline–via–microstrip (SL-MSL) modules, optimizing critical issues such as impedance matching and parasitic parameter suppression separately.

For the microstrip–wire bond–bare die interconnect module, modeling was performed in HFSS software based on the microwave hybrid circuit board laminate structure and T-type impedance matching network configuration to facilitate further analysis. The cross-sectional view of the model is shown in Figure 7, with dimensions set at 13 mm × 12 mm × 0.734 mm. This design employs a 6-layer Ferro A6M ceramic substrate with a dielectric constant of 5.9 and a loss tangent of 0.002. Each substrate layer has a thickness of 0.1 mm. The top two layers constitute the mid1 layer with a thickness h3 = 0.2 mm. The bottom four layers form the mid2 layer with a thickness h4 = 0.4 mm. Above the mid1 layer is the signal layer M1, used for microstrip traces and chip soldering. Below the mid1 layer and below the mid2 layer are the ground layers M2 and M3, respectively, with a thickness of h = 0.01 mm. Both layers use gold conductor paste with a sheet resistance ≤5 mΩ/sq. A GaAs dielectric substrate measuring 2 mm × 2 mm × 0.1 mm serves as the chip substrate, positioned above the ceramic baseplate. A metal layer with thickness h = 0.01 mm acts as the chip ground between the substrate and baseplate. Two rows of vias with a radius of 0.1 mm are placed between the chip ground and the M1 layer. Above the substrate is a gold-plated pad measuring 0.1 mm × 0.1 mm × 0.004 mm. The top layer of the model is shown in Figure 8, where a 50 Ω transmission line connects to a T-shaped microstrip, positioned at a distance d1 = 0.1 mm from the chip. A row of vias is placed on both sides of the transmission line. The via material uses silver conductive paste with a sheet resistance ≤3 mΩ/sq. All vias have a diameter of d = 0.2 mm and an inter-via spacing of t = 0.5 mm. The edge-to-edge distance between vias and the transmission line edge is t1 = 0.4 mm, ensuring electromagnetic fields remain confined within the transmission path without escaping laterally. The air cavity must extend at least 1/4 wavelength beyond the model edge. At the study frequency of 10 GHz (wavelength 30 mm), the air cavity should extend at least 7.5 mm beyond the model edge. The air cavity distance is set to 10 mm in this study.

This section primarily investigates the impact of T-matching circuits and bond wire spacing on high-frequency performance. The simulation employs the following parameter configuration: a 50 Ω lumped port is set as the output terminal at the chip substrate connection point, a wave port is configured as the input terminal at the microstrip line start point, and the air box is defined as a radiating boundary condition. The simulation frequency range is set from 1 to 20 GHz, with a scan step of 0.025 GHz. The signal transmission path sequentially follows: wave port input → microstrip line transmission → T-type matching network → gold-wire bonding interconnect → lumped port output. This model characterizes the entire signal pathway from the transmission line to the chip.

3.2.1. Effect of Gold-Wire Bonding Center Spacing on RF Performance

In LTCC multilayer packaging, gold-wire bonding stands as the most mature and cost-effective implementation method for bare die RF interconnects. Its assembly flexibility and elimination of additional metal redistribution or bumping processes make it widely adopted for interconnect structures between on-chip active devices and LTCC microstrip lines. The selection of gold-wire bonding in this study also stems from its high compatibility with LTCC processes. However, gold-wire bonding inevitably introduces parasitic inductance and coupling effects between adjacent lines, significantly impacting impedance continuity, return loss, and insertion loss flatness, particularly at frequencies above several GHz [14].

The commonly used gold-wire bonding π-type equivalent circuit (as shown in Figure 9) effectively describes series inductance, series resistance, and parasitic capacitance generated by the center-to-center spacing of bonding wires across the low-to-mid frequency range. Consequently, it is widely employed for preliminary impedance analysis. However, it should be noted that this π model is a first-order approximation that does not explicitly account for frequency-dependent phenomena such as skin effect, proximity effect, current crowding, and mutual coupling between bond wires, which become more significant above 10 GHz. Consequently, it struggles to accurately predict high-frequency broadband behavior. To overcome this limitation, this study builds upon the π-type approximate equivalent model by employing HFSS to construct a complete three-dimensional gold-wire bonding model. A parametric scan analysis of the bonding center spacing is conducted to reveal its influence on transmission characteristics. Based on these findings, collaborative optimization with the matching network is achieved, ensuring broadband interconnect performance across the 1–20 GHz range.

As shown in Figure 10, the microstrip line is connected to the GaAs substrate via two 25 μm gold wires. The gold-wire bond pad height is selected as H1 = 0.1 mm and H = 0.2 mm, with lengths D1 = 0.1 mm and D = 0.26 mm. Based on the pad dimensions of 0.1 mm × 0.1 mm defined in the preceding model, the center-to-center spacing of the bond wire output terminals is fixed at W3 = 0.05 mm, resulting in W4 = 0.05 mm. This section primarily investigates the impact of the input bond wire center-to-center spacing W4 on RF transmission performance.

Based on the parameters of the T-type matching network (W1, L1, W2, L2), a parameter scan analysis was conducted on the bond wire center-to-center spacing W4. The parameter scan for W4 was performed within the range of 0.05–0.12 mm, with a scan increment set to 0.005 mm. Through systematic simulation optimization and result screening, the performance comparison results are shown in Figure 11.

As shown in Figure 11, within the operating frequency range of 1–20 GHz, the RF transmission performance of the model in this chapter increases with the increase in W4. When the inter-bond center spacing is w4 = 0.12 mm, the model exhibits the best RF transmission performance in terms of return loss and the lowest insertion loss, with a relatively smooth curve. Therefore, w4 = 0.12 mm is selected as the inter-bond center distance for further investigation in this paper.

3.2.2. Optimization of T-Type Matching Networks

This section addresses the parasitic effects introduced by bonding and the impedance mismatch of the bare die in a microstrip-to-bare die cascade structure by optimizing the T-type matching network. At high frequencies, the bond wire exhibits a composite equivalent model comprising series inductance and parallel parasitic capacitance, with series inductance being the dominant mismatch factor. Compensation is primarily achieved by widening the microstrip width and shortening its length. To reduce optimization variables and accelerate convergence, parameter optimization of L1, W2, and L2 in the T-type matching network was performed in ADS. Variables were set as follows: L1 from 0.12 to 0.4 mm, W2 from 0.28 to 0.6 mm, with a step size of 0.04 mm, and L2 within 0.12–0.2 mm with a step size of 0.02 mm. Performance comparison results obtained through simulation optimization and result screening are shown in Figure 12.

As shown in the figure, the T-type matching network significantly impacts the RF signal transmission performance. Certain dimensions can induce resonance: L1 = 0.16 mm, L2 = 0.14 mm, W1 = 0.55 mm, and W2 = 0.52 mm yield the optimal curve. At these dimensions, S₁₁ remains below −25.6 dB, S₂₁ exceeds −0.31 dB, the curve exhibits smoothness without resonance, and transmission performance is at its peak.

3.3. Stripline–Microstrip Interlayer Interconnect Structure Design

The primary signals transmitted between layers within LTCC substrates are radio frequency signals. To achieve effective interconnection between components on different layers and transmission lines within LTCC multilayer boards, this chapter will design a microstrip-to-microstrip via (ML-MSL) interconnect structure based on the substrate model described earlier.

A three-dimensional model of the via interconnect structure was established using HFSS. The initial via structure is shown in Figure 13, where the stripline is positioned at the center of the mid2 layer with a thickness of 0.01 mm. A row of vias is placed on both sides of the stripline, with a via radius r of 0.1 mm and an inter-via spacing d2 of 0.5 mm. The distance d3 from the via edge to the stripline is 0.24 mm. The via height matches the mid2 layer height to ensure electromagnetic fields remain confined within the transmission path without lateral leakage. The microstrip line width on the M1 layer and the adjacent via dimensions and spacing remain consistent with previous specifications. RF signals first enter the model via the 0.12 mm-wide stripline and subsequently propagate through the vias to the microstrip line. Based on empirical data, the initial via structure is set as shown in Figure 14: the center via inner diameter r1 is 0.1 mm, the stripline layer pad radius r2 is 0.15 mm, the microstrip line layer pad radius r3 is 0.2 mm, and the isolation pad radius r4 is 0.5 mm. The central via material remains consistent with previous specifications, utilizing co-fired silver conductor paste, while the isolation pad is positioned on layer M2.

3.3.1. Simulation Design of Via Interconnection Structures

In microwave and millimeter-wave circuits, when high-frequency signals propagate through vias between different layers, the discontinuity in via structure causes impedance mismatch. The resulting parasitic effects can adversely affect microwave transmission characteristics to some extent. To mitigate the impact of these parasitic effects, this section optimizes the size of the pads and isolation rings within this interconnect structure.

• Effect of Pad Radii r2 and r3 on Transmission Characteristics

The pad, as the critical link between transmission lines and vias in via interconnects, significantly influences the transmission characteristics of the via interconnect structure through its structural parameters. A pad variable analysis is first conducted. While keeping other parameters constant, r2 was varied between 0.14 and 0.17 mm and r3 between 0.15 and 0.3 mm, with a step size of 0.01 mm. Through simulation optimization and result screening, the performance comparison results are shown in Figure 15.

As shown in the figure, when r2 = 0.15 mm and r3 = 0.25 mm, the overall transmission characteristics are optimal, with a return loss exceeding 19.1 dB and an insertion loss of 0.9 dB at 20 GHz. Therefore, pads with r2 = 0.15 mm and r3 = 0.25 mm are selected for subsequent optimization of the via interconnect structure.

2.

The Effect of Isolation Disc R4 on Transmission Characteristics

Perform isolation disc variable analysis in HFSS software. Based on the preceding simulation, set the via radius r1 to 0.1 mm, the pad radius r2 to 0.15 mm, and r3 to 0.25 mm. Vary the isolation disc radius r4 between 0.45 mm and 0.55 mm with a step size of 0.02 mm. The simulation results are shown in Figure 16.

As shown in the figure, when the isolation disk radius r4 is less than 0.5 mm, signal transmission performance improves as the isolation disk radius increases. This occurs because the parasitic capacitance value of the interconnect structure is inversely proportional to the isolation disk size. A larger isolation disk effectively enhances the microwave transmission characteristics of the interconnect structure. However, when the isolation disk radius r4 exceeds 0.5 mm, transmission performance deteriorates. This occurs because increasing the isolation disk radius disrupts the ground plane structure of the microstrip and stripline. As frequency increases, the negative impact of this ground plane disruption becomes increasingly pronounced, thereby degrading the transmission performance of the interconnect structure. Therefore, an isolation disk radius of 0.5 mm was selected for the via interconnect structure design.

3.3.2. Optimization of Via Interconnection Structures

• Via Interconnection Design with Coaxial-Like Structure

To achieve superior signal integrity assurance and optimize high-frequency performance, a ground via array can be added around the through-hole to form a quasi-coaxial structure. The outer shielding layer of this structure provides a signal return path, constrains the field near the central via, prevents crosstalk between signals, and reduces transmission loss. The characteristic impedance of the quasi-coaxial structure can be approximated using the characteristic impedance calculation formula for coaxial cables:

$$\begin{array}{c}{Z}_0={\displaystyle \frac{60}{\sqrt{{\epsilon }_r}}}\ln {\displaystyle \frac{r5}{r1}}\end{array}$$

(3)

This design incorporates six ground vias, as shown in Figure 17. The outer ground vias have the same radius as the through-holes, with a thickness extending from layer M1 to layer M3. Preliminary calculations using the formula yield an equivalent outer conductor radius r5 of 0.75 mm. The dielectric material for the ground vias also utilizes silver conductor paste.

To determine the optimal equivalent outer conductor radius r5, all other parameters were held constant in the HFSS software. The via radius r1 was set to 0.1 mm, the pad radius r2 to 0.15 mm, r3 to 0.25 mm, and the isolation disk radius r4 to 0.5 mm. The r5 value was varied between 0.7 and 0.9 mm in increments of 0.05 mm. The simulation results are shown in Figure 18.

As shown in the figure, after incorporating a coaxial-like structure, when the equivalent outer conductor radius r5 = 0.8 mm, the interconnect structure achieves optimal shielding performance with a return loss improvement from −19 dB to −23.9 dB.

2.

Via Interconnect Structure Loaded with DGS Architecture

To achieve superior performance in the final integrated interconnect structure from the stripline to the bare chip, each submodule within the interconnect structure must exhibit excellent transmission characteristics. Although the quasi-coaxial structure described above demonstrates good performance, its return loss inevitably deteriorates during final integration, potentially failing to meet application requirements. Therefore, further optimization of the via interconnect structure in the aforementioned quasi-coaxial design is necessary. This paper proposes a square DGS structure positioned on the ground plane of the M3 layer directly beneath the center of the via hole. The square DGS structure is shown in Figure 19. For clarity, only a portion of the structure is retained in the model:

This subsection employs a square DGS structure to suppress high-frequency resonance in the coaxial-like via region. Through electromagnetic coupling with the coaxial-like structure, it compensates for impedance discontinuities in the transition zone.

DGS can significantly improve the transmission characteristics of the ML-via-MSL structure. Using the electromagnetic simulation software HFSS, a simulation analysis was performed on the square DGS unit structure. The parameters C and K were set within the range of 0.25–0.7 mm, with a step size of 0.05 mm. As shown in the figure, when C = 0.4 mm and K = 0.6 mm, the via interconnect structure exhibits S₁₁ < −31 dB and S₂₁ > −0.48 dB. Compared to Figure 16, the return loss improved by 11 dB, demonstrating excellent transmission characteristics. Analysis of Figure 20 indicates that an excessively small DGS structure may cause poor transmission performance due to insufficient disturbance of the ground current distribution in the defect region. This failure to effectively counteract the parasitic inductance of the quasi-coaxial via and the excessive equivalent capacitive reactance leads to capacitive mismatch at high frequencies. Conversely, an excessively large DGS structure may induce excessive electromagnetic coupling with the quasi-coaxial structure, introducing additional inductive reactance that disrupts impedance continuity and degrades transmission performance.

4. Results

4.1. Full-Path Cascade Simulation and Broadband Performance Verification

After completing the optimization of the matching network, bonding interconnect, and vertical via transition, full-path cascading simulations are performed to evaluate the overall broadband performance of the proposed LTCC bare-die interconnect structure. The optimized T-type matching network, gold-wire bonding model, and DGS-enhanced coaxial-like via structure are integrated into a unified 3D electromagnetic model, as shown in Figure 21.

4.2. Impact of T-Type Matching Networks and DGS on Transmission Performance of the Overall Interconnect Structure

The optimal parameters for each module have been determined from the preceding analysis. We now proceed to simulate and analyze the integrated interconnect structures for the stripline-to-bare-chip configuration. Structure 1 incorporates a T-type matching network and a DGS cascade structure (representing the final interconnect model). Structure 2 omits the T-type matching network, substituting the T-junction section with 50 Ω microstrip lines. Structure 3 is an interconnect structure on the GND2 layer without a square DGS structure. Structure 4 is a traditional stripline-to-bare-chip interconnect structure, which lacks both the T-matching network (the T-junction section is replaced by 50 Ω microstrip lines) and the square DGS structure on the GND2 layer. While keeping all other parameters constant, we compare the effects of the T-matching network and the square DGS structure on the model’s RF performance. The simulation results are shown in Figure 22.

Simulation results indicate that Structure 1 exhibits performance characteristics where S₁₁ < −23.1 dB and S₂₁ < 0.45 dB. The return loss of Structure 1 is significantly greater than that of Structures 2, 3, and 4, while its insertion loss is notably the smallest. Furthermore, it can be observed that the transmission performance of both the T-type matching circuit and the DGS structure alone is comparable, yet both outperform the traditional stripline-to-bare-chip interconnect structure. Within the 1–15 GHz range, the device exhibits excellent impedance matching and low insertion loss, making it suitable for high-performance systems such as broadband transceivers, front-end modules, and high-precision measurement links. Beyond 15 GHz, performance degrades to some extent due to increased gold-wire inductance and the excitation of higher-order modes in the via and stackup structure. However, the overall S-parameters remain within usable ranges, making the device suitable for non-critical applications up to 20 GHz, such as broadband monitoring, auxiliary links, or general signal transmission. Consequently, this structure offers functional usability across the entire 1–20 GHz range, delivering premium performance within its primary operating band of 1–15 GHz.

Table 1. Comparison table with other literature.

Reference	BW/GHz	Structure	S11/dB	Craftsmanship
[7]	DC-30	TL-Via-TL	<−16	LTCC
[8]	DC-50	BGA-TL-Chip	<−10	LTCC
[15]	DC-50	TL-Via-TL	<−20	PCB
[16]	1–20	TL-Via-TL-Chip	<−21.5	HTCC
[17]	2–18	BGA-Via-TL TL-Via-Chip	<−15 <−16	HTCC
This article	1–20	TL-Via-TL-Chip	<−23.1	LTCC

presents a comparison of the interconnection structures between this paper and other literature. As shown in the table, this design exhibits excellent transmission performance and demonstrates superior broadband interconnection characteristics.

5. Conclusions

This paper presents a systematic multi-layer collaborative optimization methodology for broadband bare-die interconnects in LTCC multilayer structures. By jointly addressing impedance matching, gold-wire bonding parasitic effects, and vertical interlayer transition discontinuities within a unified design framework, the proposed approach overcomes the limitations of conventional interconnect designs that rely on isolated or sequential optimization of individual submodules.

First, a compact T-type microstrip impedance matching network is designed based on the complex input impedance of the bare die, achieving effective broadband matching while satisfying the stringent dimensional constraints of LTCC fabrication. Second, to accurately capture frequency-dependent parasitic effects that are not adequately described by traditional π-type models, a high-fidelity three-dimensional gold-wire bonding model is established. Parametric optimization identifies an optimal bond center spacing that significantly improves impedance continuity and insertion loss flatness across a wide frequency range.

Furthermore, a coaxial-like via structure combined with a square defected ground structure (DGS) is proposed to enhance the broadband performance of stripline–via–microstrip transitions. This co-design effectively improves electromagnetic field confinement and compensates for impedance discontinuities in the vertical interconnect region. Full-path cascaded electromagnetic simulations demonstrate that the proposed interconnect structure achieves a return loss better than −23.1 dB and an insertion loss below 0.45 dB over the 1–20 GHz frequency range, outperforming conventional LTCC interconnect architectures by more than 10 dB in return loss and approximately 0.12 dB in insertion loss.

The results confirm that the proposed collaborative optimization strategy provides both superior broadband performance and strong engineering practicality. The presented design methodology and structural configurations offer reusable references for high-frequency LTCC bare-die integration and can be readily extended to other multilayer packaging platforms. Future work will involve physical processing tests and may be extended to the fields of interconnect reliability modeling and multi-chip co-design methodologies.