Design and Analysis of 15-Level and 25-Level Asymmetrical Multilevel Inverter Topologies

Abstract

This study aims to minimize component requirements by presenting a novel topology for a single-phase 15-level asymmetrical multilevel inverter. Utilizing an H-bridge configuration, the proposed design achieves a maximum 15-level output voltage using asymmetrical DC sources. The initial 15-level inverter structure is further enhanced to support a 25-level variant suitable for renewable energy applications, effectively reducing system costs and size. However, the increased component count in multilevel inverters poses reliability challenges, particularly concerning total harmonic distortion reduction, which remains a focal point for researchers. Various parameters, including total standing voltage, multilevel inverter cost function, and power loss, are analyzed for both the proposed 15-level and the expanded 25-level multilevel inverters. This study contributes a new topology for a single-phase 15-level asymmetrical multilevel inverter, optimizing component usage and paving the way for renewable energy integration. Despite the advantages of multilevel inverters, addressing reliability concerns related to total harmonic distortion reduction remains crucial for future advancements in this domain.

1. Introduction

Solar energy, recognized as a prominent renewable energy source, has gained substantial attention in the pursuit of sustainable energy solutions. Its widespread geographic availability and considerable potential for reducing carbon emissions make it an appealing option for addressing global energy challenges. Continuous advancements in solar technology have enhanced efficiency and lowered costs, fostering its widespread adoption. As nations transition towards cleaner energy systems, solar power plays a vital role in diminishing reliance on fossil fuels and mitigating climate change. Photovoltaic (PV) energy stands out due to its cost-effectiveness and environmental benefits. Ongoing research and system development focus on maximizing energy extraction from PV cells and ensuring seamless grid integration.

In recent years, multilevel inverters (MLIs) have emerged as a crucial technology owing to their capability to handle high power levels while offering advantages such as reduced harmonic distortion, improved power quality, and minimized switching losses with enhanced electromagnetic interference performance [1,2,3,4,5]. MLIs generate stepped voltage waveforms by utilizing various DC sources and power electronic circuits composed of multiple semiconductor switches [6]. The quality of the waveform improves as the number of levels increases. However, achieving high reliability and efficiency remains challenging due to the increased component count, leading to higher costs [7].

Ensuring a stable and reliable DC voltage supply is crucial for the efficient operation of MLIs, particularly in renewable energy applications. DC/DC converters significantly enhance the voltage quality and system reliability by regulating the voltage levels and reducing fluctuations. For instance, a robust sliding mode control for a quadratic boost converter, as proposed in [8], has demonstrated improved system stability and dynamic response. Similarly, a comparative study on high-gain DC/DC converter topologies in [9] highlights advanced techniques for voltage boosting, making them suitable for integration with MLIs in PV applications.

There are three primary MLI topologies: diode-clamped or neutral point clamped (NPC), flying capacitor (FC), and cascaded H-bridge (CHB) [10]. The CHB inverter consists of multiple single-phase H-bridge units and is further categorized into symmetric and asymmetric types based on the DC voltage levels [11]. In symmetric configurations, all DC voltage sources have equal magnitudes, whereas, in asymmetric types, the voltage magnitudes vary. Conventional CHB inverters generate three output levels—positive, negative, and zero. The total output voltage is determined by summing the individual output voltages from each unit [12,13]. CHB inverters are preferred for medium- and high-voltage applications, whereas FC and NPC inverters pose challenges in voltage balancing at higher voltage levels [14].

A novel topology featuring a reduced number of switches is proposed in [15], though it requires multiple voltage sources, which is a limitation. Optimal semiconductor device utilization is essential to overcome these complexities. In [16], an asymmetric inverter topology is introduced, incorporating bidirectional power switches that increase the number of IGBTs, subsequently raising the inverter cost. Other designs focus on reducing the number of power switches while increasing voltage levels [17,18]. These designs produce a DC step output, which is converted into an AC step using a full-bridge converter, limiting applications to high-voltage scenarios due to the full-bridge converter’s voltage-blocking constraints. Various novel topologies aim to minimize component count for single-phase and three-phase systems, including a three-phase system composed of three single-phase units presented in [19].

Certain topologies employ subunit MLIs that utilize fewer switches and DC sources to generate multilevel outputs [20]. Some designs incorporate bidirectional switches connected in antiparallel, enabling current conduction in both directions while reducing the switch count [21,22,23,24]. By cascading subunits, blocking voltage across switches decreases, achieving a modular structure. However, an increase in output levels results in a proportional rise in the switch count, which remains a drawback. Thus, there is a continuous demand for innovative MLI architectures that provide multiple levels while reducing components and blocking voltage, ultimately decreasing inverter costs. A packed H-bridge MLI topology, introduced recently, features basic units connected on either side of a full bridge [25,26]. In contrast, certain designs eliminate the H-bridge, focusing on minimizing voltage stress on circuit switches. Many of these topologies, however, require numerous components. The present study explores a hybrid cascade multilevel inverter (HCFMLI) topology incorporating a standard three-leg and H-bridge cells at the lower section, optimizing structures to reduce switches, capacitors, and standing voltage while maximizing output voltage steps [27].

A comparative analysis of cascaded MLI topologies employing symmetric and asymmetric configurations is presented in [28,29]. A novel multilevel cascade converter is introduced, utilizing an innovative technique to generate both odd and even output voltage levels by adjusting DC source values. Furthermore, an optimization algorithm is devised to minimize cost and circuit size.

Reference [30] proposes a cascade topology for multilevel converters based on series-connected sub-multilevel units, with two methods for determining DC source magnitudes. This topology is optimized to achieve various voltage levels with minimal components and peak switch voltage. Additionally, ref. [31] presents a sparse 13-level inverter that achieves sextuple-boosted output voltage using a single DC source, incorporating 14 switches, four capacitors, and two diodes. The cascade topology proposed in [32] generates all potential output voltage levels, with comparative analysis demonstrating its advantages over recent multilevel converters [33].

The topology in [34] introduces a single-phase MLI capable of producing symmetrical and asymmetrical output voltages. In symmetrical mode, it generates a 9-level output, whereas, in asymmetrical mode, it can achieve 13 and 17 levels using a single cell. Expanding the number of cells or switches further enhances output levels. Reference [35] presents a flying capacitor-based multilevel topology designed to reduce size and cost while supporting symmetric and asymmetric DC source configurations, achieving 9-level and 25-level outputs, respectively. Another topology in [36] introduces a 25-level asymmetric MLI with extended cascaded configurations to enhance voltage levels, supplemented by two algorithms for calculating DC source values per unit.

Further expansion of these topologies is feasible. In [37], a novel control scheme utilizing a genetic algorithm is implemented for resistive and motor loads, maintaining stable output voltage under load disturbances. Enhancements to cascaded MLIs are explored in [38]. The topology in [39,40] doubles the MLI output level while maintaining the same circuit components. The transistor-clamped H-bridge MLI in [41] achieves multiple output levels while sustaining high voltage and power ratings without increasing component ratings. This topology benefits from lower switching losses at high switching frequencies, maintaining high efficiency [38] through carrier-based PWM control. An analysis of MLI topologies under extreme wind conditions is examined in [42].

MLIs have gained traction in the power industry, significantly enhancing PV system power quality and efficiency. When integrated with PV systems, MLIs must be optimized to minimize size, cost, and voltage stress [43]. Reference [44] introduces a novel single-phase MLI requiring fewer power switches and driver circuits compared to existing designs. Additionally, ref. [45] presents an improved asymmetrical MLI with modifications that yield 15 output voltage levels. The work in [46] proposes a new cascaded single-phase MLI utilizing innovative H-bridge units, accompanied by nine algorithms for generating all output voltage levels.

This work proposes a novel 15-level and 25-level asymmetrical MLI topology that significantly reduces the number of switches while maintaining high output voltage levels. Unlike previous topologies that either increase switch count or introduce high TSV values, our proposed design minimizes TSV while maintaining a modular structure suitable for renewable energy applications. The key contributions of this work include:

• A new asymmetrical CHB-based MLI topology that reduces the required number of power semiconductor switches while maintaining high output voltage levels.
• Optimization of the total standing voltage (TSV) and cost function to improve the inverter’s efficiency and affordability.
• A comparative evaluation demonstrating that the proposed topology achieves lower total harmonic distortion (THD) and higher or similar efficiency than existing designs.

The presented design optimally balances component count, voltage stress distribution, and power conversion efficiency. This is particularly beneficial for applications such as grid-connected PV systems, dynamic voltage restorers (DVRs), and battery storage systems, where minimizing cost and maximizing performance are crucial.

This paper is structured as follows: Section 2 details the modeling of the proposed 15-level and 25-level MLIs. Section 3 evaluates performance metrics, while Section 4 compares the proposed MLIs with existing designs. Section 5 presents results and further comparisons, leading to the conclusions outlined in Section 6.

2. Proposed Asymmetrical Multilevel Inverters

This section presents the proposed 15-level and 25-level MLI structures. The characterization of the MLIs is based on a simplified circuit, as the primary objective of this work is to evaluate the advantages of the proposed design. The asymmetrical voltages for the MLIs are derived from independent DC sources. Additionally, the loads used in the MLI characterization include a resistive load and a resistive-inductive load.

2.1. DC Sorce Characterization

In PV applications, a DC/DC converter is required to properly connect a PV generator with the suggested MLI. This converter must have a single input and multiple outputs, with the number and voltage of outputs depending on the MLI design. The 15-level MLI requires three different output voltages, while the 25-level MLI requires four different voltages.

Different topologies for Single-Input and Multiple-Output (SIMO) DC/DC converters are presented in [47]. In this reference, some isolated DC/DC converter topologies, such as Single-Switch Flyback converter, Single-Switch Forward converter, isolated Zeta converter, isolated Single-Ended Primary-Inductor Converter (iSEPIC), and isolated Ćuk converter, are introduced and proposed as frontend in PV applications.

In photovoltaic (PV) applications, a DC/DC converter is required to interface the PV generator with the proposed MLIs properly. For this purpose, a Single-Input Multiple-Output DC/DC converter is employed, providing the necessary multiple voltage levels.

The following SIMO DC/DC converter topologies could be selected due to their efficiency and suitability for integration with the proposed MLI:

• Isolated SEPIC Converter: Provides multiple output voltages while maintaining galvanic isolation, enhancing reliability in PV applications.
• Isolated Ćuk Converter: Offers high voltage gain with reduced switching stress, minimizing power losses.
• Flyback Converter: Simple implementation with single-switch control but with limitations in handling high power levels.

Nevertheless, the iSEPIC converter is particularly useful when an output voltage higher and/or lower than the input voltage is needed, including galvanic isolation. As stated in [48], iSEPIC converters are used in PV applications as an interface between varying solar panel voltages and the system’s battery or grid voltage requirements.

Given the voltage step requirements, the iSEPIC converter is a good selection in the proposed application due to its regulated multi-output capability, low ripple characteristics, and compatibility with renewable energy sources.

Assuming that the maximum output voltage of the proposed MLIs is V_Omax = 400 V, the expression utilized to determine the minimum step of the MLI output voltage (V_Ostep) is presented in Equation (1), where nl is the MLI number of output voltage levels.

$$V_{Ostep}={\displaystyle \frac{V_{Omax}}{\frac{nl-1}{2}}} \to V_{Ostep}={\displaystyle \frac{800}{nl-1}}$$

(1)

The minimum voltage step in the case of the 15-level MLI is V_Ostep-15 ≈ 57 V, and in the case of the 25-level MLI, this voltage is V_Ostep-25 ≈ 33 V.

Table 1. DC asymmetric voltages used in the proposed MLIs.

DC Voltage	15-Level	25-Level
V1	57 V	33 V
V2	114 V	66 V
V3	228 V	132 V
V4	---	165 V

summarizes the DC voltage values as voltage input for the two proposed MLIs.

2.2. Asymmetrical 15-Level MLI Topology

Figure 1 shows the proposed 15-level MLI, which consists of eleven switches, S₁ through S₁₁, and three voltage sources, labeled V₁, V₂, and V₃. The three DC sources are stacked asymmetrically due to their different voltage levels, and they are by the values reported in Table 1. The proposed MLI architecture minimizes the number of power quality issues and achieves lower Total Stating Voltage (TSV) compared to other proposed topologies in the specialized literature.

Table 2. Switching table for the 15-Level MLI.

Level	Switches State											Active DC Sources	Output Voltage
	S1	S2	S3	S4	S5	S6	S7	S8	S9	S10	S11
L1	√			√	√			√	√			V1 + V2 + V3	+7·VOstep-15
L2		√		√	√			√	√			V2 + V3	+6·VOstep-15
L3	√			√		√		√	√	√		V1 + V3	+5·VOstep-15
L4	√		√		√			√	√			V3	+4·VOstep-15
L5	√			√	√		√		√			V1 + V2	+3·VOstep-15
L6		√		√	√			√		√	√	V2	+2·VOstep-15
L7	√			√		√		√			√	V1	+VOstep-15
L8	√		√		√			√		√	√	---	0
L9		√	√		√			√		√	√	−V1	−VOstep-15
L10	√		√			√		√			√	−V2	−2·VOstep-15
L11		√	√			√		√			√	−(V1 + V2)	−3·VOstep-15
L12		√		√		√	√				√	−V3	−4·VOstep-15
L13		√	√		√		√			√	√	−(V1 + V3)	−5·VOstep-15
L14	√		√			√	√				√	−(V2 + V3)	−6·VOstep-15
L15		√	√			√	√				√	−(V1 + V2 + V3)	−7·VOstep-15

depicts the main characteristics of the 15 operation modes (or level states) of the proposed 15-level MLI. The state of each switch (mark “√” denotes the ON state) in each level state, the active DC sources, and the MLI output voltage are shown.

The output voltage column displays the resulting voltage for the corresponding switching state, ranging from −7·V_Ostep-15 to +7·V_Ostep-15 in increments of V_Ostep-15. This range of output voltages allows for versatile applications and precise control over the system’s output.

Figure 2 shows the results obtained from the simulation of the proposed 15-level MLI operation. Switches are in a “1” state if they are turned ON; otherwise, they are in a “0” state. The MLI provides an output voltage of 400 V using a 100 Ω resistor as a load.

2.3. Asymmetrical 25-Level MLI Topology

Figure 3 shows the proposed 25-level MLI topology. The system comprises eleven switches, S_a and S₁ through S₁₀, and four voltage sources, labeled V₁, V₂, V₃, and V₄. The four DC sources are stacked asymmetrically due to their different voltage levels, and they are by the values reported in Table 1. The proposed MLI architecture minimizes the number of power quality issues and also achieves lower Total Stating Voltage (TSV) compared to other similar topologies proposed in the specialized literature.

Table 3. Switching table for the 25-level MLI.

Level	Switching States											Active DC Sources	Output Voltage
	Sa	S1	S2	S3	S4	S5	S6	S7	S8	S9	S10
L1		√			√	√			√	√		V1 + V2 + V3 + V4	+12·VOstep-25
L2			√		√	√			√	√		V2 + V3 + V4	+11·VOstep-25
L3		√			√		√		√	√		V1 + V3 + V4	+10·VOstep-25
L4		√		√		√			√	√		V3 + V4	+9·VOstep-25
L5			√	√		√			√	√		−V1 + V3 + V4	+8·VOstep-25
L6	√			√	√	√				√		V1 + V2 + V3	+7·VOstep-25
L7	√		√		√	√				√		V2 + V3	+6·VOstep-25
L8	√	√			√		√			√		V1 + V3	+5·VOstep-25
L9	√	√		√		√				√		V3	+4·VOstep-25
L10		√			√	√			√		√	V1 + V2	+3·VOstep-25
L11			√		√	√			√		√	V2	+2·VOstep-25
L12		√			√		√		√		√	V1	+1·VOstep-25
L13		√		√		√			√		√	---	0
L14			√	√		√		√		√		−V1	−1·VOstep-25
L15		√		√			√	√		√		−V2	−2·VOstep-25
L16			√	√			√	√		√		−(V1 + V2)	−3·VOstep-25
L17	√	√			√		√				√	V1 −V4	−4·VOstep-25
L18	√		√		√		√				√	−V4	−5·VOstep-25
L19	√		√	√		√					√	−(V1 + V4)	−6·VOstep-25
L20	√	√		√			√				√	−(V2 + V4)	−7·VOstep-25
L21	√		√	√			√				√	−(V1 + V2 + V4)	−8·VOstep-25
L22			√		√		√	√			√	−(V3 + V4)	−9·VOstep-25
L23			√	√		√		√			√	−(V1 + V3 + V4)	−10·VOstep-25
L24		√		√			√	√			√	−(V2 + V3 + V4)	−11·VOstep-25
L25			√	√			√	√			√	−(V1 + V2 + V3 + V4)	−12·VOstep-25

depicts the main characteristics of the 25 operation modes (or level states) of the proposed 25-level MLI. The state of each switch (mark “√” denotes the ON state) in each level state, the active DC sources, and the MLI output voltage are shown.

The output voltage column displays the resulting voltage for the corresponding switching state, ranging from −12·V_Ostep-25 to +12·V_Ostep-25 in increments of V_Ostep-25. This range of output voltages allows for versatile applications and precise control over the system’s output.

Figure 4 shows the obtained simulation results of the proposed 25-level MLI operation. Switches are in a “1” state if they are turned ON; otherwise, they are in a “0” state. The MLI provides an output voltage of 400 V using a 100 Ω resistor as a load.

3. MLI Performance Evaluation

Evaluating the performance of multilevel inverters is crucial for optimizing their efficiency and cost-effectiveness in various applications. Total standing voltage (TSV), representing the sum of voltage levels in the inverter, serves as a key metric in assessing its output quality and harmonic content. Additionally, the component count per level factor offers insights into the complexity and scalability of the inverter design, impacting both manufacturing and maintenance costs.

Cost functions provide a comprehensive framework for assessing the economic viability of different multilevel inverter configurations, considering factors such as component prices, assembly expenses, and operational costs. Furthermore, analyzing power loss and efficiency helps quantify energy conversion losses and overall system effectiveness, guiding design choices toward achieving optimal performance with minimal energy wastage. Integrating these metrics facilitates comprehensive performance evaluation, enabling engineers to refine multi-level inverter designs for enhanced functionality and sustainability.

3.1. Modulation Strategies for Proposed MLIs

This section presents the modulation strategies that can be implemented for the proposed 15-level and 25-level MLIs, detailing both carrier-based and space vector modulation techniques. The selection of modulation techniques is guided by their impact on Total Harmonic Distortion (THD), switching losses, and computational complexity.

The transition between different modulation schemes is based on their influence on key performance metrics, as outlined below:

• Total Harmonic Distortion (THD): Space vector modulation (SVM) typically provides a lower THD compared to carrier-based PWM methods due to its ability to synthesize the reference voltage vector more effectively.
• Switching Losses: Carrier-based techniques such as Sinusoidal Pulse Width Modulation (SPWM) generally result in higher switching losses, as they require more switch transitions per cycle. SVM, on the other hand, optimizes switching sequences, reducing energy dissipation.
• Computational Complexity: While SVM offers superior harmonic performance and lower losses, it requires higher computational resources, making it more challenging to implement in real-time embedded control systems.

To characterize the proposed topologies, a modulation strategy based on SPWM was chosen. The implementation of SVM strategies, which, according to theory, will offer better results in terms of THD and loss, is left for future work.

3.2. Total Standing Voltage and Component Count per Level Factor

The TSV significantly influences the circuit’s switch choice. The blocking voltage for all the semiconductors in the layout is added up to produce this value. The calculation of the TSV involves determining the total maximum blocking voltages (MBV) across all switches (from i = 1, 2, 3, …, m), which is derived from Equation (2).

$$TSV=\sum _{i=1}^m{MBV}_{Si}={MBV}_{S1}+{MBV}_{S2}+{MBV}_{S3}+\cdots +{MBV}_{Sn}$$

(2)

The TSV per unit (TSV_PU), representing the ratio of the overall TSV to the maximum voltage levels of the proposed MLI, can be mathematically derived using Equation (3).

$${TSV}_{PU}={\displaystyle \frac{TSV}{V_{Omax}}}$$

(3)

The normalized voltage stress (NVS) refers to the comparison between the voltage stress experienced by a single switch and the maximum stress endured by the circuit, as determined by Equation (4).

$$NVS={\displaystyle \frac{Voltage stress across switch}{Maximum voltage stress in the circuit}}$$

(4)

3.2.1. TSV of 15-Level MLI

The 15-level MLI has 11 unidirectional switches. The maximum voltage stress (or MBV) across the unidirectional switches is MBV_Si, where i = 1, 2, 3, …, n. The stress across each unidirectional switch is represented as follows:

MBV_S1 = V₁ = 1·V_Ostep-15
MBV_S2 = V₁ = 1·V_Ostep-15
MBV_S3 = V₁ + V₂ = 3·V_Ostep-15
MBV_S4 = V₂ + V₁ = 3·V_Ostep-15
MBV_S5 = V₂ = 2·V_Ostep-15
MBV_S6 = V₂ = 2·V_Ostep-15
MBV_S7 = V₃ = 4·V_Ostep-15
MBV_S8 = V₃ = 4·V_Ostep-15
MBV_S9 = V₁ = 1·V_Ostep-15
MBV_S10 = V₂ = 2·V_Ostep-15
MBV_S11 = V₁ = 1·V_Ostep-15

The TSV is calculated from Equation (5).

$$TSV=\left(1+1+3+3+2+2+4+4+1+2+1\right)·V_{Ostep\text{-}15}=24·V_{Ostep\text{-}15}$$

(5)

Table 4. Normalized voltage stress for power switches of 15-level MLI.

Switch	MBV	NVS	Impact of Stress on Switches
S1	1·VOstep-15	1·VOstep-15/4·VOstep-15	25%
S2	1·VOstep-15	1·VOstep-15/4·VOstep-15	25%
S3	3·VOstep-15	3·VOstep-15/4·VOstep-15	75%
S4	3·VOstep-15	3·VOstep-15/4·VOstep-15	75%
S5	2·VOstep-15	2·VOstep-15/4·VOstep-15	50%
S6	2·VOstep-15	2·VOstep-15/4·VOstep-15	50%
S7	4·VOstep-15	4·VOstep-15/4·VOstep-15	100%
S8	4·VOstep-15	4·VOstep-15/4·VOstep-15	100%
S9	1·VOstep-15	1·VOstep-15/4·VOstep-15	25%
S10	2·VOstep-15	2·VOstep-15/4·VOstep-15	50%
S11	1·VOstep-15	1·VOstep-15/4·VOstep-15	25%

depicts the voltage stress distribution across each power switch within a 15-level MLI, alongside the maximum stress. S₁, S₂, S₉, and S₁₁ demonstrate the lowest stress and normalized voltage stress (NVS) levels, both at V_Ostep-15 and 25%, respectively. On the other hand, S₅, S₆, and S₁₀ experience this stress and NVS twice, each at 2·V_Ostep-15 and 50%. Conversely, S₃ and S₄ endure triple this stress and NVS, rated at 3·V_Ostep-15 and 75%, respectively. In contrast, S₇ and S₈ bear the highest voltage stress at 4·V_Ostep-15, accompanied by an NVS of 100%.

3.2.2. TSV of 25-Level MLI

The proposed 25-level MLI has 11 switches, of which one switch is bidirectional and 10 switches are unidirectional. Voltage stress across the bidirectional switch is defined as half of the applied voltage, as is stated in Equation (6).

$${MBV}_{Sa}={\displaystyle \frac{V_3+V_4}{2}}={\displaystyle \frac{\left(4+5\right)·V_{Ostep-25}}{2}}=4.5·V_{Ostep\text{-}25}$$

(6)

The maximum voltage stress (or MBV) across the unidirectional switches is MBV_Si, where i = 1, 2, 3, …, n. The stress across each unidirectional switch is represented as follows:

MBV_S1 = V₁ = 1·V_Ostep-25
MBV_S2 = V₁ = 1·V_Ostep-25
MBV_S3 = V₁ + V₂ = 3·V_Ostep-25
MBV_S4 = V₁ + V₂ = 3·V_Ostep-25
MBV_S5 = V₂ = 2·V_Ostep-25
MBV_S6 = V₂ = 2·V_Ostep-25
MBV_S7 = V₃ = 4·V_Ostep-25
MBV_S8 = V₄ = 5·V_Ostep-25
MBV_S9 = V₂ = 2·V_Ostep-25
MBV_S10 = V₂ = 2·V_Ostep-25

And the TSV is calculated from Equation (7).

$$TSV=\left(4.5+1+1+3+3+2+2+4+5+2+2\right)·V_{Ostep\text{-}25}=29.5·V_{Ostep\text{-}25}$$

(7)

Table 5. Normalized voltage stress for power switches of 25-level MLI.

Switches	MBV	NVS	Impact of Stress on Switches
Sa	4.5·VOstep-25	4.5·VOstep-25/9·VOstep-25	50%
S1	1·VOstep-25	1·VOstep-25/9·VOstep-25	11.11%
S2	1·VOstep-25	1·VOstep-25/9·VOstep-25	11.11%
S3	3·VOstep-25	3·VOstep-25/9·VOstep-25	33.33%
S4	3·VOstep-25	3·VOstep-25/9·VOstep-25	33.33%
S5	2·VOstep-25	2·VOstep-25/9·VOstep-25	22.22%
S6	2·VOstep-25	2·VOstep-25/9·VOstep-25	22.22%
S7	4·VOstep-25	4·VOstep-25/9·VOstep-25	44.44%
S8	5·VOstep-25	5·VOstep-25/9·VOstep-25	55.55%
S9	2·VOstep-25	2·VOstep-25/9·VOstep-25	22.22%
S10	2·VOstep-25	2·VOstep-25/9·VOstep-25	22.22%

presents the voltage stress distribution among each power switch within a 25-level MLI, alongside the maximum stress. S₁ and S₂ exhibit the lowest stress and normalized voltage stress (NVS) levels, both at 1·V_Ostep-25 and 11.11%, respectively. S₅, S₆, S₉, and S₁₀ encounter this stress and NVS twice, each at 2·V_Ostep-25 and 22.22%. Meanwhile, S₃ and S₄ sustain triple this stress and NVS, rated at 3·V_Ostep-25 and 33.33%, respectively. Among them, S₇ experiences the least stress and NVS at 4·V_Ostep-25 and 44.44%, respectively. In contrast, S₈ faces the highest voltage stress at 5·V_Ostep-25, accompanied by an NVS of 55.55%.

Lastly, S_a registers a stress level of 4.5·V_Ostep-25 with an NVS of 50%, representing half of the maximum NVS.

3.3. Component Count per Level Factor

Inverters with low TSV values are based on switches with low maximum blocking voltages, which reduces construction costs. The element count level factor is also considered to obtain the number of partial elements involved in the construction of the inverter. The component count factor represents the total number of semiconductors used in a circuit. A reduced number of semiconductors will reduce the circuit resistance, and this reduces losses and increases the system efficiency. The component count per level factor (F_CCL) is calculated from Equation (8).

$$F_{CCL}={\displaystyle \frac{N_S+N_D+N_C+N_{DK}+N_{DC}}{N_L}}$$

(8)

where N_S stands for the number of switches, N_D stands for the number of diodes, N_C stands for the number of capacitors, N_DK stands for the number of gate driver circuits, N_DC is the number of DC sources used in the circuit, and N_L stands for the number of levels of the considered MLI.

3.4. Cost Functions

The use of a cost function of MLI is an important factor when comparing MLI in terms of possible economic cost. Equation (9) formulates the cost function (CF) used to characterize the proposed MLI. Parameters such as the total standing voltage and the component count factor are used in its definition [49].

$$CF=N_S+N_{DK}+N_{DC}+N_D+N_C+\alpha ·{TSV}_{PU}$$

(9)

where TSV_PU stands for the total standing voltage per unit, and it is calculated by Equations (3) and (5) or (7).

The parameter α in Equation (9) is a weight coefficient that multiplies the total standing voltage per unit. In this work, two possible values for this coefficient have been considered, one less than unity (α = 0.5) and another greater than one (α = 1.5).

Since neither diodes nor capacitors are used in the suggested MLI topologies, the cost function described in Equation (9) can be simplified to that presented in Equation (10).

$$CF=N_S+N_{DK}+N_{DC}+\alpha ·{TSV}_{PU}$$

(10)

Finally, the cost-effectiveness of the proposed MLI is determined using the cost function per level (CF_L), that is, the value of the cost function determined by Equation (10) divided by the number of levels of the MLI considered, as is shown in Equation (11).

$${CF}_L={\displaystyle \frac{N_S+N_{DK}+N_{DC}+\alpha ·{TSV}_{PU}}{N_L}}$$

(11)

3.5. Power Loss and Efficiency

Switch conduction losses and switching losses make up the total switch losses. Equation (12) is used to determine the conduction losses (P_cl) for each switch [49,50,51].

$$P_{cl}\left(t\right)=\left[V_S+R_S{i}^{\beta }\left(t\right)\right]·i\left(t\right)$$

(12)

where i is the peak output current, R_S is the conduction resistance of the switch (in ON-state), V_S is the voltage drop across the switch, and β is a switch specification constant usually provided by the manufacturer. This parameter models the conduction losses considering the nonlinearity of the device’s voltage drops as a function of current, and it is an empirical model commonly used in engineering practice. If the value of this parameter is unknown, it is common to use the value β = 1, as it represents the worst case.

Equation (13) provides the generalized relation for calculating the average conduction power losses (P_CL), considering the number of switches (N_SW) conducting at the same time (t) to produce each level. T_O indicates the period of the output voltage waveform.

$$P_{CL}={\displaystyle \frac{1}{T_O}}{\int }_0^{T_O}\left[N_{SW}\left(t\right)·P_{cl}\left(t\right)\right]dt$$

(13)

The switching losses (P_SL) can be calculated using Equation (14) [49]:

$$P_{SL}=f\left[{\sum }_{q=1}^{N_{SW}}\left({\sum }_{i=1}^{N_{ON}}{E}_{ONqi}+{\sum }_{i=1}^{N_{OFF}}{E}_{OFFqi}\right)\right]$$

(14)

where f is the fundamental frequency, N_ON and N_OFF are the number of times in which the switch q turns ON or turns OFF in one fundamental cycle, and E_ON and E_OFF are the turn-on and turn-off energy loss, respectively.

The total power losses (P_TL) are calculated from Equation (15):

$$P_{TL}=P_{CL}+P_{SL}$$

(15)

The efficiency (ɳ) of the MLI is calculated from Equation (16):

$$\eta ={\displaystyle \frac{P_{OUT}}{P_{IN}}}={\displaystyle \frac{P_{OUT}}{P_{OUT}+P_{TL}}}$$

(16)

where P_OUT and P_IN are the MLI output and input powers. Finally, the output inverter power (P_OUT) can be estimated from Equation (17), where V_RMS and I_RMS are the root mean square value of the output voltage and current, respectively.

$$P_{OUT}=V_{RMS}·I_{RMS}$$

(17)

4. Comparative Studies

This section provides a comparative analysis of the proposed MLI with other topologies from previous research. The comparison includes parameters such as the number of switches, DC sources, gate driver circuits, TSV, cost function, and efficiency. The results indicate that the proposed topology achieves a balance between component reduction, cost efficiency, and harmonic performance.

4.1. Comparative with the Proposed 15-Level MLI

It should be noted that the proposed 15-level MLI architecture is less expensive than other modern designs.

Table 6. Characteristics of 15-level MLI designs.

Reference	NL	NS	NDK	NDC	ND	NC	FCCL	TSVPU	CFL
									α = 0.5	α = 1.5
[43]	15	16	16	7	-	-	2.60	-	-	-
[44]	15	10	10	5	2	-	1.80	1.06	1.84	1.91
[45]	15	10	10	5	-	-	1.66	-	-	-
[46]	15	10	10	4	-	-	1.60	4.60	1.75	2.06
Proposed MLI	15	10	10	3	-	-	1.53	3.42	1.65	1.88

compares the proposed MLI to several present topologies by considering important elements such as the number of switches, used DC sources, gate driver circuits, capacitors, overall standing voltage, and components at each level. When overall standing voltage is compared to the other topologies, it is found that the proposed design has the smallest value. The proposed 15-level MLI has a low value of cost function per level, 1.65 and 1.88 for the values of α 0.5 and 1.5, respectively.

Figure 5 provides a comparative analysis of different 15-level MLI topologies. Each subfigure (a to f) illustrates a distinct aspect of the MLI topologies, comparing the references [43,44,45,46] and the proposed system. (a) Switch count (N_S): This bar chart displays the number of switches used in each topology. The proposed topology shows the same or a low number of switches compared to the reference topologies, indicating an efficient design that could result in low cost and potentially high reliability. (b) DC source count (N_DC): This graph illustrates the number of DC sources required for each topology. The proposed system uses fewer DC sources than the other topologies, suggesting improved power efficiency and reduced complexity in the power supply design. (c) Gate driver circuit count (N_DK): Here, the number of gate driver circuits is compared. As with the number of switches, the proposed topology requires the same or fewer gate driver circuits than those proposed in the compared topologies. This could lead to a simple control scheme and possibly similar operating costs. (d) Total standing voltage per unit (TSV_PU): This bar chart indicates the TSV_PU for each topology. The proposed topology presents an intermediate value with respect to the topologies for which the value of this parameter is known. (e) Component count per level (F_CCL): This plot shows the component count per level. The proposed system demonstrates a lower count, indicating a less complex system per level, which might contribute to ease of maintenance and scalability. (f) Cost function per level count (CF_L): The final graph compares the cost function per level; the proposed system shows a slightly lower cost per level and within a competitive range. This lower cost may allow balancing the performance of the proposed system being lower or equal when other parameters used in this comparison are evaluated.

Overall, the proposed system appears to outperform the referenced topologies in terms of reduced component counts, which are beneficial for creating more compact, cost-effective, and efficient inverters. The lower value obtained in the cost function per level for the proposed system indicates that it is possible to compensate for a higher TSV than that reported by some of the topologies used in the comparison.

4.2. Comparative with the Proposed 25-Level MLI

Notably, the proposed 25-level MLI architecture is less expensive than other modern designs.

Table 7. Characteristics of 25-level MLI designs.

Reference	NL	NS	NDK	NDC	ND	NC	FCCL	TSVPU	THD (%)	CFL
										α = 0.5	α = 1.5
[30]	25	14	10	4	-	4	1.28	6.16	4.38	1.40	1.65
[31]	25	12	10	4	-	-	1.04	5.00	-	1.14	1.34
[32]	25	20	16	8	-	-	1.76	3.33	-	1.83	1.96
[33]	25	15	15	6	-	-	1.44	4.50	-	1.53	1.71
[34]	25	15	15	3	-	3	1.44	2.00	-	1.48	1.56
[35]	25	12	12	2	-	2	1.12	4.00	4.20	1.20	1.36
[36]	25	10	10	4	8	-	1.28	4.50	3.26	1.37	1.55
Proposed MLI	25	11	11	4	-	-	1.04	2.43	3.20	1.09	1.19

compares the proposed MLI with different current configurations while adjusting for critical elements like the number of switches, the amount of DC sources, the amount of gate driver circuits, the number of capacitors, the quantity of overall standing output power, and the number of components per level.

In comparison, the proposed 25-level MLI reports a low THD value of 3.20 in contrast to the THD reported in [30,35,36] using a switch count of 10 to 14 and has a least-cost function value as tabulated in Table 7.

Figure 6 compares different 25-level MLI topologies, including several references and a proposed system. Each Figure 6a–f targets a specific parameter: Figure 6a, switches count (N_S): The bar chart suggests that the proposed system requires a lower number of switches compared to most of the reference topologies, only one of them has a lower number of switches. Fewer switches imply lower converter costs and complexity. Figure 6b, DC source count (N_DC): Three of the inverters compared have the same DC source requirement as the proposed topology. On the other hand, two of them use more DC sources and two use less. Fewer DC sources means lower costs and a simpler energy management system. Figure 6c, gate driver circuit count (N_DK): The proposed topology shows a moderate number of gate driver circuits needed, which indicates a balance between control complexity and hardware requirements. Figure 6d, total standing voltage per unit (TSV_PU): The proposed system ranks in the middle range in terms of TSV. This indicates that while it is not the most compact, it maintains a reasonable balance between size and functionality. Figure 6e, component count per level (F_CCL): As for the number of components per level, the proposed system uses fewer components than most of the referenced systems, only one of them having the same value for this parameter. This could be indicative of a design that privileges performance and flexibility by using a smaller number of components. Figure 6f, cost function per level (C_FL): The cost function analysis shows two scenarios for the proposed system: one with a significance level of 0.5 and one with 1.5. In both cases, the cost function per level of the proposed system is lower than that of all reference topologies, suggesting that while the proposed system may not offer benefits in other aspects, it has a lower cost.

In summary, Figure 6 indicates that the proposed 25-level MLI system has been designed with certain trade-offs in mind. It features competitive values in the number of DC sources required, the number of switches used, and has a competitive TSVPU value. This is achieved with the lowest number of components per level and the lowest cost function. These trade-offs reflect a design optimized for good performance and the specific requirements of the selected application while keeping the cost or number of components used low.

4.3. Considerations on the Design Optimization of the Proposed MLIs

The proposed MLI. The proposed 15-level and 25-level MLIs are designed with specific trade-offs to balance performance, cost efficiency, and component count minimization. One of the key considerations in the proposed design is the prioritization of minimizing the cost function over further reducing Total Standing Voltage (TSV). The rationale behind this decision is as follows:

• Economic Viability: While reducing TSV can enhance reliability, it often requires additional components or more expensive semiconductor switches with higher voltage ratings. This increases manufacturing costs, making the inverter less attractive for cost-sensitive applications such as renewable energy systems and residential power converters.
• Component Count Reduction: A lower TSV often necessitates additional capacitors, diodes, or switch redundancy, which would increase the overall component count. Keeping the number of components low is critical for simplified circuit design, ease of maintenance, and reduced failure rates.
• Scalability and Practical Implementation: Minimizing the cost function ensures that the proposed MLI remains scalable for various voltage levels. By striking a balance between TSV and cost, the topology can be adapted for medium- and high-power applications without significantly increasing complexity.
• Operational Efficiency: Although TSV reduction can lower stress on switches, proper control strategies (such as optimized PWM techniques and switching schemes) mitigate excessive voltage stress without requiring additional components.

Table 8. Comparison of the key factors influencing the proposed design.

Parameter	Trade-Off Consideration	Justification
Total Standing Voltage (TSV)	Moderate Reduction	Lower TSV improves switch reliability, but excessive reduction increases component count and cost.
Component Count	Minimized	Fewer components reduce system complexity and improve cost-effectiveness.
Cost Function	High Priority	Optimized to ensure an affordable and scalable design.
Harmonic Performance (THD)	Balanced	Achieved through effective modulation strategies without adding extra hardware.
Switching Losses	Moderate Control	Switching frequency and modulation schemes help mitigate energy losses.

compares the key factors influencing the proposed design choices:

By striking a balance between TSV, cost, and efficiency, the proposed MLIs achieve an optimized design suitable for typical applications while maintaining economic feasibility.

5. Simulation and Experimental Results

This section shows the results obtained in the simulations and the laboratory tests carried out on the proposed MLI.

5.1. Simulation and Test of the Proposed 15-Level MLI

Using MATLAB/Simulink 2022a the numerical simulations of the proposed 15-level MLI were performed. Figure 7 shows the voltage levels of the switching states of the inverter output voltage. Figure 8 shows the inverter output voltage as V_O = 400 V and output current as I_O = 4 A, respectively (a 100 Ω resistor is used as a load). According to Figure 9, the THD obtained using the FFT analysis is 3.35%. Since the amplitude of the harmonics is very small compared to the fundamental component of the signal, a zoom is also included in the area of interest of the spectrum.

The numerical simulations are validated in the laboratory using an inverter arrangement. The prototype comprises three DC input sources (V₁, V₂, and V₃), eleven 3600 V, 75 A IGBTs, and a 100 Ω load resistor.

To validate the simulation results, a hardware prototype was developed and tested. The experimental setup consisted of the following key components:

Power Supplies:

• Programmable DC Power Supply: 600 V, 10 A, Model N8900 Series, Keysight Technologies, Colorado Spring, CO, USA.
• Multiple isolated DC voltage sources configured for asymmetrical voltage levels per MLI requirements.

Switching Devices:

• IGBT Modules: 600 V, 75 A, Model CM75DU-12, Powerex Inc., Philadelphia, PA, USA.
• Gate Driver ICs for IGBT triggering: 1ED020I12-F2, Infineon Technologies, Munich, Germany.
• Optocouplers for isolation between control and power circuits: TLP250, Toshiba Electronic Devices & Storage Corporation, Tokyo, Japan.
• Control Unit:
• Real-time interface controller: RTI1104, dSPACE, Paderborn, Germany. Interfaced with MATLAB/Simulink.
• PWM generation and switching signal control using predefined switching angles.
• DSP/FPGA-based implementation for high-speed computation and real-time data acquisition.

Measurement Instruments:

• Oscilloscope: 200 MHz, 2 GS/s, Model TDS 2024B, Tektronix, Bracknell, UK. Used for analysis of output voltage and switching signal.
• Load Configuration:
• Resistive Load: 100 Ω high-power resistor (10 kW rated).
• Inductive Load: Motor load with L = 98 mH, R ≈ 50 Ω.

The dSPACE RTI1104 (Real-Time Interface) is a robust and versatile hardware-in-the-loop (HIL) system designed for real-time simulation and rapid control prototyping. It integrates seamlessly with MATLAB/Simulink, enabling engineers to develop and test control algorithms and embedded systems efficiently. The RTI1104 provides high-performance I/O capabilities, including analog and digital inputs and outputs, as well as various communication interfaces, making it ideal for applications in automotive, aerospace, industrial automation, and renewable energy sectors. Its real-time processing capabilities ensure that control systems can be tested under realistic conditions, reducing development time and enhancing the reliability and performance of the final product. By leveraging the dSPACE RTI1104, developers can quickly iterate on designs and validate them in a controlled, real-time environment, facilitating a smoother transition from simulation to physical implementation. Figure 10 displays the experimental results with the output voltage V_O = 400 V, and Figure 11 displays the experimental results with the voltage V_O = 400 V and current I_O = 4 A for a resistive load of 100 Ω. According to IEEE standards, the experimentally measured THD, which is 3.32%, is displayed in Figure 12, and it is comparable to the modeling THD.

5.2. Simulation and Test of the Proposed 25-Level MLI

The proposed 25-level MLI simulation results are shown in Figure 13. Figure 14 represents the output voltage, V_O = 400 V, and current, I_O = 4 A. The THD obtained from the FFT analysis is 3.20% and is displayed in Figure 15. A 25-level inverter prototype is used in the laboratory to evaluate and confirm the simulation results experimentally. The system has four input DC sources (V₁, V₂, V₃, and V₄), eleven 600 V, 75 A IGBTs (CM75DU-12), and a 100 Ω load resistor.

The dSPACE RTI1104 processor’s controller board generates pulses to control IGBTs by utilizing switching angles. Experimental outcomes are illustrated in Figure 16, where the output voltage is set at V_O = 400 V. Additionally, Figure 17 shows experimental results with V_O = 400 V and I_O = 4 A current for a 100 Ω resistor as a load. Figure 18 exhibits the output voltage and current waveforms using a motor as an R-L load and featuring an inductance of L = 98 mH and an output current of 6.8 A. To assess the effectiveness of the proposed MLI, dynamic load transitions were examined for the R-L load configuration, as depicted in Figure 19. Furthermore, Figure 20 illustrates the behavior of the L-R load configuration under load disturbance conditions. As indicated by Figure 21, the experimentally determined THD of 3.20% closely aligns with the modeled THD value.

Finally, Figure 22 depicts the practical setup of the proposed multilevel inverter controlled by a dSPACE DS1104 controller. The multilevel inverter circuit is prominently visible in the central workspace, consisting of numerous power electronics components connected by a network of colored wires, which indicate the complex interconnections necessary for the inverter’s operation. The dSPACE DS1104 controller, placed on the right, is a real-time interface commonly used for control and automation tasks in power electronics and motor control applications. The oscilloscope and other measurement instruments are likely integrated into the setup to monitor the inverter’s output waveform and ensure it meets the desired specifications. A computer running software for programming the dSPACE controller and analyzing data is part of the setup. The presence of a resistive active load and a motor suggests the system was tested under various load conditions to evaluate its performance and efficiency in practical applications.

5.3. Power Losses and Efficiency Estimation in the Proposed MLIs

The calculation of power loss and efficiency was conducted for both 15-level and 25-level proposed MLIs, considering R and R-L load. The conduction losses are calculated by applying Equations (12) and (13). As an example, and in the case of the proposed 15-level MLI operating with R load, the obtained result is shown in Equation (18), where the values of R_S = 400 mΩ and V_S = 0.6 V are obtained from the IGBTs datasheet, and β = 1 is assumed for switches based on IGBT devices.

$$P_{CL}=\left[V_S+R_S·I\right]·I·N_{SW}=\left[0.6+0.4·2.82\right]·2.82·11=53.60 \mathrm{W}$$

(18)

The switching losses of one switch q are calculated by applying Equation (14), where the turn-on (E_ONq) and turn-off (E_OFFq) energy losses are calculated by Equations (19) and (20), respectively [49].

$$E_{ONq}={\displaystyle \frac{1}{6}}·V_{SWq}·I·t_{on}$$

(19)

$$E_{OFFq}={\displaystyle \frac{1}{6}}·V_{SWq}·I^{\prime }·t_{off}$$

(20)

where time to turn ON and OFF of the switch q are t_on and t_off, respectively, I and I’ are the switch current before turning ON and after turning OFF, and V_SWq is the OFF state switch voltage.

The results obtained are presented in

Table 9. Power loss and efficiency calculation for the proposed MLI.

Parameter	15-Level		25-Level
	R Load	R-L Load	R Load	R-L Load
VRMS	282.82 V	282.82 V	282.82 V	282.82 V
IRMS	2.82 A	4.80 A	2.82 A	4.80 A
POUT	797.55 W	1357.54 W	797.55 W	1357.54 W
PCL	53.60 W	133.06 W	53.60 W	133.06 W
PSL	0.22 W	0.37 W	0.37 W	0.62 W
PTL	53.82 W	133.43 W	53.97 W	133.68 W
PIN	851.37 W	1490.97 W	851.52 W	1491.22 W
η	93.68%	91.05%	93.66%	91.03%

.

Table 10. Efficiency of 15-level and 25-level MLI designs.

15-Level		25-Level
Reference	η	Reference	η
[43]	90.0%	[30]	---
[44]	93.7%	[31]	93.8%
[45]	* 90.0%	[32]	* 96.5%
[46]	---	[33]	---
Proposed	* 93.7%	[34]	* 92.5%
		[35]	* 92.5%
		[36]	95.0%
		Proposed	* 93.7%

Note that the value ‘---’ indicates that the specified reference does not offer any value for this parameter, and the mark ‘*’ indicates that the efficiency values have been obtained theoretically using mathematical models.

presents a comparison of the efficiency of the two MLIs presented in this work with those previously introduced in Section 4.1 and Section 4.2 of this document.

Furthermore, the efficiency values shown in Table 8 were obtained under different operating conditions of the referenced MLIs, which complicates the comparison of values between them. However, the values shown indicate that the efficiency of the MLIs presented in this paper equals or improves the efficiency of some of the converters presented in the literature and used in this comparison.

6. Conclusions

A novel asymmetrical 15-level MLI (multilevel inverter) topology, along with a 25-level topology, is proposed utilizing fewer semiconductor switches. This design aims to reduce the inverter’s cost and size while improving its reliability and, in some cases, efficiency (when compared to the theoretical values offered by other topologies proposed in the references used). The presented MLIs demonstrate low total harmonic distortion (THD) and can generate the required output voltage levels with minimal wastage.

Through evaluating configurations with varying quantities of MLI, the total standing voltage (TSV) and cost function were computed. The results indicate that the recommended MLI’s lower TSV value enhances its competitiveness, speed, and cost-effectiveness. Experimental comparisons showed that the structure is highly suitable for grid-connected applications and dynamic voltage restorer (DVR) technologies, generating electricity with low harmonic content within IEEE standards.

The MLIs also performed well with renewable energy sources. Additionally, the availability of multiple isolated DC sources makes them useful for single-phase applications. This work is particularly promising for battery storage in standalone and alternative facilities, such as residential and hotel sectors. Future research will focus on the implementation of the proposed MLIs in practical applications to verify these findings, including the implementation of a DC/DC converter, which could be based on the basic isolated SEPIC topology.

Some parts of this article have been extracted from research carried out by the first author of this article during the completion of his doctoral thesis [52]. The doctoral thesis was presented at the Polytechnic University of Catalonia in July 2024, and a part of the presented research work is related to asymmetric multilevel converters.