Improving Temporal Characteristics of Mealy FSM with Composite State Codes

Round 1

Reviewer 1 Report

Comments and Suggestions for Authors

The reviewed article focuses on improving the timing characteristics of Mealy finite state machines (FSMs) using the composite state code (CSC) method of encoding states. The research focuses on the implementation of FSMs on FPGAs, in particular on reducing the cycle time of FSMs by reducing the number of cascaded LUTs (Look-Up Tables). The paper presents both the theoretical basis of the approach and experimental results for standard FSM benchmarks. There are many methods in the scientific literature for optimizing FSMs for performance, including:
- One-hot and maximal binary coding (MBC) - used in many commercial FSM synthesis tools (e.g., Vivado).
- JEDI algorithm - which optimizes state assignment to reduce the number of logic elements.
- State coding with composite codes (CSC) - as the paper shows, this method allows a better compromise between FPGA resource consumption and signal propagation time.

A novelty proposed in the paper is the use of one-hot coding for classes of states and binary maximal codes for states within classes, which is expected to lead to a reduction in FSM cycle time.

Weaknesses of the article:
- Lack of analysis of the impact on power consumption - optimization of FSMs in FPGAs often involves not only performance, but also minimization of power consumption.
- Vagueness in comparison with other methods - although the authors compare their method with other approaches (MBC, JEDI, one-hot), a deeper analysis of their advantages and disadvantages in specific industrial applications is missing.
- Lack of comparisons for newer FPGA technologies - the article is based on the Virtex-7 architecture, but does not address more modern FPGAs, such as the UltraScale+ family.

Summary:
The paper makes an important contribution to the field of FSM synthesis on FPGAs, presenting a method that improves FSM timing characteristics with a relatively small increase in the number of LUTs used. However, some aspects, such as energy efficiency analysis and tests on newer FPGAs, could enrich the work and make it more convincing.

Author Response

Dear Respected Reviewer!

Thank you very much for your valuable time spent on thorough analysis of our article. We think your comments help us to improve the quality of our paper. All changes in the pdf document are highlighted. Furthermore, in the attachment you will find our response to your comments.

Thank you very much once more.

Yours sincerely,

Authors

 

Author Response File: Author Response.pdf

Reviewer 2 Report

Comments and Suggestions for Authors

The article proposes a new state assignment method focused on Mealy's finite state machines (FSM). The method makes it possible to improve the temporal characteristics of FSM circuits whose internal states are encoded by composite state codes (CSCs). However, the paper has some critical issues that need to be resolved.

1) The motivation of the paper needs to be articulated more clearly, better explaining the context and the gap to existing approaches.

2) The comparison with existing methods focuses mainly on LUT-based FSM. The authors should include other FSM optimization techniques to get a more complete picture. I am not asking the authors to implement a new model, but only to include a paragraph dealing with induced current models for defect detection in composite materials. The correlation with FSMs represents an extra quid in the context of industrial quality control, where optimized FSMs can accelerate real-time analysis; list the following paper in the bibliography: doi:10.3390/math12182854.

3) The proposed methodology was tested on benchmarks with relatively small FSMs. The authors should evaluate the impact on FSMs with a much larger number of states and transitions.

4) The method introduces an average 10% increase in the number of LUTs compared to the CSC approach. The authors should explore strategies to reduce this overhead.

5) The authors should discuss in which specific areas the improvement of FSM speed leads to concrete benefits.

6) The paper uses standard benchmarks, but it would be useful to validate the method on real digital circuit design cases.

7) The paper does not analyze the impact on power and energy consumption, which are critical aspects in FPGA devices.

8) The figures need to be improved to make the structure of the proposed method clearer, e.g., by better highlighting the logic levels and connections between LUTs.

Author Response

Dear Respected Reviewer!

Thank you very much for your valuable time spent on thorough analysis of our article. We think your comments help us to improve the quality of our paper. All changes in the pdf document are highlighted. Furthermore, in the attachment you will find our response to your comments.

Thank you very much once more.

Yours sincerely,

Authors

 

Author Response File: Author Response.pdf

Round 2

Reviewer 1 Report

Comments and Suggestions for Authors

Thank you for including the comments in the revised version of the article.

Reviewer 2 Report

Comments and Suggestions for Authors

I thank the authors for their replies to the comments. I have no further comments to ask.