Efficient Large-Width Montgomery Modular Multiplier Design Based on Toom–Cook-5

Round 1

Reviewer 1 Report

Comments and Suggestions for Authors

Overall, the paper is well-structured and includes all the necessary sections: introduction, review of previous research, description of methods, hardware implementation, and experimental results. The work makes a significant contribution to the field of hardware acceleration for cryptographic computations.

Comments and Areas for Improvement

1. Lack of Information on Power Consumption

The Implementation Results and Comparison section only considers area (Area), delay (Time), and their product (ATP) as evaluation metrics.

1. Security Analysis

In cryptographic applications, resistance to side-channel attacks is crucial. The paper does not address how the proposed method impacts resistance to such attacks.

1. Comparison with Alternative Approaches

Although the paper provides a comparison with other Toom-Cook implementations, there is no analysis of its efficiency relative to FFT-based multiplication, which is often used for higher bit-width operations.

Author Response

Please see the attachment

Author Response File: Author Response.pdf

Reviewer 2 Report

Comments and Suggestions for Authors

1. It is suggested if authors can briefly mention about the system's impact on cryptographic primitives such as RSA and ECC in real-world workloads.

2. Toom-Cook-5's usage has been explained (based on reduced bit-width in multiplication steps), but could the authors compare or provide trade-offs against Toom-Cook-4 or FFT-based approaches? Maybe a complexity analysis with other advanced multipliers would make sense in this study?

3. I feel there is a need for more discussion on the impact of area overhead, as the study did not explore or mention how the design scales with increased band-width like with 4096-bit RSA operation?

4. What is the impact of proposed optimizations on resistance to side channel attacks (ex. differential power analysis, and fault injection).

5. Can authors include the mention of power consumption or related discussions? As per the study, the design reduces computational power consumption and overhead, but a discussion or analysis would make sense, briefly. Because in the practical setting for cryptographic applications power efficiency is important to be kept in focus.

6. Its suggested that the authors discuss the side-channel vulnerabilities and countermeasures in the proposed hardware architecture.

7. Also, possible discussion can be added for the feasibility of extending this architecture to 4096-bit modular multiplication.

Author Response

Please see the attachment.

Author Response File: Author Response.pdf

Round 2

Reviewer 2 Report

Comments and Suggestions for Authors

I believe that the content added to the manuscript seems adequate on technical standpoint, essentially covering its bases. I have no objections and can support the manuscript.