Reduced Loss Tristate Converters

Abstract

In a tristate converter the basic circuit topology is extended by an additional electronic switch and an additional diode. Three modes follow each other within one switching period. During the first mode M1, both electronic switches are on and both diodes are off. In the second mode M2, only the second switch is on and the first diode is conducting, and in mode M3, only the second diode is conducting. The voltage transformation ratio is a function of the two duty cycles of the electronic switches. In a typical tristate converter, the current flows through the second switch during the first two modes. In the converters treated here, the current is flowing through the second switch only during the second mode, so the losses are reduced compared to the normal tristate converter. This is shown for the Buck, the Buck–Boost, the Boost, the Zeta, the Cuk, the Super Boost, the quadratic Buck, and a reduced-duty cycle converter. The voltage transformation ratios are depicted in diagrams. As an example the reduced loss tristate Buck is used to demonstrate the derivation of the large and the small signal models. The transfer functions are also calculated and Bode plots are shown for an operating point. The voltage and the current stress of the converters are analyzed and the results are summarized in tables. The considerations are proved by simulations with the help of LTSpice.

1. Introduction

DC/DC converters are used to transfer a DC input voltage into a DC output voltage. Nearly all electric and electronic systems need these converters. The basic topologies are described in the textbooks of Power Electronics, e.g., [1,2,3]. But many other topologies can be found in the literature. A basic text about the construction of DC/DC converter topologies is found in [4]. A vast amount of step-up converter topologies can be found in [5]. More than a hundred step-up, step-down, and step-up-down topologies can be seen in [6]. Converters may have more than two pairs of connectors. A valid concept study of three terminal converters is given in [7]. Converters with reduced duty cycles are given in [8]. Here now, tristate converters are investigated. A basic text is [9] where this tristate method is explained with a Boost converter. The electronic switch of a converter is replaced by a series connection of two electronic switches and an additional diode, connected to the connection point of the two active switches. This method is applied to several other converter topologies: the Buck, the Buck–Boost, the Zeta, the Cuk, the SEPIC, the d-square Buck, two types of the (2d − 1)/(1 − d), and the improved superlift converter in [10]. Another extension of the tristate concept can be found in [11], where it is applied to coupled coil converters. In this case, three possibilities exist to influence the voltage transformation ratio: the duty cycles of the two active switches and the winding ratio. The papers [12,13] show a topology change in the tristate Boost converter. The forward losses are reduced, due to this change of the position of the second switch. A combination of two tristate Buck–Boost converters is shown in [14]. The two converters are driven by control signals which are shifted by 180°, the so-called interleaved concept. The inductor of a half-bridge Boost converter is shunted by a diode and a transistor in [15]. In this case, it is used to achieve ZVS (zero voltage switching). The converters with a quadratic term in the voltage transformation ratio are also interesting candidates for using the tristate conception. The basic text for these converters is found in [16]. The transfer function of converters with step-up behavior has a non-phase-minimum behavior. The design of the controller therefore leads to a slower control, caused by the additional shift of minus ninety degrees, due to the zero (or n-time 90° for n positive zeros) in the right-hand side of the complex plane. A control study for the Boost converter can be found in [17,18,19]. The control of the Buck–Boost converter is treated in [20]. A dual output tristate converter is analyzed in [21].

The basic function of a reduced loss tristate (RLT) converter is now shown with the help of the Buck converter. The circuit diagram of the Buck converter is shown in Figure 1.

The converter consists of an electronic (active) switch S1, a diode (passive switch) D2, an inductor (coil) L1, and a capacitor C1. Parallel to the capacitor, there are the output terminals to which the load R is connected. The input voltage U1 is connected to the input terminals.

To transform the converter into a tristate converter, the electronic switch S1 is replaced by two electronic switches S1 and S2, and a diode D1, which is connected to the connection point between the two active switches. The circuit diagram is depicted in Figure 2.

The operation of this converter can be described by three modes which follow each other during one switching period. During mode M1, both active switches S1 and S2 are on. The input current which is equal to the current through the inductor is flowing through them. Both diodes are off. When the first active switch is turned off, mode M2 begins. The diode D1 turns on, and the current through the coil commutates into the diode D1. It is easy to see that the inductor is now nearly short-circuited (only the onward losses across S2 and D1 produce a small negative voltage), and the current through it therefore stays nearly constant. When the second switch S2 is turned off, too, mode M3 starts. Now the current through the coil has to commutate into the diode D2.

It is evident that in modes M1 and M2, the current is flowing through the active switches and produces forward losses. When the position of S2 is changed as shown in Figure 3, the losses are reduced because only in mode M2 current is now flowing through S2, and the overall forward losses are reduced.

This concept is now applied to several typical DC/DC converters and is described in the next section. Remark: the electronic switches are drawn as MOSFETs, so they have a body diode antiparallel to the electronic switch but it is not necessary to be current bidirectional.

2. Application of the Reduced Loss Tristate Concept

We start with the three basic single-coil converters. These converters consist of an electronic switch S1, a diode D2, an inductor L1, and a capacitor C1. The input voltage U1 is connected to the input terminals, the load is connected to the output terminals which are parallel to the capacitor. In the later part of this section the Zeta, the Cuk, the Super Boost, the quadratic Buck, and the d₁/(1 − d₁ − d₂) converter are used as examples. The Sepic converter is treated in [22]. During mode M1, both switches are turned on at the same time, and after the time interval d1·T, S1 is turned off, and after the time interval d2·T, the second switch turns off. Mode M1 takes d1·T and mode M2 takes (d₂ − d₁)·T. Mode M3 takes (1 − d₂)·T. It should be mentioned that S2 can be turned on later within mode M1, but d2 is defined as the time interval between the turning on of S1 and the turning off of S2. The usual definition of the duty cycle is the on-time of the switch referring to the switching period and is used in the paper. However, it is not necessary to turn the two switches on at the same time. When we turn on the two switches at the same time and turn off S1 after the time d1T and the second switch S2 after d₂T, we obtain the voltage transformation ratio according to (2). During the on-time of S1, no current is flowing through S2, although the switch is turned on. The diode D1 blocks the current. When S1 is turned off, the current commutates into S2. As one can see, it is not necessary to turn on switch S2 at the same time as switch S1. The turn-on can be delayed until near the end of the on-time of switch S1. The voltage transformation ratio is still the same, although the on-time of switch S2 is shorter. For the time d₂T, we use the interval between the moment when S2 is turned off and the moment when S1 is turned on, when calculating the voltage–time balance in (1).

2.1. Reduced Loss Tristate Buck Converter

The circuit diagram of the RLT Buck is shown in Figure 3.

During mode M1 (both switches are on), the difference between the input and the output voltages is across the coil and the current through the coil increases. When the first switch S1 is turned off and the second switch S2 is still on, the current through the coil commutates into the first diode D1 and the current through the coil stays nearly constant. When the electronic switch S2 is turned off, mode M3 begins and the diode D2 turns on. The voltage across the coil is now the negative output voltage U2. If S1 and S2 are switched on contemporarily and their duty cycles are d₁ and d₂, respectively, the voltage–time balance can be expressed as

$$\left(U_1-U_2\right)d_1=\left|-U_2\right|\left(1-d_2\right),$$

(1)

leading to the voltage transformation ratio

$$M={\displaystyle \frac{U_2}{U_1}}={\displaystyle \frac{d_1}{1+d_1-d_2}}.$$

(2)

The voltage transformation ratio now has two possibilities to be influenced. Figure 4 shows the voltage transformation ratios for the constant duty cycle d₂ of the second switch and the duty cycle d₁ of the first switch as the variable. The straight line is the voltage transformation ratio of the classical Buck converter. Using this control method, the output voltage increases more for low-duty cycles and changes less for higher-duty cycles of the first electronic switch.

The straight line in Figure 4 represents the voltage transformation ratio of the normal Buck. The curves are the voltage transformation ratios of the tristate converter. If the duty cycle d₂ is smaller than d₁, the converter works like the normal Buck converter, and the voltage transformation ratio in dependence on d1 is linear. But when d₁ is smaller than d₂, the voltage transformation ratio is curved. When the curve reaches the linear line, the voltage transformation follows the line. At the point where the curve meets the straight line, the parameter for d₂ is written. So, it is easy to find the correct line.

One can also control the circuit by keeping the duty cycle d₁ constant and using the duty cycle d₂ of the second switch as the variable. This is shown in Figure 5. The straight line is the normal Buck. For low-duty cycles of d₂, the voltage transformation rate is hardly changing, but for higher-duty cycles, the derivative of the voltage transformation ratio is larger than the one of the classical Buck.

In Figure 5, the voltage transformation ratio follows first the straight line and when the duty cycle of S2 is higher than the one of S1, the curve diverges. The parameter is always written at this point.

It should be mentioned that it is not necessary to turn on the second switch synchronously with the first switch. During M1, the switch S2 is on but no current is flowing through it. Therefore, one can turn it on later, but during the on-time of switch S1. To achieve the voltage transformation ratio according to (2), the second switch must be turned on before the first switch is turned off. In this case, variable d₂ in (1) and (2) is not the duty cycle of S2, but is related to the time interval between the turn-on of switch S1 and the turn-off of switch S2. Note that in this RLT converter, during M1 the switch S2 is on, but no current is flowing through it. This is opposite to the traditional tristate converter, where during mode M1 the inductor current flows through both the active switches S1 and S2.

When S1 is turned off at the end of M1 and the second switch is not on, the current commutates directly into the diode D2. In this case, the converter works as the original converter without the bypass branch (D1 in series to S2) in parallel to the coil. When the on-time of switch S1 is longer than the on-time of switch S2, the converter also works as a traditional converter and has the same voltage transformation ratio as the original one. When S1 and S2 are switched on and S2 turns off before S1 is turned off again, there is no tristate mode, and the converter works again as the original converter.

The control of the converters can also be conducted in a second way (a sketch of the timing can be found in Appendix B, Figure A1b): S1 is turned on with the duty cycle d1, and S2 is turned on with the duty cycle d2_2 (on-time of the switch referred to the switching period), but S2 is turned on only within the time (1 − d₁)T, when the first switch is off. The voltage–time balance is therefore

$$\left(U_1-U_2\right)d_1=\left|-U_2\right|\left(1-d_1-d_{2\_2}\right),$$

(3)

so the voltage transformation ratio differs in this case compared to the first control concept, when the current commutes after the turn-off of switch S1 into the bypass branch S2 D1. In this second control method, the current commutates into D2 when S1 is turned off, when S2 turns on within the off-time of S1, the current commutates from D2 into S2, and when the switch S2 turns off, the current commutates into the diode D2 again. So two commutations occur between the modes M3 and M2 which produce switching losses. The voltage transformation ratio is given in this case by

$$M={\displaystyle \frac{U_2}{U_1}}={\displaystyle \frac{d_1}{1-d_{2\_2}}}.$$

(4)

The duty cycle d_{2_2} must be smaller than (1 − d₁). In this paper, only the first concept is treated because one switching transient is avoided and its switching loss omitted. (Note: a sketch of the timing of method 1 can be found in Appendix B, Figure A1a). In the second control concept, we have the following commutations: from S1 to D2, from D2 to S2, from S2 to D2, and back from D2 to S1, so we have four switching events per period. In the first control concept, we have the following commutations: from S1 to S2, from S2 to D2, and back from D2 to S1, so we have only three switching events per period. The first control concept has therefore lower switching losses. It should be mentioned, that the second control concept leads to a linear voltage transformation ratio, when d_{2_2} is held constant, again leading to a phase-minimum system. More details can be found in [10].

Figure 6 shows the current through the capacitor, the current through the coil, the load current, the input voltage, the control signal of the second switch, the output voltage, and the control signal of S1. The spike of the current through the capacitor is caused by charging the parasitic capacitors of the diodes, when the switches turn on again the voltage must change across the diodes.

2.2. Reduced Loss Tristate Buck–Boost Converter

The circuit diagram of the RLT Buck–Boost converter is shown in Figure 7. During mode M1, the input voltage is across the coil, during mode M2, nearly zero voltage, and during M3, the negative output voltage is across the inductor.

The voltage–time balance is therefore

$$U_1{d}_1=U_2\left(1-d_2\right),$$

(5)

leading to the voltage transformation ratio

$$M={\displaystyle \frac{U_2}{U_1}}={\displaystyle \frac{d_1}{1-d_2}}.$$

(6)

From (6), one can see that for a constant duty cycle d₂ of S2, the voltage transformation ratio is a linear function of the duty cycle d₁ of the switch S1, as depicted in Figure 8.

Figure 9 shows the voltage transformation ratio for a fixed duty cycle of S1 and a variable duty cycle of S2. When the duty cycle d₂ is smaller than d₁, the converter works as a normal Buck–Boost. When the duty cycle d₂ is higher than d₁, the converter works in the actual tristate mode. The derivative of the voltage transformation is lower and the voltage transformation ratio is still nonlinear.

Figure 10 again shows the current through the output capacitor, the current through the coil, the current through the load, the input voltage, the control signal of the second switch S2, the control signal of the first switch S1, and the output voltage. The spike occurs when the voltages across the semiconductors change when S1 turns off.

2.3. Reduced Loss Tristate Boost Converter

The circuit diagram of the RLT Boost converter is given in Figure 11.

During mode M1, the input voltage is across L1, during M2, the coil is short-circuited, and during M3, the difference between the input and the output voltages is across the coil. For the voltage–time balance one can write

$$U_1{d}_1=\left|U_1-U_2\right|\left(1-d_2\right).$$

(7)

This leads to the voltage transformation ratio according to

$$M={\displaystyle \frac{U_2}{U_1}}={\displaystyle \frac{1+d_1-d_2}{1-d_2}} \mathrm{with} d_2\ge d_1.$$

(8)

If the duty cycle d₂ is smaller than d₁, the converter works as a normal Boost converter. One can easily see that the voltage transformation ratio is a linear function of d₁ when the duty cycle d₂ is kept constant (Figure 12).

Figure 13 shows the voltage transformation ratio with a fixed duty cycle of the first switch S1 and a variable duty cycle of the second switch S2. As long as the duty cycle d₂ is smaller than the duty cycle d₁, the converter works as a normal Boost converter. When d₂ is greater than d₁, the converter operates in the tristate mode and the derivative of the voltage transformation ratio is reduced.

Figure 14 shows a simulation with the current through the capacitor, the current through the coil, the load current, the input voltage, the control signal of the second switch, the output voltage, and the control signal of S1. The spike occurs when the voltages across the semiconductors change when S1 turns off.

2.4. Reduced Loss Tristate Zeta Converter

The Zeta converter is a step-up-down converter. When the circuit is applied to a stable input voltage, no inrush occurs. With the switch S1, the capacitor C1 can be charged with limited input current. In the case of an error, the switch S1 can also be used as an electronic fuse. The circuit diagram of the RLT-Zeta is shown in Figure 15.

During M1, the input voltage U1 is across the first inductor L1, during M2, the inductor is short-circuited, and during M3, the voltage across C1 is with negative polarity across L1. The voltage–time balance is therefore

$$U_1{d}_1=\left|-U_{C1}\right|\left(1-d_2\right).$$

(9)

It can immediately be seen (the voltages across the inductors are zero in the mean) that in the steady state, the voltage across C1 is equal to the output voltage U2:

$$U_2=U_{C2}=U_{C1}.$$

(10)

The voltage transformation ratio is equal to the one of the RLT Buck–Boost converter

$$M={\displaystyle \frac{U_2}{U_1}}={\displaystyle \frac{d_1}{1-d_2}} \mathrm{with} d_2\ge d_1.$$

(11)

The diagrams of the voltage transformation ratio in dependence on one duty cycle with the other duty cycle as a variable are shown in Figure 8 and Figure 9.

The voltage across the second coil has the same form as the voltage of the first coil. One could combine both windings on the same magnetic core (integrated magnetics).

When the duty cycle d₂ is smaller than d₁, the converter works like a normal Zeta converter with the voltage transformation ratio:

$$M={\displaystyle \frac{U_2}{U_1}}={\displaystyle \frac{d_1}{1-d_1}}.$$

(12)

A simulation of the steady state is shown in Figure 16. The signals are the current through the intermediate capacitor C1, the current through the second coil L2, the load current, the current through the first coil L1, the input voltage, the output voltage, the control signal of the second switch S2, and the control signal of S1.

A second possibility to obtain an RLT Zeta converter is by placing the diode D1 and the switch S2 in parallel to the output coil L2. This leads to the same voltage transformation ratio, but the circuit has now no continuous output current. Instead of L2, C2 and the load R, the armature winding of a DC machine, can be connected to obtain a motor driver.

2.5. Reduced Loss Tristate Cuk Converter

The Cuk converter has continuous input and output currents and operates as an inverting step-up-step-down converter. Figure 17 shows the circuit diagram of the RLT Cuk converter. Figure 18 shows the same signals as Figure 16.

During mode M1, the input voltage U1 is across L1, L1 is short-circuited during M2, and during M3, the difference between the input voltage U1 and the voltage across C1 UC1 is across the coil L1, leading to the voltage–time balance

$$U_1{d}_1=\left|U_1-U_{C1}\right|\left(1-d_2\right).$$

(13)

Inspecting the circuit, one can easily see that in the steady state, the voltage across C1 UC1 must be equal to the input voltage U1 plus the output voltage U2:

$$U_{C1}=U_1+U_2,$$

(14)

leading to

$$M={\displaystyle \frac{U_2}{U_1}}={\displaystyle \frac{d_1}{1-d_2}}, \mathrm{with} d_2\ge d_1.$$

(15)

The diagrams for the voltage transformation ratio in dependence on one duty cycle with the other duty cycle as a variable are equal to the results in Figure 8 and Figure 9.

Figure 18 shows a simulation with the current through the intermediate capacitor C1, the current through the second coil L2, the load current, the current through the first coil L1, the input voltage, the control signal of the second switch S2, the control signal of the first switch S1, and the output voltage. During M2, the input current is zero and no more continuous.

By connecting S2 and D1 in parallel to the second inductor, a second variant of the RLT-Cuk (Figure 19) is obtained. In this case, the output current is not continuous, but pulsating.

A disadvantage of the Cuk converter is the large inrush current, when the converter is connected to a stable input source such as car batteries. Figure 20 shows a simulation with constant inductors. In reality, the coils saturate and the current will be even higher. When the circuit is connected to the stable input voltage, both electronic switches are blocked. During the first half period, diode D2 is on and the current through the coil L1, which is equal to the current into the circuit, is larger. When D2 turns off, a damped ringing occurs between the inductors and the capacitors, which form a series resonance circuit.

2.6. Reduced Loss Tristate Super Boost Converter

The RLT Super Boost converter (Figure 21) has a continuous output current. During M1, the input voltage is across the first inductor L1, during M2, the coil is short-circuited, and during M3, the difference between the input voltage and the voltage across C1 is across the coil L1. The voltage–time balance is given by

$$U_1{d}_1=\left|U_1-U_{C1}\right|\left(1-d_2\right).$$

(16)

When inspecting the loops L2, C2, L1, and C1, it is obvious that the voltage across C1 must be equal to the output voltage. This leads to

$$M={\displaystyle \frac{U_2}{U_1}}={\displaystyle \frac{1+d_1-d_2}{1-d_2}}, d_2\ge d_1,$$

(17)

the same result as that of the RLT Boost converter. The diagrams in Figure 12 and Figure 13 are also valid for the so-called Super Boost converter.

An interesting aspect of the converter is that during the modes M1 and M3, the input current is the sum of the currents through both inductors.

Figure 22 shows a simulation with the current through the intermediate capacitor C1, the current through the second coil L2, the load current, the current through the first coil L1, the input voltage, the control signal sigma2 of the second switch, the control signal of the first switch sigma1, and the output voltage U2.

In steady state, Figure 23 shows the signal diagrams of the voltages across the diodes D1 and D2, the voltages across the electronic switches S1 and S2, the output voltage U2, the input voltage U1, and the control signals of the electronic switches.

When S1 and S2 are on, the diode D1 has to block the input voltage, during M2, the diode is conducting and the voltage across it is equal to the forward voltage. During M3, the voltage across D1 is nearly zero. The voltage across D2 is equal to the voltage across C1 which is equal to the output voltage. During M2, the voltage is the difference between the input voltage and the voltage across C1. During M3, when the diode is conducting, only a small forward voltage can be seen. The electronic switch S1 is on during M1, has to block the input voltage during M2, and has to block the voltage across C1 during M3. Transistor S2 is on during M1 and M2, therefore the voltage across it is zero and has to block the difference between the voltage across C1 and the input voltage during M3.

2.7. Reduced Loss Tristate D-Square Buck Converter

The quadratic Buck converter consists of a Buck stage built by the switch S1, the diode D3, the coil L2, the output capacitor C2, and a pre-stage built by the first inductor L1, two diodes D1 and D2, and the first capacitor C1. The basic text for converters with a quadratic term in the voltage transformation ratio is the paper [16]. When the switch S1 is turned on, the diode D1 is also on, and when the switch S1 is turned off, the diode D1 also turns off and diode D2 turns on. The branch for the tristate operation is built by the second switch S2 and the fourth diode D4. The circuit diagram is depicted in Figure 24.

For the tristate operation, the three modes follow each other again. During M1, the input voltage minus the voltage across C1 is across L1, and the difference between the voltage across C1 and the output voltage is across the second coil. When S1 turns off, mode M2 begins. When the current through L1 commutates into the series connection of S2 and D4, D1 turns off, D2 is still off, and D3 must turn on, and the current through L2 commutates into D3. When S2 is turned off, too, the current through L1 commutates into the branches C1 and D2. The capacitor C1 is now being charged. The voltage–time balance is therefore

$$\mathrm{L}1\text{:} \left(U_1-U_{C1}\right)d_1=\left|-U_{C1}\right|\left(1-d_2\right),$$

(18)

$$\mathrm{L}2\text{:} \left(U_{C1}-U_2\right)d_1=\left|-U_2\right|\left(1-d_1\right),$$

(19)

which leads to the voltage transformation ratio

$$M={\displaystyle \frac{U_2}{U_1}}={\displaystyle \frac{d_1^2}{1+d_1-d_2}}, d_2\ge d_1.$$

(20)

Figure 25 shows the voltage transformation ratio of the RLT d-square converter with the duty cycle of switch S2 as a parameter and the duty cycle of switch S1 as a variable. The black line shows the voltage transformation ratio of a quadratic Buck. For duty cycles of switch S2 lower than 0.5, nearly no difference exists referred to the simple quadratic converter. For duty cycle d₂, the voltage transformation ratio is higher than that of the simple quadratic converter.

Figure 26 shows the voltage transformation ratio of the RLT d-square converter with the duty cycle of switch S1 as a parameter and the duty cycle of switch S2 as a variable. The black line shows the voltage transformation ratio of a quadratic Buck. The lines are all under the line of the voltage transformation ratio of the quadratic Buck converter and their derivative is smaller.

Figure 27 shows the current through the intermediate capacitor C1, the current through the second coil L2, the load current, the current through the first coil L1, the input voltage, the control signal of the second switch S2, the output voltage, and the control signal of the first switch S1.

2.8. Reduced Loss Tristate D1/(1-D1-D2) Converter

This converter topology, shown in Figure 28, has an electronic switch in series to the input source. Therefore, no inrush current occurs when the converter is connected to a stiff input source. Another interesting feature is that the converter has a limited duty cycle range. An early study of this kind of converter can be found in [8]. The converter inverts a negative voltage into a positive one. The converter acts as a step-up-down converter.

During mode M1, the sum of the input voltage and the voltage across C1 is across L1. During M2, the L1 is short-circuited. During M3, the negative output voltage is across the first coil. It can be directly seen that the voltage across C1 must be equal to the output voltage in the mean. With

$$U_2=U_{C2}=U_{C1}$$

(21)

and with the voltage–time balance

$$\left(U_1+U_{C1}\right)d_1=\left|-U_2\right|\left(1-d_2\right),$$

(22)

one obtains the voltage transformation ratio

$$M={\displaystyle \frac{U_2}{U_1}}={\displaystyle \frac{d_1}{1-d_1-d_2}} \mathrm{with} d_1+d_2<1\mathrm{and} d_2\ge d_1.$$

(23)

For lower duty cycles d₂ than that of d₁, the converter does not work in the tristate modus. Without the additional branch D1, S2, the voltage–time balance across L1, can be calculated according to

$$\left(U_1+U_{C1}\right)d_1=\left|-U_2\right|\left(1-d_1\right)$$

(24)

and again with

$$U_{C1}=U_2,$$

(25)

one obtains the voltage transformation ratio according to

$$M={\displaystyle \frac{U_2}{U_1}}={\displaystyle \frac{d_1}{1-2d_1}}, d_1<0.5.$$

(26)

Figure 29 shows the voltage transformation ratio of the RLT D1/(1 − D1 − D2) converter with the duty cycle of the second switch as a parameter and the duty cycle of the first switch as a variable. The voltage transformation rate is flatter and higher than that of the D/(1 − 2D) converter.

Figure 30 shows the voltage transformation ratio of the RLT D1/(1 − D1 − D2) converter with the duty cycle of the first switch as a parameter and the duty cycle of the second switch as a variable. The voltage transformation rate is flatter than that of the original converter.

For the steady state, one obtains the exemplary simulation results shown in Figure 31. One sees the current through the second coil L2, the load current, the current through the first coil L1, the output voltage, the control signal of the second switch S2, the control signal of the first switch S1, and the input voltage.

For another duty cycle of S2, Figure 32 shows the input current into the converter, the current through the second coil L2, the load current, the current through the first coil L1, the output voltage, the control signal of the second switch, the control signal of the first switch, and the input voltage.

3. RLT Buck Transfer Functions and Bode Diagrams

In this section, the calculations of the idealized model and the transfer functions of the RLT Buck are shown. This is similar to the method used for the normal tristate converter shown for the Buck–Boost in [10]. In the continuous mode and with ideal components (no losses, infinite fast switching), the three modes can be described by the three matrix equations

$$\mathrm{M}1 {\displaystyle \frac{d}{dt}}\left(\begin{array}{c}{i}_L\\ u_C\end{array}\right)=\left[\begin{array}{cc}0& -{\displaystyle \frac{1}{L}}\\ {\displaystyle \frac{1}{C}}& -{\displaystyle \frac{1}{RC}}\end{array}\right]\left(\begin{array}{c}{i}_L\\ u_C\end{array}\right)+\left[\begin{array}{c}{\displaystyle \frac{1}{L}}\\ 0\end{array}\right]\left(u_1\right),$$

(27)

$$\mathrm{M}2 {\displaystyle \frac{d}{dt}}\left(\begin{array}{c}{i}_L\\ u_C\end{array}\right)=\left[\begin{array}{cc}0& 0\\ 0& -{\displaystyle \frac{1}{RC}}\end{array}\right]\left(\begin{array}{c}{i}_L\\ u_C\end{array}\right),$$

(28)

$$\mathrm{M}3 {\displaystyle \frac{d}{dt}}\left(\begin{array}{c}{i}_L\\ u_C\end{array}\right)=\left[\begin{array}{cc}0& -{\displaystyle \frac{1}{L}}\\ {\displaystyle \frac{1}{C}}& -{\displaystyle \frac{1}{RC}}\end{array}\right]\left(\begin{array}{c}{i}_L\\ u_C\end{array}\right).$$

(29)

When the time constants of the converter are large (e.g., a factor from about 10 to 100) compared to the time period of the switching frequency, the three equations can be combined by multiplying (27) by d₁, (28) by (d₂ − d₁), and (29) by (1 − d₂) and adding them. This leads to the large signal model

$${\displaystyle \frac{d}{dt}}\left(\begin{array}{c}{i}_L\\ u_C\end{array}\right)=\left[\begin{array}{cc}0& -{\displaystyle \frac{1+d_1-d_2}{L}}\\ {\displaystyle \frac{1+d_1-d_2}{C}}& -{\displaystyle \frac{1}{RC}}\end{array}\right]\left(\begin{array}{c}{i}_L\\ u_C\end{array}\right)+\left[\begin{array}{c}{\displaystyle \frac{d_1}{L}}\\ 0\end{array}\right]\left(u_1\right).$$

(30)

To linearize this equation around the operating point, the variables are replaced by the operating point value (written with a capital letter with the index 0) plus a disturbance variable around the operating point (written with a small letter with a roof on top). This leads to the linear, small signal model around the operating point according to

$${\displaystyle \frac{d}{dt}}\left(\begin{array}{c}{\stackrel{\wedge }{i}}_L\\ {\stackrel{\wedge }{u}}_C\end{array}\right)=\left[\begin{array}{cc}0& -{\displaystyle \frac{1+D_{10}-D_{20}}{L}}\\ {\displaystyle \frac{1+D_{10}-D_{20}}{C}}& -{\displaystyle \frac{1}{RC}}\end{array}\right]\left(\begin{array}{c}{\stackrel{\wedge }{i}}_L\\ {\stackrel{\wedge }{u}}_C\end{array}\right)+\left[\begin{array}{ccc}{\displaystyle \frac{D_{10}}{L}}& {\displaystyle \frac{U_{10}-U_{C0}}{L}}& {\displaystyle \frac{U_{C0}}{L}}\\ 0& {\displaystyle \frac{I_{L0}}{C}}& -{\displaystyle \frac{I_{L0}}{C}}\end{array}\right]\left(\begin{array}{c}{\stackrel{\wedge }{u}}_1\\ {\stackrel{\wedge }{d}}_1\\ {\stackrel{\wedge }{d}}_2\end{array}\right).$$

(31)

This model has three input variables: the disturbances of the input voltage and of the duty cycles around the operating point. Using the Laplace transformation

$$\left[\begin{array}{cc}s& {\displaystyle \frac{1+D_{10}-D_{20}}{L}}\\ -{\displaystyle \frac{1+D_{10}-D_{20}}{C}}& s+{\displaystyle \frac{1}{RC}}\end{array}\right]\left(\begin{array}{c}{I}_L(s)\\ U_C(s)\end{array}\right)=\left[\begin{array}{ccc}{\displaystyle \frac{D_{10}}{L}}& {\displaystyle \frac{U_{10}-U_{C0}}{L}}& {\displaystyle \frac{U_{C0}}{L}}\\ 0& {\displaystyle \frac{I_{L0}}{C}}& -{\displaystyle \frac{I_{L0}}{C}}\end{array}\right]\left(\begin{array}{c}{U}_1(s)\\ D_1(s)\\ D_2(s)\end{array}\right),$$

(32)

one can now calculate six transfer functions. The most important ones are the output voltage (which in the ideal case is equal to the voltage across the capacitor), referred to as the duty cycles and to the input voltage. With the help of Crammer’s law one obtains

$${\displaystyle \frac{U_2(s)}{D_1(s)}}={\displaystyle \frac{s\frac{I_{L0}}{C}+\frac{\left(U_{10}-U_{20}\right)\left(1+D_{10}-D_{20}\right)}{CL}}{s^2+s\frac{1}{CR}+\frac{{\left(1+D_{10}-D_{20}\right)}^2}{CL}}},$$

(33)

$${\displaystyle \frac{U_2(s)}{D_2(s)}}={\displaystyle \frac{-s\frac{I_{L0}}{C}+\frac{U_{20}\left(1+D_{10}-D_{20}\right)}{CL}}{s^2+s\frac{1}{CR}+\frac{{\left(1+D_{10}-D_{20}\right)}^2}{CL}}},$$

(34)

$${\displaystyle \frac{U_2(s)}{U_1(s)}}={\displaystyle \frac{\frac{D_{10}\left(1+D_{10}-D_{20}\right)}{CL}}{s^2+s\frac{1}{CR}+\frac{{\left(1+D_{10}-D_{20}\right)}^2}{CL}}}.$$

(35)

The transfer functions of the influence of the duty cycles have a zero

$$s_{ZD1}={\displaystyle \frac{\left(U_{10}-U_{20}\right)\left(1+D_{10}-D_{20}\right)}{I_{L0}L}}, s_{ZD2}=+{\displaystyle \frac{U_{20}\left(1+D_{10}-D_{20}\right)}{I_{L0}L}}.$$

(36)

The zero is on the left side of the complex plane for d₁ as variable and on the right side of the complex plane for d₂ as variable. This means that the second one (34) is a non-phase-minimum system and therefore has an additional phase shift of minus 90° for high frequencies. The original Buck, however, is a phase-minimum system.

Figure 33 shows the Bode plot of the output voltage in dependence on the duty cycle D1. The resonance is caused by the inductor and the capacitor, which leads to a sharp change in the phase. The position of the pole has an imaginary part of about 830 Hz. The parameters used for the Bode plots are the same ones used for the simulation (Figure 6) (D01 = 0.3, D02 = 0.6, U10 = 24 V, C = 380 µF, L = 47 µH, R = 4 Ω). The break caused by the zero is at 9 kHz (at the phase shift of −135°).

Figure 34 shows the Bode plot of the transfer function (34). The zero is now on the right side and shifts the phase in the direction of −270 degrees.

For the influence of the input voltage U1 on the output voltage U2, one obtains the Bode plot Figure 35. The transfer function describes a phase-minimum system with no zero.

Looking at the other converters treated in Section 2, one can see that the converters according to Figure 7 (the RLT Buck–Boost), Figure 12 (the RLT Boost), Figure 15 (the RLT Zeta), Figure 17 (the RLT Cuk), Figure 20 (the RLT Super Boost) have a linearized voltage transformation ratio, when the duty cycle of the second switch is held constant. This leads to a phase-minimum behavior of the transfer function between the output voltage and the duty cycle of the first switch.

4. Voltage Stress Across the Semiconductors of RLT Converters

4.1. RLT Buck (Figure 3)

The first switch is on during the first mode and has to block the difference between the input and the output voltages in the second mode, and during the third mode, the input voltage. The second switch is turned on during the first two modes and has to block the output voltage during the third mode. The first diode must block the output minus the input voltages during the first mode, conduct during the second mode, and stay nearly at zero during mode three. The second diode has to block the input voltage during mode one, the output voltage during mode 2, and conduct during the third mode.

4.2. RLT Buck–Boost (Figure 7)

The active switch S1 is on during M1 and must block the input voltage during M2, and the sum of the input and the output voltages during M3. The second switch S2 is on during M1 and M2 and has to block the output voltage during M3. The diode D1 is stressed only during M1, during which it must hold the input voltage. Diode D2 is stressed during M1 with the sum of the input and the output voltages, stressed with the output voltage during M2, and conducts during M3.

4.3. RLT Boost (Figure 11)

During M1, S1 is on, during M2, it has to block the input voltage, and during M3, the output voltage. The second switch S2 is on during M1 and M2 and must block the difference between the output and the input voltages during M3. Diode D1 must hold the input voltage during M1, conduct during M2, and stay near zero during M3. The output diode D2 has to block the output voltage during M1 and only the difference between output and input voltages during M2, and conducts during M3.

4.4. RLT Zeta (Figure 15)

The first switch has to block the input voltage during M2 and during M3, the sum of the input and output voltages. The second switch is on during M1 and M2 and blocks the voltage across the intermediate capacitor C1 which is equal to the output voltage during M3. Diode D1 blocks the input voltage during M1, conducts during M2, and stays near zero in M3, because the second transistor takes the voltage. The diode D2 must block the voltage across the intermediate capacitor C1 which is equal to the output voltage and the input voltage during M1, blocks the voltage across C1 (equal to the output voltage) during M2, and conducts during M3.

4.5. RLT Cuk (Figure 17)

The voltage across the intermediate capacitor C1 is the sum of the input and the output voltages. When switch S1 turns off and mode M2 begins, the transistor S1 has to block the input voltage, and in mode M3, the voltage of the intermediate capacitor C1. Switch S2 is on during M1 and M2 and has to block the voltage across C1 minus the input voltage during M3. The diode D1 blocks the input voltage during M1 and is nearly zero during M2 and M3. The free-wheeling diode D2 must hold the voltage across C1 during M1 and during M2, the difference between the input and the intermediate capacitor voltages that is equal to the output voltage.

4.6. RLT Super Boost (Figure 21)

The voltage across C1 is equal to the output voltage. So one obtains for the voltage stress across S1 the input voltage during M2 and the capacitor voltage during M3. S2 is turned off at the end of M2 and has to block the difference between U2 and U1. The maximum voltage across D1 is during M1 and is equal to the input voltage. The diode D2 is stressed during M1 with the voltage across C1 and during M2, by the input voltage minus the output voltage.

4.7. RLT D-Square Buck (Figure 24)

The voltage stresses across the diodes D1 and D2 are equal to the input voltage. The main transistor S1 has to block the input voltage during M2 and the sum of the voltage across C1 and the input voltage during M3. The maximum stress across S2 is during M3 and is equal to the voltage across C1. The additional diode D4 must block the difference between the input voltage and the voltage across C1 during the first mode. The free-wheeling diode D3 is conducting during the second and the third modes and has to block the voltage across C1 during mode M1. D4 has to block the input voltage minus the voltage across C1.

4.8. RLT D1/(1-D1-D2) Converter (Figure 28)

The voltage across the intermediate capacitor C1 is equal to the output voltage. When the main transistor S1 turns off, the voltage across it goes up the sum of the voltage across C1 and the input voltage and reaches two times the output voltage plus the input voltage in M3. The additional switch S2 has to block the output voltage during M3. The sum of the input and the voltage across C1 stresses the diode D1 during M1. The diode D2 is stressed by two times the output voltage plus the input voltage during M1, and during M2, the output voltage.

4.9. Summery Voltage Stress

The voltage stress of the semiconductors is now summarized.

Table 1. Voltage stress across the semiconductors of the second-order converters.

	S1	S2	D1	D2
Buck	U1	U2	U1	U1
Boost	U2	U2 − U1	U1	U2
Buck–Boost	U1 + U2	U2	U1	U1 + U2

summarizes the results for the second-order converters,

Table 2. Voltage stress across the semiconductors of the fourth-order converters.

	S1	S2	D1	D2
RLT Zeta	U1 + U2	U2	U1	U2
RLT Cuk	U1 + U2	U1	U1	U1 + U2
RLT Super Boost	U2	U2 − U1	U1	U2
RLT D1/(1 − D1 − D2)	2U2 + U1	U2	U1 + U2	2U2 + U1

for the fourth-order converters, and

Table 3. Voltage stress across the semiconductors of the d-square Buck converter.

	S1	S2	D1	D2	D3	D4
D-SquareBuck	U1·(1 + D1)	U1·D1	U1	U1	D1·U1	U1·(1 − D1)

for the D-square converter. The D-square converter has four diodes and the numbers for the diodes are different, therefore, a separate table is used.

5. Connections Between the Currents

5.1. Simple Approximation of the Currents

Considering large inductors means that the current ripple is low. To obtain the connections between the mean values of the current through the coils, one has to observe the currents through the capacitors. In the steady state, they must be zero in the mean.

5.1.1. Currents Through the Second Order Converters

In the RLT Buck converter, the current that flows through the output capacitor is the current through the coil reduced by the load current during M1, the negative load current during M2, and again the same current as in M1 during M3. The current through the capacitor is always minus I_LOAD plus the current through the inductor minus the current through the bypass. Only during the time interval (d₂ − d₁)·T, the current of the coil is shunted and is not flowing into the output node. The current through the coil flows into the output node during M1 (d₁T) and M3 (1 − d₂)T and not during M2 (d₂ − d₁)T. Therefore, the charge balance (the time T is reduced) leads to

$${\stackrel{\_}{I}}_L\left(1+d_1-d_2\right)=I_{LOAD}.$$

(37)

For the Buck–Boost converter the negative load current flows through the capacitor during the first and the second mode, and during M3 the difference between the current through the coil and the load current. Only in mode M3, the current through the coil flows into the output node. So one obtains the charge balance (T is reduced)

$${\stackrel{\_}{I}}_L\left(1-d_2\right)=I_{LOAD}.$$

(38)

The current balance through the capacitor in the Boost converter is the same as that for the Buck–Boost converter. For a small current ripple through the coils, the rms value is near to the mean value. The rms values are calculated with large inductors (small current ripple). This is now shown for the primary switch S1. To evaluate the rms value, the current through the coil is assumed equal to its mean value. The square of the rms value is given by

$$I_{S1rms}^2={\displaystyle \frac{1}{T}}{\displaystyle \underset{0}{\overset{d1T}{\int }}{\stackrel{\_}{I}}_L^2}dt={\stackrel{\_}{I}}_L^2{d}_1.$$

(39)

The results are summarized in

Table 4. Currents through the components of the second-order converters.

	$\frac{{\stackrel{\_}{\mathit{I}}}_{\mathit{L}}}{{\mathit{I}}_{\mathit{L}\mathit{O}\mathit{A}\mathit{D}}}$	$\frac{{\mathit{I}}_{\mathit{S}1\mathit{r}\mathit{m}\mathit{s}}}{{\mathit{I}}_{\mathit{L}\mathit{O}\mathit{A}\mathit{D}}}$	$\frac{{\mathit{I}}_{\mathit{S}2\mathit{r}\mathit{m}\mathit{s}}}{{\mathit{I}}_{\mathit{L}\mathit{O}\mathit{A}\mathit{D}}}$	$\frac{{\mathit{I}}_{\mathit{D}1\mathit{r}\mathit{m}\mathit{s}}}{{\mathit{I}}_{\mathit{L}\mathit{O}\mathit{A}\mathit{D}}}$	$\frac{{\mathit{I}}_{\mathit{D}2\mathit{r}\mathit{m}\mathit{s}}}{{\mathit{I}}_{\mathit{L}\mathit{O}\mathit{A}\mathit{D}}}$
Buck	${\displaystyle \frac{1}{1+d_1-d_2}}$	${\displaystyle \frac{\sqrt{d_1}}{1+d_1-d_2}}$	${\displaystyle \frac{\sqrt{d_2-d_1}}{1+d_1-d_2}}$	${\displaystyle \frac{\sqrt{d_2-d_1}}{1+d_1-d_2}}$	${\displaystyle \frac{\sqrt{1-d_2}}{1+d_1-d_2}}$
Buck–Boost	${\displaystyle \frac{1}{1-d_2}}$	${\displaystyle \frac{\sqrt{d_1}}{1-d_2}}$	${\displaystyle \frac{\sqrt{d_2-d_1}}{1-d_2}}$	${\displaystyle \frac{\sqrt{d_2-d_1}}{1-d_2}}$	${\displaystyle \frac{\sqrt{1-d_2}}{1-d_2}}$
Boost	${\displaystyle \frac{1}{1-d_2}}$	${\displaystyle \frac{\sqrt{d_1}}{1-d_2}}$	${\displaystyle \frac{\sqrt{d_2-d_1}}{1-d_2}}$	${\displaystyle \frac{\sqrt{d_2-d_1}}{1-d_2}}$	${\displaystyle \frac{\sqrt{1-d_2}}{1-d_2}}$

.

5.1.2. Currents Through the Fourth-Order Converters

A glance at the circuit diagrams of the Zeta (Figure 15), the Cuk (Figure 17), the Super Boost (Figure 21), and the d-square Buck (Figure 24) converters shows that the mean current through the second inductor must be equal to the load current.

For the first three topologies, the negative current through the second coil flows through the intermediate capacitor C1 during M1 and M2. During the third mode M3, only the current through the first coil flows through C1. So one obtains

$$I_{LOAD}{d}_2={\stackrel{\_}{I}}_{L1}\left(1-d_2\right).$$

(40)

The results are summarized in

Table 5. Currents through the components of the fourth-order converters.

	$\frac{{\stackrel{\_}{\mathit{I}}}_{\mathit{L}1}}{{\mathit{I}}_{\mathit{L}\mathit{O}\mathit{A}\mathit{D}}}$	$\frac{{\stackrel{\_}{\mathit{I}}}_{\mathit{L}2}}{{\mathit{I}}_{\mathit{L}\mathit{O}\mathit{A}\mathit{D}}}$	$\frac{{\mathit{I}}_{\mathit{S}1\mathit{r}\mathit{m}\mathit{s}}}{{\mathit{I}}_{\mathit{L}\mathit{O}\mathit{A}\mathit{D}}}$	$\frac{{\mathit{I}}_{\mathit{S}2\mathit{r}\mathit{m}\mathit{s}}}{{\mathit{I}}_{\mathit{L}\mathit{O}\mathit{A}\mathit{D}}}$	$\frac{{\mathit{I}}_{\mathit{D}1\mathit{r}\mathit{m}\mathit{s}}}{{\mathit{I}}_{\mathit{L}\mathit{O}\mathit{A}\mathit{D}}}$	$\frac{{\mathit{I}}_{\mathit{D}2\mathit{r}\mathit{m}\mathit{s}}}{{\mathit{I}}_{\mathit{L}\mathit{O}\mathit{A}\mathit{D}}}$
Zeta, Cuk, Super Boost	${\displaystyle \frac{d_2}{1-d_2}}$	1	${\displaystyle \frac{\sqrt{d_1}}{1-d_2}}$	${\displaystyle \frac{\sqrt{d_2-d_1}}{1-d_2}}$	${\displaystyle \frac{\sqrt{d_2-d_1}}{1-d_2}}$	${\displaystyle \frac{1}{\sqrt{1-d_2}}}$

.

5.1.3. Currents Through the D-Square Converter

The current–time balance at the capacitor C1 can be found according to

$$\left|{\stackrel{\_}{I}}_{L1}-{\stackrel{\_}{I}}_{L2}\right|d_1={\stackrel{\_}{I}}_{L1}\left(1-d_2\right) \mathrm{and} \mathrm{with} {\stackrel{\_}{I}}_{L2}=I_{LOAD}.$$

(41)

One can calculate the mean value of the current through L1.

Table 6. Currents through the components of the d-square Buck converter.

	$\frac{{\stackrel{\_}{\mathit{I}}}_{\mathit{L}1}}{{\mathit{I}}_{\mathit{L}\mathit{O}\mathit{A}\mathit{D}}}$	$\frac{{\stackrel{\_}{\mathit{I}}}_{\mathit{L}2}}{{\mathit{I}}_{\mathit{L}\mathit{O}\mathit{A}\mathit{D}}}$	$\frac{{\mathit{I}}_{\mathit{S}1\mathit{r}\mathit{m}\mathit{s}}}{{\mathit{I}}_{\mathit{L}\mathit{O}\mathit{A}\mathit{D}}}$	$\frac{{\mathit{I}}_{\mathit{S}2\mathit{r}\mathit{m}\mathit{s}}}{{\mathit{I}}_{\mathit{L}\mathit{O}\mathit{A}\mathit{D}}}=\frac{{\mathit{I}}_{\mathit{D}4\mathit{r}\mathit{m}\mathit{s}}}{{\mathit{I}}_{\mathit{L}\mathit{O}\mathit{A}\mathit{D}}}$	$\frac{{\mathit{I}}_{\mathit{D}1\mathit{r}\mathit{m}\mathit{s}}}{{\mathit{I}}_{\mathit{L}\mathit{O}\mathit{A}\mathit{D}}}$	$\frac{{\mathit{I}}_{\mathit{D}2\mathit{r}\mathit{m}\mathit{s}}}{{\mathit{I}}_{\mathit{L}\mathit{O}\mathit{A}\mathit{D}}}$	$\frac{{\mathit{I}}_{\mathit{D}3\mathit{r}\mathit{m}\mathit{s}}}{{\mathit{I}}_{\mathit{L}\mathit{O}\mathit{A}\mathit{D}}}$
D-Square Buck	${\displaystyle \frac{d_1}{1+d_1-d_2}}$	1	$\sqrt{d_1}$	${\displaystyle \frac{d_1\sqrt{d_2-d_1}}{1+d_1-d_2}}$	${\displaystyle \frac{\left(1-d_2\right)\sqrt{d_1}}{1-d_2}}$	${\displaystyle \frac{d_1\sqrt{1-d_2}}{1+d_1-d_2}}$	$\sqrt{1-d_1}$

shows the mean value of the currents and the rms values of the currents through the semiconductors.

5.1.4. Currents Through the D1/(1 − D1 + D2) Converter

The charge balance of the capacitors

$$\left|-{\stackrel{\_}{I}}_{L2}-I_{LOAD}\right|d_2=\left({\stackrel{\_}{I}}_{L1}-I_{LOAD}\right)\left(1-d_2\right), {\stackrel{\_}{I}}_{L1}{d}_1+{\stackrel{\_}{I}}_{L2}\left(d_2-d_1\right)+{\stackrel{\_}{I}}_{L2}\left(1-d_2\right)=0$$

(42)

leads to the results shown in

Table 7. Currents through the components of the D1/(1-D1+D2) converter.

	$\frac{{\stackrel{\_}{\mathit{I}}}_{\mathit{L}1}}{{\mathit{I}}_{\mathit{L}\mathit{O}\mathit{A}\mathit{D}}}$	$\frac{{\stackrel{\_}{\mathit{I}}}_{\mathit{L}2}}{{\mathit{I}}_{\mathit{L}\mathit{O}\mathit{A}\mathit{D}}}$	$\frac{{\mathit{I}}_{\mathit{S}1\mathit{r}\mathit{m}\mathit{s}}}{{\mathit{I}}_{\mathit{L}\mathit{O}\mathit{A}\mathit{D}}}$	$\frac{{\mathit{I}}_{\mathit{S}2\mathit{r}\mathit{m}\mathit{s}}}{{\mathit{I}}_{\mathit{L}\mathit{O}\mathit{A}\mathit{D}}}$	$\frac{{\mathit{I}}_{\mathit{D}1\mathit{r}\mathit{m}\mathit{s}}}{{\mathit{I}}_{\mathit{L}\mathit{O}\mathit{A}\mathit{D}}}$	$\frac{{\mathit{I}}_{\mathit{D}2\mathit{r}\mathit{m}\mathit{s}}}{{\mathit{I}}_{\mathit{L}\mathit{O}\mathit{A}\mathit{D}}}$
D1/(1 − D1 + D2)	${\displaystyle \frac{1-d_1}{1-d_1-d_2}}$	${\displaystyle \frac{d_1}{1-d_1-d_2}}$	${\displaystyle \frac{\sqrt{d_1}}{1-d_1-d_2}}$	${\displaystyle \frac{\sqrt{d_2-d_1}}{1-d_1-d_2}}$	${\displaystyle \frac{\sqrt{d_2-d_1}}{1-d_1-d_2}}$	${\displaystyle \frac{\sqrt{1-d_2}}{1-d_1-d_2}}$

.

5.2. Onward Losses

With the help of these tables (Table 4, Table 5, Table 6 and Table 7), one can approximately calculate the onward losses of the components of the converters. With the parasitic resistors of the inductors RL1, RL2 one obtains for the coils

$$P_{LL1}=R_{L1}{\left({\stackrel{\_}{I}}_{L1}\right)}^2, P_{LL2}=R_{L2}{\left({\stackrel{\_}{I}}_{L2}\right)}^2.$$

(43)

With on-resistors of the electronic switches RS1 and RS2, one obtains for the losses

$$P_{LS1}=R_{S1}{\left({\stackrel{\_}{I}}_{S1rms}\right)}^2, P_{LS2}=R_{S2}{\left({\stackrel{\_}{I}}_{LS2rms}\right)}^2.$$

(44)

The diodes are modeled by a fixed knee-voltage VD and the differential resistor RD to obtain the losses across the diodes according to

$$P_{LDi}=R_{Di}{\left({\stackrel{\_}{I}}_{Dirms}\right)}^2+V_{Di}{\stackrel{\_}{I}}_{Dirms},$$

(45)

with i as the number of the diode. The losses of the diodes dominate the losses of the complete converter. It should be mentioned that the rms value for S1 and D2 has a larger error compared to the currents through coils. The ripple in these components is higher because it is the sum of the ripple of both inductor currents. A detailed exact calculation is explained in Section 5.5. For higher-power applications, it can be useful to shunt the diodes with active electronic switches. Additional driver units are now necessary which increases the cost. The loss across the diodes is reduced and therefore the cooling effort is reduced, too, and this can even lead to reduced cost. Weight and volume are also influenced. As an example, this is shown for the Super Boost converter. Figure 36a shows an improvement of the bypass by connecting the auxiliary switch SH1 antiparallelly to the first diode, and Figure 36b shows both diodes shunted by an additional auxiliary switch.

Summarizing all losses of the components to PL, one obtains the efficiency

$$\eta ={\displaystyle \frac{P_{OUT}}{P_{IN}}}={\displaystyle \frac{P_{OUT}}{P_{OUT}+P_L}}.$$

(46)

To reduce the switching losses, fast semiconductors based on SiC technology can be used, and/or snubbers or zero voltage switching ZVS concepts can be applied.

5.3. Reduction of the Loss Compared to the Traditional Tristate Converter

All components except S2 have the same losses in the regular and in the RLT versions. The reduction factor for the Buck converter is now derived. The same result can be found for the two other second-order converters. The same factor can also be found for the fourth-order converters. In this case, the current flowing through S2 is the sum of both inductor currents. For the quadratic Buck, it is a little more complicated but it is also given. In the here-treated tristate converters, the current flows through the switch S2 only during mode M2. In the traditional one, however, the current through the coils is also flowing through the second switch S2 during M1 and not only during M2. The losses at all other components do not change. For the traditional tristate Buck converter, one can write for the square of the rms value of the current through S2

$$I_{S2rms}^2={\displaystyle \frac{1}{T}}{\displaystyle \underset{0}{\overset{d_{2}T}{\int }}{\stackrel{\_}{I}}_L^{2}dt=}{\left({\displaystyle \frac{I_{LOAD}}{1+d_1-d_2}}\right)}^2{d}_2.$$

(47)

The approximate loss reduction factor of S2 is defined by

$${\displaystyle \frac{I_{S2rmsRLT}}{I_{S2rms}}}={\displaystyle \frac{\sqrt{d_2-d_1}}{\sqrt{d_2}}}.$$

(48)

The same result can also be found for the Buck–Boost and Boost converters. For the linear fourth-order converters, the sum of both currents through the coils is always flowing through S2 during the first two modes for the traditional version and only during M2 in the RLT version. The reduction factor is the same as given in (48).

For the quadratic converter, the reduction factor is more complicated and can be found according to

$${\displaystyle \frac{I_{S2rmsRLT}}{I_{S2rms}}}={\displaystyle \frac{\frac{d_1\sqrt{d_2-d_1}}{1+d_1-d_2}}{\sqrt{d_1+\frac{d_1^2\left(d_2-d_1\right)}{{\left(1+d_2-d_1\right)}^2}}}}={\displaystyle \frac{d_1\sqrt{d_2-d_1}}{\sqrt{d_1+2d_1^2-2d_1{d}_2-d_1^2{d}_2+d_1{d}_2^2}}}.$$

(49)

5.4. Input and Output Currents

The form of the input and the output currents is another interesting question. Are the currents continuous (abbreviation C) or discontinuous (abbreviation D)?

Table 8. Continuous or discontinuous input and output currents.

	Buck	Buck–Boost	Boost	Zeta	Cuk I	Cuk II	Super Boost	Quadratic Buck	D1/(1 − D1 − D2)
IN	D	D	D	D	D	C	D	D	D
OUT	D	D	D	C	C	D	C	C	D

summarizes the results.

When the input current is discontinuous, an input capacitor must be placed at the input of the converter to avoid overvoltage at the switching devices caused by the parasitic inductance between the supplying source and the converter. When the output current is discontinuous, a larger output capacitor is necessary than that which must be used in the continuous case.

5.5. Precise Calculation of the Currents

For the Super Boost, the more precise calculation of the currents is demonstrated. We start with the load current. Because the output capacitor C2 is so large, the voltage across it is nearly constant. During M1, the current rises, starting from IL20, according to the voltage across the coil of UC1 + U1 − U2. The voltage across the capacitor C1 is equal to the output voltage U2. The current rises by $\Delta I_{L2}$. During M2, the voltage across the coil is nearly zero and the current stays nearly constant. The current decreases by $\Delta I_{L2}$ in the third mode. To better understand the following calculation Figure 37 is included.

One obtains the mean value of the current through the coil ideally with the integration of

$${\stackrel{\_}{I}}_{L2}=I_{LOAD}={\displaystyle \frac{1}{T}}{\displaystyle \underset{0}{\overset{d1T}{\int }}\left(I_{L20}+\frac{\Delta I_{L2}}{d_{1}T}t\right)}dt+{\displaystyle \frac{1}{T}}{\displaystyle \underset{d1T}{\overset{d2T}{\int }}\left(I_{L20}+\Delta I_{L2}\right)}dt+{\displaystyle \frac{1}{T}}{\displaystyle \underset{d2T}{\overset{T}{\int }}\left(I_{L20}+\Delta I_{L2}-\frac{\Delta I_{L2}}{\left(1-d_2\right)T}t\right)}dt.$$

(50)

This results in

$${\stackrel{\_}{I}}_{L2}=I_{LOAD}=I_{L20}+{\displaystyle \frac{\Delta I_{L2}}{2}}\left(1+d_2-d_1\right).$$

(51)

From (51), one can obtain the starting point of the current in the steady state to

$$I_{L20}=I_{Load}-{\displaystyle \frac{\Delta I_{L2}}{2}}\left(1+d_2-d_1\right).$$

(52)

The current ripple can be found by

$$\Delta I_2={\displaystyle \frac{U_1{d}_{1}T}{L_2}}.$$

(53)

The maximum value is given by

$$I_{L2\max }=I_{L20}+\Delta I_{L2}=I_{L20}+{\displaystyle \frac{U_1{d}_{1}T}{L_2}}.$$

(54)

In the next step, we look at the current through the capacitor C1. During M1 and M2, the negative current through L2 discharges the capacitor a little, and during M3, the capacitor is charged again by the current through L1. The mean value of the current through L1 only referred to the duration of M3 multiplied by the duration of M3 must be as large as the charge that was taken from the capacitor during the modes M1 and M2. The mean value of the current through an inductor is calculated over the complete period. For the here-demonstrated calculation of the currents, only the mean value during M3 is necessary and this differs from the mean value of the current. This is caused by the fact that the currents through the inductors in a tristate converter are not triangular but have some time where the current stays constant. Therefore, one can write

$${\stackrel{\_}{I}}_{L1M3}\left(1-d_2\right)T=\left[{\displaystyle \underset{0}{\overset{d1T}{\int }}\left(I_{L20}+\frac{\Delta I_{L2}}{d_{1}T}t\right)}+{\displaystyle \underset{d1T}{\overset{d2T}{\int }}\left(I_{L20}+\Delta I_{L2}\right)}dt\right].$$

(55)

The mean value of the current through L1 referred to the off-time of switch S2 (the off-time of S2 is equal to the mode M3) is now obtained according to

$${\overline{I}}_{L1,M3}=\left[I_{20}{d}_2+\Delta I_{L2}\left(d_2-{\displaystyle \frac{d_1}{2}}\right)\right]/\left(1-d_2\right).$$

(56)

The maximum value of the current through L1 can now be calculated according to

$$I_{L1,\max }={\overline{I}}_{L1,M3}+{\displaystyle \frac{\Delta I_{L1}}{2}}.$$

(57)

One can now calculate the current ripple according to

$$\Delta I_{L1}={\displaystyle \frac{U_1{d}_{1}T}{L_1}}$$

(58)

and obtain the starting point of the current through L1 according to

$$I_{L10}={\overline{I}}_{L1,M3}-{\displaystyle \frac{\Delta I_{L1}}{2}}.$$

(59)

The mean value of the current through L1 can be found by the same method as for the mean value of L2 leading to

$${\stackrel{\_}{I}}_{L1}=I_{L10}+{\displaystyle \frac{\Delta I_{L1}}{2}}\left(1+d_2-d_1\right)$$

(60)

5.6. Inrush Currents

When the converter is connected to a constant input voltage with a low output resistor, a very high inrush current can occur (cf. 2.5). Converters with a switch directly at the input avoid this and the start-up of the converter is performed by increasing the duty cycle starting from zero.

Table 9. Inrush? YES (Y) or NO (N).

	Buck	Buck–Boost	Boost	Zeta	Cuk I	Cuk II	Super Boost	Quadratic Buck	D1/(1 − D1 − D2)
INRUSH	N	N	Y	N	Y	Y	Y	N	N

shows that for the here-discussed converters, whether an inrush (Y) or no one occurs (N).

6. Conclusions

To reduce the forward losses in a tristate converter, a series connection of a second electronic switch S2 and an additional diode D1 is connected in parallel to a coil of a basic DC/DC converter, instead of replacing the original transistor of the e.g., Buck converter by a series connection of two electronic switches and a diode in between them.

In higher-order converters with two coils, there are two possibilities to connect the bypass branch.

During the first mode M1, both electronic switches are on and both diodes are off. In the second mode M2, only the second switch is on and the first diode is conducting, and in mode M3, only the second diode is conducting.

Compared to the traditional tristate converter, where current flows through both electronic switches during the modes M1 and M2, current flows through the second switch only during M2. This reduces the forward losses of the converter.

The voltage transformation ratio of tristate converters is a function of the duty cycles of the two switches.

The duty cycle of the first switch is defined as the on-time of the switch S1 and is referred to as the switching period. If the two switches are not switched on contemporarily, the definition of the duty cycle d₂ of the second switch S2 is different from the usual definition: d₂ must be defined as the time interval between the turn-on of switch S1 and the turn-off of switch S2 referred to the switching period.

To achieve the tristate operation, the duty cycle of switch S2 must be larger than that of switch S1. In the simulations, both switches are turned on at the same time.

Using the duty cycle of switch S2 as the parameter, and the duty cycle of switch S1 as an independent variable, the voltage transformation ratio of step-up converters (e.g., the Boost, the Buck–Boost, the Zeta, the Cuk, the Super Boost) is linearized, and the small signal model has phase-minimum behavior.

In the figures depicting the voltage transformation ratio of the converters, one can see that the steepness can be adapted to fit the application used.

Compared to other tristate concepts, the losses across the second switch are reduced, leading to a small improvement of the efficiency, depending on the operating point and the used components of about 0.5 up to 2%. Other features of the original converter are maintained.