High-Precision Low-Power Interface Circuit for Two-Dimensional Integrated Magnetic Switches

Abstract

This paper proposes a high-precision low-power interface circuit for two-dimensional (2D) integrated magnetic switches that can detect 2D magnetic fields and output 5 V CMOS digital signals. The interface circuit combines chopper stabilization and output offset storage technology to effectively suppress the offset of the entire signal chain and significantly improve detection accuracy. Additionally, an architecture-level signal processing algorithm is proposed, which not only realizes full polarity detection of the magnetic field at a low cost but also realizes switch detection of multi-dimensional magnetic fields in the interface circuit without additional processing. Furthermore, the circuit provides flexible adjustment of both switch trip thresholds and hysteresis windows through 4-bit off-chip trimming codes, which greatly enhances the universality of the interface circuit. This chip is implemented using 180 nm BCD technology with a chip area of 1.18 ${\mathrm{mm}}^2$. The measurement results show that the interface circuit can simultaneously process 2D input signals with a resolution of less than 85 μV. In addition, through a 4-bit trim code, the interface circuit can adjust the switch trip threshold in the range of 0–13.52 mV and the hysteresis interval in the range of 0–7.32 mV. The average current consumption of the chip is 6.757 μA.

1. Introduction

With the iterative advancement of modern electronic technology, sensing technology has deeply penetrated all areas of human production and life [1]. As a typical representative of non-contact detection technology, magnetic switches enable the precise detection of displacement states, motion trajectories, and mechanical actions through the principle of magnetic field coupling [2], and exhibit excellent anti-mechanical vibration characteristics and high sensitivity.

The magnetic induction switches currently on the market are generally one-dimensional (1D) sensors [3,4], but, due to their lack of sensitivity to the direction of the magnetic field, they face significant limitations in wide-angle magnetic sensing applications. As an important component of the integrated magnetic switch, the interface circuit is the key to achieving high-precision, low-power, and multi-dimensional sensing. Affected by non-ideal factors such as process deviations, temperature drift, and packaging stress, the input offset voltage of CMOS operational amplifiers that have not undergone offset calibration generally reaches the millivolt level [5,6], which will significantly degrade the effective detection accuracy of the magnetic switch for magnetic sensitive devices with low output voltage characteristics such as silicon-based hall elements [7,8]. In terms of energy efficiency optimization, the kiloohm-level internal resistance of magnetic sensitive elements results in milliampere-level static current losses, which significantly contradicts the trend toward miniaturization and low power consumption in modern sensing systems. In addition, as shown in

Table 1. Comparison of magnetic sensing elements.

Magnetic Sensor Element	Sensitivity (mV/(V×mT))	Output Voltage of 10 mT (mV)
GaAs Hall element [9]	0.183–0.367	1.83–3.67
InAs Hall element [9]	0.6–0.967	6–9.67
InSb Hall element [9]	0.82–7.4	8.2–74
Silicon-based Hall element [7]	0.03–0.0408	0.3–0.408
AMR 1	1–10	10–100

¹ anisotropic magnetoresistance.

, due to the different sensitivities of different types of magnetic sensor elements, a set of interface circuits needs to be customized for different types of magnetic sensor elements. This behavior of reinventing the wheel will greatly waste manpower and material resources.

In order to achieve multi-dimensional detection, reference [10] designed a three-dimensional (3D) integrated magnetic switch, but its interface circuit only amplifies and compares the input signals in three dimensions, respectively. The detection results in the three dimensions are independent of each other and require additional digital signal processing. In terms of high-precision detection, reference [11] used chopping technology to suppress the offset of the first stage of the instrumentation amplifier in the interface circuit, but did not process the offset of the entire signal chain of the entire interface circuit, which would result in a relatively large residual offset. In addition, reference [12,13] did not perform any offset suppression on the interface circuit. In terms of versatility, relatively few studies have been published.

The 2D magnetic switches can not only solve the problem of 1D magnetic switches’ sensitivity to magnetic field direction but also significantly reduce costs and power consumption compared with 3D magnetic switches. These advantages make them particularly suitable for position detection requiring wide magnetic field sensing angles, such as industrial liquid level position detection, smart meter anti-magnetic attack detection, etc. This paper studies the dedicated interface circuit of 2D magnetic switches. We combined chopper stabilization and output offset storage technology to effectively suppress the overall circuit offset. Through both the physical circuit and the proposed switch generation algorithm, the 2D omnidirectional and omnipolar switch detection was achieved at low cost without the need for additional digital signal processing. In addition, clock-controlled micro-power technology was used to significantly reduce the chip power consumption without affecting the performance of the 2D magnetic switch signal processing chip. Finally, off-chip trim technology was used to achieve a custom configuration of the switching threshold and hysteresis range, enhancing the versatility of the 2D magnetic switch interface circuit application.

In Section 1, we introduce the research background and significance of 2D integrated magnetic switches and the interface circuit. Section 2 analyzes the basic detection principles of 2D integrated magnetic switches. In Section 3, the design of a high-precision low-power interface circuit for 2D integrated magnetic switches is introduced. In Section 4, the chip measurement results are discussed. Finally, Section 5 provides the conclusion.

2. Basic Detection Principle of the 2D Integrated Magnetic Switch

In practical applications, the NS pole plane of the magnet is parallel to the chip plane, as shown in Figure 1a, so that the magnetic flux lines emitted by the magnet are parallel to the chip surface. By decomposing the magnetic induction intensity in the chip plane into vertical and horizontal components, two mutually perpendicular magnetic induction vectors are obtained, as shown in Figure 1b.

Two mutually perpendicular magnetic induction intensity vectors are detected by two 1D magnetic sensing elements, such as magnetoresistive bridge, Hall element, etc., to convert the magnetic signals into electrical signals. Subsequently, the electrical signals from these two elements are processed by the 2D integrated magnetic switch interface circuit to determine whether a switch action should be triggered.

In this design, when the absolute value of the differential output voltage from either of the two 1D magnetic sensing elements exceeds the predefined threshold, the interface circuit triggers the switch action, thereby enabling a 2D magnetic field threshold judgment. The threshold window is illustrated in Figure 2, where $V_B$ is the voltage corresponding to the total magnetic induction intensity in the plane where the chip is located, $V_X$ is the voltage in the X direction, $V_Y$ is the voltage in the Y direction, $V_{op}$ is the operating point voltage, and $V_{rp}$ is the release point voltage. Based on the 360° switch threshold achieved by the interface circuit in this paper, when combined with magnetic sensing elements, it can achieve linear position switch measurement.

3. Interface Circuit Architecture and Principle

Figure 3 illustrates the block diagram of the 2D integrated magnetic switch interface circuit architecture, comprising the amplification module, summation module, comparison module, switching signal generation and driving module, and auxiliary module. The 2D magnetic field information is detected by orthogonal 1D magnetic sensing elements aligned along the X and Y axes, which convert the magnetic signals into electrical signals. Subsequently, the electrical signals undergo amplification, sampling, summation, and comparison, followed by algorithmic processing to ultimately generate and output a 5 V CMOS digital switch signal.

3.1. High-Precision Signal Processing Path

As shown in Figure 4, it is the analog signal path of the interface circuit. The key factors affecting comparison accuracy in this analog signal path are the offset and noise of the instrumentation amplifier, the offset of the switched capacitor amplifier, and the offset of the comparator. Therefore, this paper combines chopper stabilization and output offset storage technology [14,15,16,17,18] to achieve full signal chain offset and noise suppression, thereby achieving high-precision switch detection.

As shown in Figure 4, to eliminate the offset and noise of the instrumentation amplifier, the chopper instrumentation amplifier structure is used. The chopper amplifier consists of two chopper switches and an instrumentation amplifier. The instrumentation amplifier employs two identical CMOS operational amplifiers to form a dual-terminal in-phase amplification structure, as illustrated in Figure 4. This configuration effectively isolates the input signal source while delivering high input impedance. By precisely adjusting the resistor ratio, the instrumentation amplifier maintains a stable closed-loop gain. The chopper switch structure is illustrated in Figure 5. During the high phase of the control clock CLK, switches S1 and S2 are activated to conduct current, $V_{OP}=V_{IP}$ and $V_{ON}=V_{IN}$. Conversely, when CLK transitions to its low phase, conduction is transferred to switches S3 and S4, $V_{OP}=V_{IN}$ and $V_{ON}=V_{IP}$.

The ideal voltage waveforms at different circuit nodes of the chopper amplifier [19] are depicted in Figure 6. The first chopper modulates the input signal to a higher frequency. Then, the amplifier amplifies the modulated signal superposed on its own input offset, $V_{os1}$. Lastly, the second chopper demodulates the amplified input signal and modulates the output offset of the instrumentation amplifier. An output signal with an offset ripple and no DC offset is obtained at point D. Since global chopping technology is used, the output formulas in the two phases of the chopping sequence are as follows:

$$V_{o1}=A\ast \left(V_{IP}-V_{IN}\right)+A\ast V_{os1}$$

(1)

$$V_{o2}=A\ast \left(V_{IP}-V_{IN}\right)-A\ast V_{os1}$$

(2)

where $V_{o1}$ is the differential output of the chopper amplifier when the chopper clock is high, $V_{o2}$ is the differential output when the chopper clock is low, and $A$ is the closed-loop gain of the chopper amplifier.

To eliminate the output offset ripple of the chopper amplifier, the fully differential switched capacitor amplifier architecture [20] is adopted in this paper. Its simplified model is shown in Figure 7. The switched-capacitor amplifier adopts bottom plate sampling technology to eliminate the influence of parasitic capacitance. In addition, the switched capacitor amplifier has six inputs, which sample the differential switch threshold voltage and the output of the instrumentation amplifier at different phases of the chopper clock. These inputs perform addition and subtraction operations on the voltages, thereby eliminating the output offset ripple of the chopper amplifier and subtracting the switch transition threshold from the input signal.

As shown in Figure 8, the schematic diagram illustrates the relationship between the sampling timing and the chopping timing. When the switched-capacitor amplifier is in the ${\phi }_1$ phase, switches S1 and S6 are closed, while S2, S3, S4, and S5 are disconnected, placing the amplifier in a reset state. In the ${\phi }_2$ phase, switches S2 and S6 are closed, while S1, S3, S4, and S5 are disconnected, allowing the amplifier to sample the output voltage of the chopper amplifier, $V_{o1}$, as shown in Formula (1). In the ${\phi }_3$ phase, switches S2, S3, and S6 are closed, while S1, S4, and S5 are disconnected, placing the amplifier in a reset state again. In the ${\phi }_4$ phase, switches S2, S4, and S5 are closed, while S1, S3, and S6 are disconnected, enabling the amplifier to sample the output voltage of the chopper amplifier, $V_{o2}$, as shown in Formula (2), along with the switch threshold voltage $V_T$. Then, through charge sharing, the addition and subtraction operations of the three are realized and output.

Therefore, the fully differential switched capacitor amplifier output formula is as follows (in this design, $C_2=2C_1$):

$$V_o=0.5\ast \left[V_{o1}+V_{o2}-2V_T\right]+V_{os2}$$

(3)

where $V_{os2}$ is the offset voltage of the main op-amp of the switched-capacitor amplifier.

Since the output offset voltage of the switched capacitor amplifier is the same in both the sampling phase ${\phi }_{1-3}$ and the amplification phase ${\phi }_4$, the offset of the main op-amp of the switched capacitor amplifier can be regarded as the input offset of the next stage circuit. Additionally, since the output voltage of the switched capacitor amplifier exhibits a discrete time signal characteristic, as shown in Figure 4, the comparator adopts the architecture of the pre-amplifier and dynamic comparator [21] and employs output offset storage technology to eliminate both the offset of the pre-amplifier and the offset of the main op-amp.

As shown in Figure 9, $V_{os4}=V_{os3}+V_{os2}$, where $V_{os3}$ is the original offset voltage of the pre-amplifier. The comparator works in two phases, namely the offset storage phase and the amplification phase. In the offset storage phase, the switch $S$ is closed, the output offset of the pre-amplifier is stored on the capacitor, and the voltage difference across the capacitor $C$ is:

$$V_C=V_{ref}-V_{cm}+A_{pre}\ast V_{os4}$$

(4)

where $A_{pre}$ is the gain of the pre-amplifier, $V_{cm}$ is the output common mode voltage of the pre-amplifier, and $V_{ref}$ is a reference voltage.

When the comparator is in the amplification phase, switch $S$ is turned off. The input signal after pre-amplification is minus the output offset voltage of the pre-amplifier. The final differential output voltage formula of the pre-amplifier is as follows:

$$V=A_{pre}\ast \left(A\ast \left(V_{IP}-V_{IN}\right)-V_T\right)$$

(5)

The specific implementation circuit diagram of the comparator is shown in Figure 10. The pre-amplifier uses a diode-connected MOSFET as a load and operates in an open-loop amplification state. Its open-loop gain is 20.29 dB and the −3 dB bandwidth is 4.14 MHz. Since the dynamic comparator is reset during the offset storage phase, an SR latch is added to latch the comparison result in the amplification phase.

As shown in Figure 11, it is the Monte Carlo simulation result of the combined offset voltage of the switched capacitor amplifier and the pre-amplifier and the offset voltage of the chopper amplifier.

3.2. Switch Signal Algorithm

As shown in Figure 12, the schematic diagram illustrates the switch signal generation logic. Figure 13 shows the corresponding chopper switch clock control timing. By using the chopper switch in Figure 12 and the control timing in Figure 13, the input switching and input polarity switching functions of the 1D magnetic sensor element in the X and Y directions are realized. Therefore, in the four chopping cycles (a, b, c, and d), four comparison results (A, B, C, and D) are obtained, which respectively represent the four comparison results between the output signal of the 1D magnetic induction element in the X direction, the output signal in the X direction after polarity reversal, the output signal of the 1D magnetic induction element in the Y direction, and the output signal in the Y direction after polarity reversal and the set switching threshold. These results are input into the switching signal algorithm module and stored by four D flip-flops, respectively, as shown in Figure 14. Then, the final digital switch signal is obtained through the combinational logic in the following formula:

$$S{W}_{out}=\left(A\odot B\right)\left(C\odot D\right)$$

(6)

This combinational logic realizes that, when any one of the four comparison results is low, the 2D magnetic switch interface circuit outputs a low level, which represents that the input signal exceeds the threshold, thereby realizing the full polarity threshold judgment of the 2D magnetic field at a low cost. Additionally, by using $XOR$ logic instead of $AND$ logic, false triggering of the switch caused by the comparison results of A and B or C and D being simultaneous is prevented, thereby enhancing the robustness of the circuit.

3.3. Switching Threshold and Hysteresis Range Design

The magnetic switch transition threshold generation circuit is illustrated in Figure 15. Here, $VP$ and $VN$ are the outputs of the chopper amplifier. The equivalent switch threshold formula at the input of the 2D magnetic switch interface circuit is as follows ($R_1=R_2=R$):

$$V_T=2\ast I\ast R/A$$

(7)

In this design, the switching threshold is adjusted by varying the current, $I$. To enhance the versatility of the interface circuit, a 4-bit trim code is implemented to adjust the threshold. Additionally, if hysteresis needs to be set, it can be achieved by externally connecting the interface circuit’s output pin, $S{W}_{out}$, to one of the trim code pins. Since a low level on $S{W}_{out}$ indicates that the input signal exceeds the threshold, this connection allows the hysteresis interval to be configured. The final switch threshold formula of the 2D magnetic switch interface circuit is as follows:

$$V_{op}=2\left(2^3\ast Bit3+2^2\ast Bit2+2^1\ast Bit1+2^0\ast Bit0\right)\ast I_{0}R/A$$

(8)

$$V_{rp}=2\left(2^3\ast Bit3+2^2\ast Bit2+2^1\ast Bit1+2^0\ast Bit0-2^x\ast Bitx\right)\ast I_{0}R/A$$

(9)

where $V_{op}$ is the operating point voltage of the switching threshold, $V_{rp}$ is the release point voltage of the switching threshold, $Bit3-0$ represents the input code of the 4-bit trim code, $Bitx$ is the bit represented by the trim code to which the output of the 2D magnetic switch interface circuit is connected, and $I_0$ is the unit current value of the current source.

Therefore, by incorporating a 4-bit trim code, the switching transition threshold and hysteresis range can be flexibly configured to adapt to various application fields and requirements, greatly enhancing the versatility of the 2D magnetic switch interface circuit.

3.4. Sleep and Wake-Up Mode

This low-power 2D integrated magnetic switch signal processing chip is designed by using clock-controlled micro-power technology. The clock logic circuit inside the chip enables the chip to sample external input signals at a frequency of 20 Hz. There are two working states in one cycle: awake state and sleep state. In the awake state, the output voltages of the two 1D magnetic sensor elements are sampled, and the chip works with a fast clock. After 9.5 fast clock cycles, the chip enters sleep mode. In sleep mode, the power consumption of the chip is almost negligible, as shown in Figure 16. And Figure 17 shows the breakdown of power consumption. In the awake state, all modules of the chip are operational, resulting in a current consumption of 2.432 mA. In the sleep state, only the 20 Hz low-speed oscillator and digital output driver remain active, reducing the chip’s power consumption to 3.989 μA. During the 50 ms detection cycle, the chip remains active for only 57 μs and spends the remainder of the cycle in sleep state. This approach has reduced the chip’s average current consumption from 2.432 mA to 6.757 μA while ensuring proper operation of the 2D integrated magnetic switch interface circuit.

4. Results and Analysis

The chip has been fabricated in 0.18 um BCD technology with an area of 1.18 ${\mathrm{mm}}^2$. And, to reduce the impact of mechanical stress on the 2D magnetic switch interface circuit chip during the packaging process, the chip is packaged in bare chip COB (Chips on Board) [22]. The microscope photo of the chip is shown in Figure 18.

In this design, the bias of the two 1D magnetic sensing elements is supplied by the interface circuit and is only provided in the wake-up mode to minimize power consumption. Therefore, the slow clock working cycle can be obtained by measuring the bias pin voltage. As shown in Figure 19, the measurement results indicate that the detection frequency is 20 Hz. And Figure 20 shows the output bias current of four samples.

The input–output relationship measurement result of the chip is shown in Figure 21. In this photograph, the two triangular wave signals serve as positive inputs along the X and Y axes, respectively, while their corresponding negative inputs are biased at the common-mode voltage. The bottom digital signal is the 5 V CMOS digital output signal of the interface circuit. The diagram demonstrates that switching activation occurs when either directional input signal surpasses its predetermined threshold level. This operational characteristic effectively illustrates the chip’s capability for two-dimensional full-polarity detection.

To enhance the versatility of the 2D magnetic switch interface circuit to adapt to different application scenarios, a 4-bit trim code is designed to configure the chip’s jump threshold and hysteresis interval. Since the two 1D magnetic sensing elements share a set of interface circuits, one group is given a differential triangle wave signal, while the other group is given a common mode signal during measuring. To accurately measure the chip’s jump threshold under different codes, the hysteresis interval size is set to 0 during the measurement (that is, the chip output is not connected to any trim code pin). The measurement results of the chip under different trim codes are shown in Figure 22. These results demonstrate that the switch jump threshold can be adjusted within the range of 0 to 13.52 mV and the hysteresis threshold can be adjusted within the range of 0 to 7.32 mV through trim. In addition, the gain error in Figure 22 is mainly caused by the switch transition threshold voltage in the circuit being greatly affected by the process and has nothing to do with the high-precision signal chain.

The performance of the proposed interface circuit is summarized and compared with other magnetic switch interface circuits in

Table 2. Comparison of the magnetic switch interface circuit.

Parameters	[12]	[10]	[13]	This Work
Process (μm)	0.18	0.18	0.5	0.18/BCD
$\mathrm{Chip}\mathrm{area}({\mathrm{mm}}^2$)	0.396	1.46	NA	1.18
Supply voltage (V)	3.3	3.3	5	5
Operating point voltage (mV)	0.41	0.41	40.5–55.35	0–13.52
Release point voltage (mV)	0.26	0.28	27–36.9	0–13.52
Hysteresis voltage (mV)	0.15	0.13	3.6–28.35	0–7.32
Operating frequency (Hz)	20	NA	NA	20
Average current consumption (μA)	7.89	>14.85	NA	6.757
Trim code (bit)	0	0	0	4
Dimensions	1	3	1	2

. Compared with reference [12], this circuit not only realizes multi-dimensional detection but also slightly reduces the average current consumption. Although reference [10] realizes three-dimensional detection, on the one hand, its average current consumption is particularly large, and, on the other hand, its three-dimensional detection results are independent of each other, requiring additional signal processing. Reference [13] can only perform one-dimensional magnetic field detection, and the switching threshold is very large and is not suitable for high-precision detection scenarios. None of these three references give the specific offset size, so no comparison is made here. Finally, none of the three can adjust the switching threshold, so this design is slightly better in flexibility and practicality.

5. Conclusions

This paper uses the 180 nm BCD process to design a 2D integrated magnetic switch interface circuit. Chopper technology and output offset storage technology are used to effectively suppress the offset voltage of the interface circuit, improve the performance of the interface circuit, and achieve extremely low offset. Furthermore, by combining the physical circuit and the algorithm, the 2D omnidirectional and omnipolar switch detection function is realized. At the same time, sequential logic is employed to regularly control the chip’s sleep and wake-up cycles, thereby reducing average current consumption from 2.432 mA to 6.757 μA. Finally, the off-chip trim method is used to realize the flexible configuration of the switching threshold and hysteresis interval of the interface circuit to adapt to different application scenarios and enhance the versatility of the interface circuit.