Programmable Gain Amplifier with Programmable Bandwidth for Ultrasound Imaging Application

Abstract

This paper presents a low-power, fully differential, programmable gain amplifier (PGA) for ultrasound receiver analog front-ends (AFE). It consists of a programmable attenuator implemented by a capacitive voltage divider and a closed-loop amplifier based on a differential difference amplifier (DDA). A suitable sizing strategy provides orthogonal control over gain and bandwidth. The PGA was designed using a standard 180 nm CMOS process. The gain value can be set between −18 dB and +20 dB in 2 dB steps; the bandwidth can be programmed independently of gain, to values from 5 MHz to 20 MHz, in 5 MHz steps; it draws 600 µA from a 1.8 V supply line. It achieves a differential output swing of 0.8 V peak-to-peak differential with no more than 1.7% total harmonic distortion (THD) and an input-referred noise density of 22 nV/√Hz at 10 MHz, measured at the gain of 20 dB. The PGA exhibits high input impedance and low output resistance for easy integration within the AFE signal chain. The digitally controlled gain and bandwidth make this PGA suitable for ultrasound imaging applications requiring precise time gain compensation and adjustable frequency response and/or additional anti-aliasing filtering.

1. Introduction

Historically, ultrasonography has been the main application of ultrasound in biomedical imaging, where transducers generate acoustic waves that penetrate the body and monitor the signal reflecting off tissues to create images based on variations in acoustic impedance.

Traditional piezoelectric transducers are increasingly being replaced by capacitive micro-machined ultrasound transducers (CMUTs) and piezoelectric micro-machined ultrasound transducers (PMUTs), offering broad bandwidth of 1–20 MHz, high sensitivity, and improved integration in high-density arrays in ASICs via flip-chip bonding. PMUT-based arrays require lower bias voltage (<10 V) compared to CMUT, where greater than 100 V DC bias is required; however, they have increased variation with process [1,2].

Ultrasound signals are exponentially attenuated when traveling in the human body. The rate of attenuation depends on the transmitted signal frequency, required imaging depth, and attenuation constant of the medium, which require a receiver circuit capable of handling a large dynamic range [3].

Figure 1 presents a block diagram of an integrated receiver for an ultrasound imaging system. It comprises three functional blocks: a low-noise amplifier (LNA)—with input impedance adapted to the transducer device—followed by a time gain compensation (TGC) loop that changes the receiver gain depending on the reflected signal strength [4], and an anti-aliasing filter (AAF). The TGC usually comprises a programmable gain amplifier (PGA) and a low-pass filter with programmable gain (LPF). The programmable bandwidth is an essential feature for ultrasound imaging systems because it enables adjustments to various transducer types and imaging depths, as well as advanced processing methods such as harmonic imaging [5].

Gain, bandwidth, noise figure (or input-referred noise), power consumption, and linearity are the main design parameters for ultrasound receivers. Effective system-level design is necessary to properly set the block-level requirements while meeting the overall performance required by the system. Neither this topic nor the LNA design, which are well covered elsewhere [1,2,6], are addressed here. Instead, this paper focuses on an effective implementation of the ensemble PGA + LPF with programmable bandwidth.

There are three main architectures for implementing programmable or variable gain control in amplifiers [7]. The most popular one is based on conventional OpAmps and the voltage feedback (series-shunt) topology [8]. Such PGAs are relatively straightforward to analyze and design, but their performance is hindered by the inherent constant gain–bandwidth product (GBW)—a major limitation for an application that requires both high gain and large bandwidth. The second approach is to employ current feedback and/or current feedback OpAmps (CFB/CFB-OA) [9,10]. This surpassed the constant GBW limitation and helped improve the dynamic performance. However, its main limitations are related to significantly increased power consumption and die area, relative to the first approach.

The third architecture involves transconductance control [11], where the gain is varied by adjusting the transconductance of the circuit. This approach is followed in this work but applied to a differential difference amplifier (DDA)-based circuit. The DDA is a versatile analog building block [12], commonly used in various sensor applications [13], and instrumentation amplifiers [14]. It consists of two transconductors and a gain stage, with one transconductor operating in open loop while the other is enclosed in a feedback loop together with the gain stage and an external passive network.

The main idea is to implement the PGA+LPF ensemble illustrated in Figure 1 by using only one DDA-based circuit. This approach enables independent control of gain and bandwidth, while the compact implementation reduces noise and power consumption.

The remainder of this paper is structured as follows: Section 2 presents the architecture of the proposed PGA+LPF, discusses the principle of operation using a brief mathematical analysis, and then details a compact circuit implementation. Section 3 presents a comprehensive set of simulation results, that validate the design. In addition, the performance of the proposed circuit is compared against similar prior works, highlighting its advantages. Finally, Section 4 summarizes the main points and concludes the paper.

2. Circuit Implementation

2.1. DDA-Based Programmable Bandwidth PGA Circuit

Figure 2 shows the block diagram of the DDA-based PGA with controlled, programmable bandwidth. The circuit comprises two main components: a programmable capacitive voltage divider and an indirect current feedback DDA. The programmable capacitive divider provides coarse gain control from −18 dB to 0 dB in 6 dB steps. The DDA facilitates fine gain adjustment from 0 dB to 20 dB in 2 dB increments while maintaining a constant bandwidth. Together, these components form the PGA circuit with a total gain range of 38 dB in 2 dB steps, which enables the TGC to attenuate reflected signals from the surface of the skin and amplify signals that are reflected from the deep tissue, maximizing the dynamic range and linearity.

The attenuator circuit is implemented by a binary-weighted programmable capacitor array with 2.7 pF unit capacitance, adding up to 43.2 pF total capacitance. The 6 dB gain steps are realized by connecting the Cg<2:0> capacitor units in parallel. Capacitor C implements AC coupling between the LNA and the PGA, and resistors, R_ICM, are used to set the common mode voltage of V_{CM_IN} at the DDA input V_INP and V_INM.

The DDA consists of two transconductors, denoted by Gm₁ and Gm₂ in Figure 2, followed by a high-gain operational amplifier with the GBW set by the frequency compensating capacitors Cc. In order to implement a PGA, the series shunt feedback network formed by R₁ and R₂ is placed around the DDA. The voltage gain of the resulting PGA is expressed by Equation (1), while its bandwidth is described by Equation (2).

$${\mathrm{A}}_{\mathrm{d}}={\displaystyle \frac{{\mathrm{G}\mathrm{m}}_1}{{\mathrm{G}\mathrm{m}}_2}}·\left(1+{\displaystyle \frac{{2·\mathrm{R}}_1}{{\mathrm{R}}_2}}\right)$$

(1)

$$\mathrm{B}\mathrm{W}={\displaystyle \frac{{\mathrm{G}\mathrm{m}}_2}{{2·\pi ·\mathrm{C}}_{\mathrm{C}}}}·\left(1+{\displaystyle \frac{{2·\mathrm{R}}_1}{{\mathrm{R}}_2}}\right)$$

(2)

Unlike a conventional OA-based circuit with series-shunt feedback, here, the gain–bandwidth product is not constant. This allows for orthogonal control of the PGA gain and bandwidth: the PGA gain can be adjusted through Gm₁, without affecting the bandwidth, while the PGA bandwidth can be modified independently of its gain through Cc. Thus, programmable gain and bandwidth can be achieved by digitally controlling the values of the transconductance Gm₁ and the OA compensation capacitor C_C.

2.2. Transistor-Level Implementation of the Proposed Circuit

Figure 3 presents the transistor-level schematic of the PGA core. It is a DDA-based voltage amplifier with a topology similar to the one described in [15]. The two matched differential input stages with resistive degeneration are implemented by transistors M₁, M₂, and Rd₁ and M₃, M₄, and Rd₂. The transconductances of these stages are largely determined by their degeneration resistors, assuming that the product of input transistor transconductances gm__M1,2 and gm__M3,4 and the corresponding degeneration resistors, Rd1 and Rd2, is far larger than unity:

$$\mathrm{G}\mathrm{m}={\displaystyle \frac{{\mathrm{g}\mathrm{m}}_{\mathrm{M}}/2}{1+{\mathrm{g}\mathrm{m}}_{\mathrm{M}}·{\mathrm{R}}_{\mathrm{d}}/2}}\approx {\displaystyle \frac{1}{{\mathrm{R}}_{\mathrm{d}}}} \mathrm{i}\mathrm{f} {\mathrm{g}\mathrm{m}}_{\mathrm{M}}·{\mathrm{R}}_{\mathrm{d}}/2\gg 1$$

(3)

By substituting Equation (3) in Equations (1) and (2) and by choosing R₂ = 2·R₁, one obtains:

$${\mathrm{A}}_{\mathrm{d}}={\displaystyle \frac{{2\mathrm{R}\mathrm{d}}_2}{{\mathrm{R}\mathrm{d}}_1}}; {\mathrm{A}}_{\mathrm{d}}\propto {\displaystyle \frac{1}{{\mathrm{R}\mathrm{d}}_1}}$$

(4)

$$\mathrm{B}\mathrm{W}={\displaystyle \frac{2}{2·\pi ·{\mathrm{C}}_{\mathrm{C}}{·\mathrm{R}\mathrm{d}}_2}}; \mathrm{B}\mathrm{W}\propto {\displaystyle \frac{1}{{\mathrm{C}}_{\mathrm{c}}}}$$

(5)

Resistors Rg_1,2 set the common mode voltage at the OA input nodes, denoted by V_P and V_M in Figure 3. During regular operation, the signal amplitude on these nodes is relatively small, equal to the DDA output signal divided by the OA gain.

The differential input voltage is converted into a circular current by Gm_M1; this circular current closes through Gm_M2, which converts it back to a differential voltage on the terminals of resistor R₂. The resulting differential voltage on resistor R₂ generates a second circular current, which is converted back to the differential output voltage by pushing it and pulling it through the two resistors, R₁ connected to the output V_OUTP and V_OUTM.

Figure 4 shows the transistor-level implementation of the OA within the DDA.

It is a fully differential operational amplifier (OA) with a folded-cascode input stage and a class-AB output stage based on the Monticelli design [16]. Class-AB was chosen over the class-A output stage because of its improved frequency response and current drive capacity. The dedicated bias circuit dynamically adjusts the current through the output stage to maintain the linearity for varying currents. The push-pull output gives 2× equivalent output transconductance, allowing for a better frequency response with only half the bias current of a class-A output. The output common-mode voltage is set by using a fairly simple error amplifier that drives the net V_CMCTRL.

To implement programmable bandwidth and bandwidth trimming for process variation, the four compensation capacitors within the OA, denoted by C_C in Figure 4, are implemented by digitally programmable capacitor arrays.

The resistor Rd₁ is implemented by a digitally programmable array of n = 11 pairs of resistors built by using different numbers of the same unit resistor, as shown in Figure 5. A thermometric code is used to control the switches; that ensures precise gain control, minimizes the required resistor count, and reduces the mismatch across the programmable gain range. This arrangement allows the PGA gain to be set between 0 and 20 dB, in 2 dB steps, as indicated by Equation (4).

3. Simulation Results

The PGA was implemented in a 180 nm CMOS process from AMS. It uses a 1.8 V supply, drawing 600 µA while driving a 10 pF differential load capacitor.

Table 1. Device sizes for the programmable BW PGA.

ATTENUATOR from Figure 2		Class-AB FD-OA from Figure 4
RICM (kΩ)	250	MIN1,2 (N × W/L)	2 × 20 µ/200 n	Mirror ratios: DIODE M = 1 with bias current 5 µ A
C/CG<2:0 > (pF)	2.7/7 × 2.7	MPO1,2 (W/L)	10 µ/200 n
TSW (M × (W/L))	2 × (4 µ/180 n)	MNO1,2 (N × W/L)	6 × 5 µ/200 n	MBP1, MBC1: M = 4
PGA CORE from Figure 3		MBPX (W/L)	10 µ/200 n	MBP2, MBC2: M = 2
M1,2,3,4 (M × (N × W/L))	2 × (2 × 20 µ/200 n)	MCPX (W/L)	10 µ/180 n	MBP1,2cm, MBC1,2cm: M = 2
MP1,2,3,4 (M × (N × W/L))	10 × (1 × 12 µ/800 n)	MBNX (W/L)	5 µ/5 µ	MBN1,2: M = 3
Rd1 total/Rd2 (kΩ)	32.2/2 × 7.5	MCNX (W/L)	5 µ/180 n	McN1,2: M = 8
R1/R2 (kΩ)	30/60	MN (W/L)	5 µ/500 n	MB1,2cm, MC1,2cm: M = 1
Rg1,2 (kΩ)	4	MP (W/L)	10 µ/500 n	MN,P: M = 2
CC total (pF)	1.2	Mcm1,2 (W/L)	4 µ/300 n
IB (µ A)	100	Rdcm, Rocm (kΩ)	100

presents the device sizes for the entire design: the attenuator circuit input capacitor and the binary-weighted programmable capacitor array are built using the same unit capacitor, C = 2.7 pF controlled by transistors T_SW; and the resistors used to set input common-mode level have fairly large values, R_ICM = 250 kΩ. The PGA core shown in Figure 3 was sized considering current consumption, linearity, and noise performance. For optimum noise and linearity, the bias current for the DDA core was set to IB = 100 µA.

When maximum voltage swing is applied to the transconductor formed by M_1,2/M_3,4, the resulting circular current reaches 25 µA; this provides sufficient operational margin to ensure reliable and linear operation without compromising THD performance. From the PGA perspective, the class-AB FD-OA was designed to drive the 10 pF differential capacitive load and to facilitate programmability of the PGA bandwidth through digital control of capacitors Cc, while consuming 200 µA. The class-AB output stage provides good linearity performance with increased drive capability and aids the OA loop stability with the double-output transconductance compared to a simple common source output stage.

Figure 6 presents the loop gain magnitude and phase frequency characteristics for the feedback circuit formed by the FD-OA, resistors R₁ and R_2, and the transconductor implemented by transistors M_3,4. These characteristics are very similar to the frequency response of a typical two-pole system, demonstrating that the circuit is stable for all gain and bandwidth settings. Moreover, the results listed in the adjacent table indicate a very small sensitivity to the PGA gain setting: when the gain is varied between 0 and 20 dB, the resulting phase margin varies by less than one degree, with the mean value changing from 75.8 to 65 degrees as the PGA bandwidth is set to 10 MHz, then 20 MHz.

Figure 7a presents the closed-loop frequency response of the entire PGA across all gain settings, ranging from −18 dB to 20 dB in 2 dB increments, for two settings of the PGA bandwidth: 10 MHz (red traces) and 20 MHz (black traces). The vertical cursors indicate the upper cutoff frequency. These plots indicate that, once the PGA bandwidth was set through digital controls, its measured value is largely independent of the PGA gain. The zoom-in shown in Figure 7b indicates that once the gain value was set through digital controls, the measured PGA gain remains constant in the frequency range of interest, from 1 MHz up to the two programmed values of the PGA bandwidth. These results demonstrate the orthogonal programmability of the proposed PGA gain and bandwidth, as predicted by Equations (4) and (5).

Figure 8 presents the impact of the process, supply voltage (1.8 V ± 10%), and temperature (−40 to +125 °C) variations (PVT) on the PGA gain and bandwidth. Figure 8a shows that, over the entire range of PVT variations, the PGA gain remains within ±1 dB of its set value, while Figure 8b presents the variation over PVT of the PGA −3 dB cutoff frequency, as a function of the gain setting; it shows that the cutoff frequency remains within ±10% of its programmed value across the entire gain range.

The capacitive attenuator placed at the PGA sets the lower crossover frequency; Figure 7a indicates that its value is approximately 300 kHz. It also determines the PGA input impedance, Zin; Figure 9 presents the module frequency characteristic of Zin for each of the four possible settings of the attenuator. The minimum value, 6.74 kΩ, is obtained for the setting that yields the maximum attenuation, all Cg < 2:0 > = ON. This is a large enough value for the LNA to handle.

In ultrasound applications, the time gain compensation (TGC) adjusts the PGA gain according to a predefined control profile, requiring fast gain settling within 100 ns [17, 18]. Figure 10 presents the PGA output voltage and its corresponding envelope as the gain is increased incrementally from 0 to 20 dB; a zoom-in provides data on the PGA response to a gain step change. The PGA output voltage settles within 35 ns after each gain step, with negligible overshoot, ensuring a rapid response to TGC control signals.

Figure 11a presents the 1 dB output-referred compression point (OCP1dB) for all gain settings. The value corresponding to peak-to-peak differential signaling and a 50 Ω load is approximately 11 dBm, largely independent of the gain; this demonstrates that the proposed PGA is able to handle large signals, with amplitudes up to 560 mV peak single-ended, without significant compression. Results for another metric for linearity are presented in Figure 11b: total harmonic distortion (THD) obtained for all gain settings, measured for the following scenario: a sinewave with the frequency of 5 MHz applied at the input, and the output signal level maintained at 200 mV peak single-ended. The PGA BW was set to the maximum value, 20 MHz, and the common-mode voltage levels at both the input and output differential ports were set to 400 mV. This test yielded THD values no larger than 1.7% across the entire gain range, further proving the excellent linearity of the proposed PGA.

Figure 12a presents a 5 MHz peak-to-peak differential ultrasound input signal with predefined amplitudes applied to the PGA input. The gain setting of the PGA is adjusted to produce a nearly constant output signal with a peak amplitude of 400 mV differential, as illustrated in Figure 12b.

The PGA noise performance across the entire gain range is presented in Figure 13. The minimum input-referred spot noise voltage, measured at 10 MHz, is 22 nV/√Hz at the maximum gain setting of 20 dB and increases to 1.7 µV/√Hz at the minimum gain setting of −18 dB. The RMS noise, measured over a bandwidth of 1 to 20 MHz, is 98 µVrms at 20 dB gain and 7.5 mVrms at −18 dB gain. The PGA noise performance was optimized by balancing current consumption with the system requirements, considering that an LNA with an input-referred noise (IRN) of at least 10 nV/√Hz is required to pre-condition weak ultrasound signals.

Table 2. Performance summary and comparison.

Parameter/Units	This Work	[9]	[11]	[17]	[18]	[19]	[20]	[21]
Gain range (dB)	−18 to 20	0 to 24	0 to 14	0 to 30	−10 to 27	−24 to 24	−12 to 24	10 to 40
Gain step (dB)	2	4	2	3.75	2	0.19	0.5	5
Gain error (dB)	0.9	-	-	-	3.9	-	-	-
Cutoff Frequency, fC (MHz)	20	20	30	9.4	0.02–8	82	10–25	40
VoutMAX 1 (VppDiff)	0.8	0.7	1	0.15	0.94	2	2	0.8
$\mathrm{IR} \mathrm{Spot} \mathrm{Noise} (\mathit{nV}/\sqrt{Hz}$)	22.4 at 10 MHz	-	56	4.8	-	4.1	4.25	13.7
IRN RMS (µV)	98.1	-	244.1	-	-	-	18.5	-
Supply Voltage (V)	1.8	1.05	1.8	1.8	3.3	1.8	1.8	1.8
Supply Current (mA)	0.6	4.76	0.58	0.61	0.58	4.8	2	2.33
Power (mW)	1.08	5	1.04	1.1	1.9	8.64	3.6	4.2
Process (µm)	0.18	0.028	0.18	0.18	0.35	0.18	0.18	0.18
FOM	1176.78	28.01	114.4	26.37	220.94	4664.77	827.31	135.68

¹—Maximum output voltage amplitude for which distortions do not hinder system operation. For this work, it is THD < 2%.

summarizes the performance of the PGA with programmable bandwidth proposed here and compares it against similar designs published in the last decade.

Figures of Merit (FoMs) are often used to compare the overall performance of circuits designed for the same application with similar yet significantly different parameters. With respect to Table 2, the parameters listed there can be split into two categories: parameters for which the larger the value, the better the performance—gain range, Fc max, Vout_max—and those for which the smaller the value, the better the performance—gain step, supply voltage, power consumption. The FoM introduced by Equation (6) is simply the ratio between the product of parameters in the first category and the product of parameters in the second category. One could add to the second category a parameter related to the die area required for integration and a parameter related to the noise performance—such as the spot noise at the same frequency or the RMS noise integrated over the same bandwidth. However, for most PGAs presented in Table 2, these data are not available.

$$\mathrm{F}\mathrm{O}\mathrm{M}={\displaystyle \frac{\mathrm{G}\mathrm{a}\mathrm{i}\mathrm{n}\_\mathrm{r}\mathrm{a}\mathrm{n}\mathrm{g}\mathrm{e}[\mathrm{V}/\mathrm{V}]\times {\mathrm{f}}_{\mathrm{C}}\left[\mathrm{M}\mathrm{H}\mathrm{z}\right]\times {\mathrm{V}\mathrm{o}\mathrm{u}\mathrm{t}}_{\mathrm{M}\mathrm{A}\mathrm{X}}\left[\mathrm{V}\right]}{\mathrm{G}\mathrm{a}\mathrm{i}\mathrm{n}\_\mathrm{s}\mathrm{t}\mathrm{e}\mathrm{p}[\mathrm{V}/\mathrm{V}]\times \mathrm{V}\mathrm{s}\mathrm{u}\mathrm{p}\mathrm{p}\mathrm{l}\mathrm{y}\left[\mathrm{V}\right]\times \mathrm{I}\mathrm{s}\mathrm{u}\mathrm{p}\mathrm{p}\mathrm{l}\mathrm{y}\left[\mathrm{m}\mathrm{A}\right]}}$$

(6)

Obviously, FoMs should only be used for quick-and-rough comparisons. For the PGA presented here, the main system-level requirement was to minimize power consumption, while ensuring the necessary gain range, frequency operating range, and linearity. This is reflected by data listed in Table 2: with respect to the FoM defined by Equation (6), our PGA is surpassed by [19]; however, its power consumption is 8 times smaller, even if it was implemented in a similar 0.18 um process and operated at the same supply voltage, 1.8 V. Moreover, our PGA helps reduce the power consumption of the entire system, as it also provides a programmable bandwidth, independent of the gain setting.

4. Conclusions

This work presented the design and simulation of a fully differential PGA tailored for compact implementation of the time gain compensation function in integrated ultrasound receivers. It consists of a programmable attenuator implemented by a capacitive voltage divider and a closed-loop amplifier based on a differential difference amplifier.

The DDA-based topology, combined with a suitable sizing strategy, provides orthogonal control over the PGA gain and bandwidth (that is, −3 dB cutoff frequency).

The proposed PGA was implemented using a 180 nm CMOS process from AMS, operating with a 1.8 V supply and consuming 600 µA of current. Its gain can be set between −18 dB and 20 dB in 2 dB increments, while the cutoff frequency can be programmed independently of gain to values from 5 MHz to 20 MHz, in 5 MHz steps. Besides the orthogonal control of gain and bandwidth, simulation results presented in the paper demonstrate the relative insensitivity of this design to process, supply voltage (1.8 V +/−10%), and temperature (−40 °C to +125 °C) variations: the PGA gain remains within ±1 dB of its set value for all PVT corners and gain/bandwidth settings and the cutoff frequency remains within ±10% of its programmed value across the entire gain range and PVT corners.

The PGA is able to drive a 10 pF differential capacitive load and exhibits very good linearity: the 1 dB output-referred compression point is around 11 dB for all gain settings; a THD better than 1.7% was obtained for all gain settings when the PGA outputted a 200 mV peak single-ended sinewave with the frequency of 5 MHz. The minimum IR spot noise voltage at 10 MHz is 22 nV/√Hz at the gain of 20 dB and 1.7 µ V/√Hz at −18 dB gain. RMS noise integrated over the frequency range 1 MHz–20 MHz is 98 μVrms for 20 dB gain and 7.5 mVrms for −18 dB. An important feature for time gain compensation is fats settling after a gain change: the proposed PGA settles in no more than 35 ns after a 2 dB gain step.