Study of Improved Active Clamp Phase-Shifted Full-Bridge Converter

Abstract

The polar energy router is a key device in the polar clean energy system which converges the output of wind power, photovoltaic units, energy storage units and hydrogen fuel cells through the power electronic power converter to the DC bus, which requires the use of a variety of specifications of DC/DC converters; as a result, the efficiency of the DC/DC converter is directly connected to the efficiency of the polar energy router. This paper presents an enhanced isolated DC/DC converter with a phase-shifted full-bridge topology designed to meet the high-efficiency conversion requirements of polar energy routers. Although soft switching can be realized naturally in phase-shifted full-bridge topology, it also faces challenges, such as the difficulty of realizing soft switching under light load conditions, large circulation losses, a loss of duty cycle and oscillation in the secondary-side voltage. To solve these problems, an improved scheme of the phase-shifted full-bridge converter with an active clamp circuit is proposed in this paper. The scheme realized zero-voltage switch (ZVS) under light load by utilizing clamp capacitor energy. The on-state loss was reduced by zeroing the primary-side current during the circulating phase. This paper provides a detailed description of the topology, working principle and performance characteristics of the improved scheme, and its feasibility has been verified through experiments.

1. Introduction

The polar energy router is a piece of hub equipment for converging wind turbines, photovoltaic units, energy storage units, hydrogen fuel cells and electrical loads in the polar clean energy system [1]. The isolated DC/DC converter is a crucial component of the polar energy router [2], and its operational reliability and efficiency greatly influence the reliability and energy efficiency of the polar energy router, thereby affecting the overall performance of the entire clean energy system.

The phase-shifted full-bridge topology is a typical power circuit for realizing isolated DC/DC power conversion and has attracted much attention due to the advantages of low current stress on semiconductor devices, high utilization of magnetic components, wide control range, high efficiency and constant switching frequency [3]. Nevertheless, there are some drawbacks, including the significant switching loss of the primary-side switching tube under light load conditions, the high voltage stress of the synchronous rectifier switching tube, the reduction in the duty cycle on the secondary side, the small soft-switching range and the high circulating current loss, which limit the popularization and application of the phase-shifted full-bridge topology.

A common way to solve the phase-shifted full-bridge topology problem is to extend the range of the zero-voltage switch (ZVS) by connecting resonant inductors in series to the primary side of the transformer and increasing the energy provided by charging and discharging the switching tubes of the lagging bridge arm; however, increasing the resonant inductor may lead to a more pronounced duty cycle loss. The conflict between ZVS range and duty cycle loss can be alleviated to a certain extent by replacing linear inductors in series with saturated inductors on the primary side of the transformer [4], but the saturated inductors have a limited energy storage capacity, and the introduction of auxiliary components in the power circuit also leads to additional losses and instabilities [5,6,7]. The energy deficit on the primary side of the transformer can be mitigated by adding clamping diodes and transformer leakage series, but the increase in inductance may exacerbate duty cycle loss [8]. To achieve a light-load ZVS on the primary side, one option is to utilize the reverse current in the output inductor and the increased magnetizing current in the main transformer. However, the clamp circuit function of this scheme is limited to limit the secondary-side overvoltage, while the circulating current conduction loss is also large [9,10,11]. Another scheme that can realize a light-load ZVS on the primary side is to optimize its modulation mode by judging the voltage ratio between the two ends of the inductor and the size of the transmitted power and resorting to appropriate switching rules [12]. To tackle the problem of circulating current losses, the zero-current switch (ZCS) of the lagging bridge arm can be implemented by quickly driving the primary current to zero during the circulating current phase, thereby not only eliminating duty cycle losses but also reducing circulating current losses [13,14]. In addition, the circulation can also be actively used in some cases to achieve energy balance; the MACP-MMC (Modular Multilevel Converter) in the case of flexible interconnection can actively inject the fundamental frequency circulation to achieve internal energy balance [15]. In addition to the above-mentioned methods, in order to improve power quality, a simplified digital logic-based scheme can also be adopted by improving dead-zone compensation, which only uses current polarity to determine the phase shift of the PWM signal using digital logic, and it adjusts pulse-width modulation signal waveforms by either delaying the leading edge or the lagging edge for dead-zone compensation, irrespective of the control and modulation methods employed [16].

For the purpose of overcoming the traditional phase-shifted full-bridge topology’s shortcomings, we solve the problems of voltage oscillation, duty cycle loss and high circulating current loss on the secondary side and widen the zero-voltage switch range. An improved active clamp phase-shifted full-bridge converter realization scheme is proposed in this paper that combines the improvement strategies of enhancing the ZVS currents and reducing the circulating currents, utilizing the energy in the clamp capacitor to achieve the lagging bridge arm’s ZVS under a light load, and reducing the circulating current in the loop phase to zero by precisely controlling the timing of the switches in the clamped switching tubes, ultimately reducing the primary- and secondary-side pass-state losses in the loop phase.

2. Improvement Strategy

On the secondary side, a current-doubling rectifier circuit is combined with the phase-shifted full-bridge ZVS converter topology, as shown in Figure 1, with node A as the midpoint of the lagging bridge arm and node B as the midpoint of the leading bridge arm. With the aim of realizing the soft switching of the power devices in the lagging bridge arm, when switch Q₁ is off, Q₂ is on, and the primary current needs to flow from the transformer into node B; when Q₂ is off, Q₁ is on, and the primary current needs to flow from the transformer into node A.

If a current enhancement module is added to the circuit, the module can inject the current into node A or node B when the primary-side switching tube carries out the switching operation; this means that the current flowing into node A or node B will be enhanced, thus assisting the parasitic capacitor of the primary-side switching tube in charging and discharging more efficiently to broaden the ZVS range. The schematic diagram of the current enhancement module is shown in Figure 2.

After considering the difficulty of circuit design and hardware cost, the active clamp circuit is used as the current enhancement module [17]. The circuit diagram of the active clamp circuit used as the current enhancement module is shown in Figure 3. The active clamp module has a simple structure and is composed of two fully controlled switch tubes Q_AC1 and Q_AC2 and two capacitors AC₁ and AC₂ with a large capacity. The fully controlled switch tubes are called clamped switching tubes and the capacitors are called clamp capacitors. Through two clamped switching tubes, a clamp capacitor is connected to the positive and negative terminals on the secondary side of the transformer.

3. Improved Active Clamp Phase-Shifted Full-Bridge Converter

3.1. Topological Structure

Figure 4 shows the main circuit topology. The transformer’s primary side employs a full-bridge topology with phase-shift control. Q₁ to Q₄ are four switching tubes, among which Q₁ and Q₂ are lagging tubes and Q₃ and Q₄ are leading tubes. L_r is the resonant inductance and leakage inductance. The secondary synchronous rectifier tubes Q_SR1 and Q_SR2 and the output inductors L_out1 and L_out2 constitute a double-current rectifier circuit. An active clamp circuit is formed by the clamped switching tubes Q_AC1 and Q_AC2 and the clamp capacitor AC. The active clamp circuit shown in the figure omits a clamp capacitor, which has no effect on the analysis of the operating principle and simplifies the analysis process.

The phase-shifted full-bridge converter obtains a quasi-square wave with an adjustable duty cycle by controlling the phase difference between the two bridge arms. The current-doubling rectifier circuit adopts synchronous control, and the active clamp circuit adopts a novel control method, whose advantages are listed below:

• The primary side’s switches can achieve a ZVS, reducing switching losses.
• There is no circulation on the primary side of the circulation stage, which reduces the on-state loss on the primary side.
• The two synchronous rectifiers conduct at the same time to jointly refill the current for the output inductor and reduce the secondary-side pass-state losses.
• There is no loss in duty cycle because there is no current commutation time.
• The clamped synchronous rectifier on the secondary side effectively prevents secondary-side overvoltage.

3.2. Modal Analysis

Each PWM cycle has 12 modes, and the upper half of the cycle is opposite to the lower half of the cycle; therefore, the upper half of the cycle is analyzed as an example. Figure 5 shows the time sequence chart of the primary waveform.

Switches Q₁, Q₂ and Q₃, Q₄ are complementarily switched at a 50% duty cycle minus a short dead time, and by controlling the phase shift between Q₁, Q₂ and Q₃, Q₄, the output voltage is regulated.

• Prior to t₀, the circuit is in the loop current stage; although the switching tubes Q₂ and Q₄ are in the on state, there is no current flowing through it, and the primary-side current remains zero. The transformer’s primary and secondary sides are electrically isolated, and energy is not transferred from the primary side to the secondary side. The two synchronous rectifiers Q_SR1 and Q_SR2 refill the current at the same time, and the currents I_Lout1 and I_Lout2 in the output inductor of the secondary side pass through the two synchronous rectifiers Q_SR1 and Q_SR2, respectively.
• Mode 1 (t₀–t₁): This stage is the stage of delayed bridge arm shutdown; at time t₀, Q₂ is off and Q_AC1 is on, which connects the secondary clamp capacitor to the secondary side of the transformer. This process is very short; therefore, the clamp capacitor can be considered a constant voltage source. The equivalent circuit is shown in Figure 6. Equivalent parallel capacitors C₁, C₂ and the resonant inductor L_r resonate; the primary current starts at zero and increases in the negative direction in the form of a sine wave, discharging C₁ and charging C₂. The expressions of the primary current, the voltage at both ends of the resonant inductor, and the voltage at both ends of the parasitic capacitor C₁ and C₂ are as follows:

$$i_{\mathrm{p}}(t)=-6V_{\mathrm{AC}}(t_0)\sqrt{{\displaystyle \frac{2C}{L_{\mathrm{r}}}}}\sin {\displaystyle \frac{1}{\sqrt{2L_{\mathrm{r}}\mathrm{C}}}}\left(t-t_0\right),$$

(1)

$$u_{\mathrm{L}}(t)=-6V_{\mathrm{AC}}(t_0)\cos {\displaystyle \frac{1}{\sqrt{2L_{\mathrm{r}}\mathrm{C}}}}\left(t-t_0\right),$$

(2)

$$u_{\mathrm{C}1}(t)=6V_{\mathrm{AC}}(t_0)\cos {\displaystyle \frac{1}{\sqrt{2L_{\mathrm{r}}C}}}\left(t-t_0\right),$$

(3)

$$u_{\mathrm{C}2}(t)=6V_{\mathrm{AC}}(t_0)\left(1-\cos {\displaystyle \frac{1}{\sqrt{2L_{\mathrm{r}}C}}}\left(t-t_0\right)\right).$$

(4)

At moment t₁, the voltage on the equivalent parallel C₁ is resonant to zero, and the voltage across C₂ raises to the input voltage, marking the completion of the charge–discharge process for C₁ and C₂. At this time, the primary current is negative, and the natural conduction of Q₁’s body diode D₁ is the continuous current of the primary current. The ZVS can be realized by turning on Q₁ after D₁ conduction.

The duration of this mode is the charge–discharge time of the lagging bridge arm, and the expression is as follows:

$$t_{01}=t_1-t_0={\displaystyle \frac{\pi }{2}}\sqrt{2L_{\mathrm{r}}C}.$$

(5)

From Equation (5), it is evident that the charge-discharge time is only related to the resonant inductor inductance value and the switching tube parasitic capacitor capacitance value, independent of the energy stored in the output inductor and independent of the load size.

The switching of the secondary side of the transformer and the clamp switching tube Q_AC1 will make the synchronous rectifier tube Q_SR1 stop, and the voltage at both ends of the Q_SR1 is clamped, thus avoiding the oscillation problem of the secondary-side voltage in the traditional phase-shifted full-bridge converter. At this stage, the clamp capacitor is in a discharge state, but because the clamp capacitance is large, the voltage amplitude does not change much. The energy released by the clamping capacitor is divided into two parts: One part flows into the output inductor Lout1 in the form of current to provide continuous current for the circuit and bear the output current that should flow through the cutoff Q_SR1. The other part of the current is returned to the original side, which is used to charge and discharge the parasitic capacitors C₁ and C₂, so as to achieve the ZVS of the lagging bridge switching tube Q₁.

3.

Mode 2 (t₁–t₂): This stage is the lagging bridge arm ZVS turn-on phase. Figure 7 shows the equivalent circuit. At moment t₁, the parasitic capacitor completes its charge–discharge process, and the body diode D₁ naturally refills the current, clamping the voltage across Q₁ at zero. After that, Q₁ is turned on to implement the ZVS. In order to ensure that the ZVS for the lagging bridge arm switching tube can be reliably achieved, the dead time of the lagging bridge arm should be greater than the charge and discharge time; that is, the charge and discharge time of C₁ and C₂ is shorter than the dead time of the driver signals for Q₁ and Q₂. The expression is as follows:

$$t_{d.lag}>t_{01}={\displaystyle \frac{\pi }{2}}\sqrt{2L_{\mathrm{r}}C}.$$

(6)

4.

Mode 3 (t₂–t₃): This stage is the power transfer phase. Figure 8 displays the equivalent circuit diagram. At t₂, Q₁ is turned on, and since the voltage at both ends of Q₁ is zero at this time, Q₁ achieves the ZVS. At this stage, both ends of the resonant inductor and clamp capacitor are directly affected by the input voltage, causing the clamp capacitor to resonate with the resonant inductor. Most of the input voltage V_in is added to the clamp capacitor through the transformer, while only a small portion of the input voltage acts on the resonant inductor. The primary side’s current is transferred from the body diode D₁ to the switching tube Q₁ and rises gradually in the form of a nearly sinusoidal waveform. As the primary current increases, when the current value reaches the output inductor current I_Lout1 value that is converted to the primary side, the clamp capacitor is converted from a discharging state to a charging state, and the volts–seconds balancing expression on the resonance inductor is as follows:

$${\displaystyle \frac{1}{L_{\mathrm{r}}}}{\displaystyle {\int }_{t_1}^{t_3}\left(V_{in}-6u_{AC}(t)\right)dt}=i_p(t_3)-i_p(t_1).$$

(7)

The expression of the average voltage of the clamping capacitor in modes 2 and 3 is as follows:

$$V_{\mathrm{AC}.\mathrm{eq}}={\displaystyle \frac{{\displaystyle {\int }_{t_1}^{t_3}{V}_{\mathrm{AC}}(t)dt}}{t_3-t_1}}.$$

(8)

The primary current at the end of the resonant stage is as follows:

$$i_{\mathrm{p}}(t_3)={\displaystyle \frac{V_{\mathrm{in}}-6V_{\mathrm{AC}.\mathrm{eq}}}{L_{\mathrm{r}}}}\ast \left(t_3-t_1\right)+i_{\mathrm{p}}(t_1).$$

(9)

The duration of the mode is related to the duty cycle of the phase-shifted full-bridge converter and the dead time of the bridge arm. The expression is as follows:

$$t_{23}=d{T}_s-t_d,d\in \left(\mathrm{0,0.5}\right).$$

(10)

5.

Mode 4 (t₃–t₄): This stage is the stage of turning on the ZVS of the leading bridge arm and zeroing the current. Figure 9 shows the equivalent circuit. At moment t₃, Q₄ turns off, and the original primary current flowing through Q₄ is transferred to parasitic capacitors C₃ and C₄, discharging C₃ and charging C₄ simultaneously. Due to the short charging and discharging time and the fact that the resonant inductor is connected to the secondary output inductor L_out1 and the clamp capacitors AC through the transformer, it can be thought of as a constant current source. After the charge–discharge process is completed, D₃ naturally conducts, thus clamping the voltage across Q₃ at zero. The time required for the whole charge–discharge process is calculated as follows:

$$t_{lead}={\displaystyle \frac{2C{V}_{in}}{i_{Lout1}(t_3)-i_{ac}(t_3)}}.$$

(11)

The ZVS of the leading bridge arm should meet the charging and discharging time of the advance bridge arm whose dead-zone time is greater than C₃ and C₄:

$$t_{\mathrm{lead}}={\displaystyle \frac{2C{V}_{\mathrm{in}}}{i_{\mathrm{Lout}1}(t_3)-i_{\mathrm{ac}}(t_3)}}.$$

(12)

This time is the time when the falling edge of the clamp tube lags behind the falling edge of the switch tube of the overfront bridge arm, which is determined by the current in the circulation stage and is related to the load size and the working state of the circuit.

At this stage, Q_AC1 remains switched on, and under the voltage of the clamp capacitor, the resonant inductor current decreases in a linear manner.

6.

Mode 5 (t₄–t₅): The equivalent circuit diagram is shown in Figure 10. Switch tube Q3 is turned on at moment of t₄, and the leading bridge arm’s ZVS can be achieved because the voltage at both ends of Q₃ is zero. At this point, the current on the primary side is transferred from the body diode D₃ to Q₃, and the working state of the other devices is unchanged. The clamp capacitor is connected to the primary resonant inductor through the transformer, and the voltage of the clamp capacitor is applied across the resonant inductor so that the primary current is rapidly reduced to zero. The time required for the current return to zero depends on how long the clamp tube Q_AC1 remains on after the switching tube Q₄ is turned off. The expression is as follows:

$$t_{off\_delay}=t_5-t_3={\displaystyle \frac{i_p(t_3)}{k}}={\displaystyle \frac{L_{\mathrm{r}}{i}_p(t_3)}{6V_{AC}(t_3)}}.$$

(13)

This time is the time when the falling edge of the clamp tube lags behind the falling edge of the switching tube of the leading bridge arm, which is determined by the current in the circulation stage and is related to the load size and the working state of the circuit.

7.

Mode 6 (t₅–t₆): This stage is the circulating current stage. Figure 11 shows the equivalent circuit. At moment t₅, the primary current drops to zero, and Q_AC1 needs to be turned off in time to prevent the current from growing in the reverse direction. Although the primary side switch tubes Q₁ and Q₃ remain on at this stage, the primary current is reduced to zero, and no current flows through Q₁ and Q₃, resulting in no circulation on the primary side and significantly reducing the primary loss during the on state. The two synchronous rectifier tubes Q_SR1 and Q_SR2 are switched on at the same time, the transformer is short-circuited, the voltage at both ends of the transformer drops to zero, and the original secondary side is decoupled. In addition, the secondary winding of the transformer carries no current, and the synchronous rectifier tubes Q_SR1 and Q_SR2 provide a continuous current path for the output inductance L_out1 and L_out2, respectively, to share the output current. In contrast to the traditional phase-shifted full-bridge mode of continuous flow only through a single rectifier tube, the RMS (Root Mean Square) current and on-state loss in the synchronous rectifier switching tubes are significantly reduced. The on-state loss on both the primary and secondary sides has been effectively reduced.

4. Principle of Operation and Characteristics

4.1. Lagging Bridge Arm ZVS

Under conditions of no load or light load, the traditional phase-shifted full-bridge lagging bridge arm switching tubes are short-circuited due to the transformer secondary side, and the energy required to realize ZVS is only provided by the resonant inductor. However, because the resonant inductance is significantly smaller than the output inductance converted to the primary side, it is difficult to fully implement the ZVS.

The active clamp phase-shifted full-bridge topology with improved control scheme realizes fine control of the resonant processes of L_r and the junction capacitor by precisely adjusting the on and off timing of the clamped switching tubes, thus ensuring the lagging bridge arm’s ZVS.

When Q_AC1 is switched on, the secondary clamp capacitor is connected to both ends of the transformer’s secondary side, which can be regarded as the clamp capacitor directly acting on the transformer’s primary side. Since the switching processes of the lagging bridge switching tubes are very short, the clamp capacitor can be regarded as a constant voltage source whose amplitude is close to the input voltage after converting to the primary side.

By controlling the turning on and turning off of the two switching tubes, the clamp capacitor energy can be transferred to the primary side under the action of the transformer and injected into node A or node B in the form of current to provide energy for the charge–discharge of the lagging bridge arm’s parasitic capacitor, resulting in a ZVS with a wide range of loads. The energy released by the clamp capacitor is split into two parts: One part is fed back into the load and flows into the output inductor L_out1 in the form of current to provide a continuous current for the circuit and bear the output current that should flow through the cutoff Q_SR1. The other part of the current is returned to the original side, which is used to charge and discharge the parasitic capacitors C₁ and C₂, so as to realize the lagging bridge switch tube Q₁’s ZVS. The charge–discharge process of C₁ and C₂ is actually the resonance process with the resonant inductor L_r, which requires enough time to reduce the junction capacitor voltage to zero before turning on the switch tube, and the charge and discharge time is one-quarter of the resonant period. The expression is as follows:

$$t_1-t_0={\displaystyle \frac{\pi }{2}}\sqrt{2L_{\mathrm{r}}C}.$$

(14)

It can be seen from the expression that this time is determined by the converter parameters and has nothing to do with the load size. After the circuit enters the steady state, due to the presence of the internal body diode of the clamped switching tube, a large voltage value will be maintained on the capacitor, which is related to the input voltage V_in and the transformer ratio n. Moreover, due to the large capacitance of the clamp capacitor, the amplitude of the voltage does not change much when the clamp capacitor exchanges energy. In addition, the active clamp circuit does not impact the voltage gain of the converter, which is only determined by the transformer ratio and duty cycle, just like the traditional phase-shifted full-bridge converter. The switching of the clamped switching tube Q_AC1 will make the synchronous rectifier tube Q_SR1 stop, and the voltage at both ends of Q_SR1 is clamped, thus avoiding the problem of secondary-side voltage oscillation in the traditional phase-shifted full-bridge converter.

4.2. Low On-State Loss

In the traditional phase-shifted full-bridge converter circulation phase, only one rectifier is in the on state, which means that the rectifier must carry all the output current by itself, resulting in significant on-state loss. The two sides of the transformer work independently, the primary switching tube Q₄ and the body diode D₂ are in the on state, and the secondary side’s output current is continued through the output inductance and the rectifier diode.

The improved active clamp phase-shifted full-bridge circuit precisely controls the drive timing of the fully controlled switch and reduces the primary current to zero by using the voltage on the clamp capacitor. When either clamped switching tube Q_AC1 or Q_AC2 is on, the clamp capacitor will be directly connected to the transformer’s secondary side. Under the effect of capacitor voltage, the current i_p in the resonant inductor will be rapidly reduced, and the decline rate is determined by the capacitor voltage and the resonant inductor L_r. After the current i_p in the resonant inductor is reduced to zero with the slope of V_C/L_r, timely shutdown of the fully controlled switching tubes Q_AC1 or Q_AC2 prevents the primary current from increasing in the opposite direction and keeps the current in the zero-current state with the lowest on-state loss, thus significantly reducing the on-state loss.

By reducing the primary side’s current to zero, the decoupling of the two sides is realized in the improved control of the active clamp full bridge. In this way, the two synchronous rectifiers on the secondary side can bear the current of the corresponding output inductance, which helps to reduce the burden of a single rectifier and reduce the overall on–off loss. Figure 12 shows the schematic diagram of the two synchronous rectifiers sharing the output current.

With the same output current, the loss flowing through a synchronous rectifier tube is as follows:

$$p_{\mathrm{con}1}={(i_{\mathrm{Lout}1}+i_{\mathrm{Lout}2})}^2{R}_{\mathrm{ds}\_\mathrm{on}}.$$

(15)

With the same output current, the loss flowing through the two synchronous rectifier tubes is as follows:

$$p_{\mathrm{con}2}=i_{\mathrm{Lout}1}^2{R}_{\mathrm{ds}\_\mathrm{on}}+i_{\mathrm{Lout}2}^2{R}_{\mathrm{ds}\_\mathrm{on}}.$$

(16)

By comparing Equation (15) with Equation (16), the above formula can be presented as follows:

$${(i_{Lout1}+i_{Lout2})}^2{R}_{ds\_on}>(i_{Lout1}^2+i_{Lout2}^2)R_{ds\_on},$$

(17)

and

$$p_{\mathrm{con}1}>p_{\mathrm{con}2}$$

(18)

As can be seen from Equation (17), the purpose of reducing transmission loss can be achieved by diverting the current, and the effect of reducing the loss increases with the increase in load.

5. Test Result

To verify the accuracy and effectiveness of the proposed control strategy, a 2.5 kW test prototype was manufactured. The prototype parameters are as follows: Primary GaN MOSFET, GS66508T; secondary rectifier MOSFET, IPT026N10N5; switching frequency, 450 kHz; secondary-side clamp MOSFET, BSC0802LS; transformer core material, JNP50; transformer ratio, 6:1; V_in = 200 V~470 V; L_r = 1.2 μH; AC = 470 nF. The experimental platform built in this paper is shown in Figure 13, and the main power board and control board of the converter are shown in Figure 14. The inductor and transformer core use a flat magnetic component, the transformer winding is directly coated with copper on the PCB board, which is integrated into the motherboard, and the transformer and the output inductor are magnetically integrated.

5.1. ZVS Waveform Analysis

Figure 15 shows the grid drive signal waveform from Q₁ to Q₄ of the primary-side switch tube under the condition of V_in = 250 V, d = 0.7. It can be seen that Q₁ and Q₂ of the lagging bridge arm and Q₃ and Q₄ of the leading bridge arm all adopt the 180° complementary conduction mode with dead-zone protection. The switching frequency is 450 kHz and the dead time is 70 ns, which is about 3% of the switching cycle. The switch tubes Q₃ and Q₄ of the leading bridge arm are used for phase-shift control, which is 333 ns ahead of the lagging bridge arm.

Figure 16 and Figure 17 show the experimental waveforms for V_in = 250 V, d = 0.7, V_o = 14.4 V, and I_out = 10 A. As can be seen from Figure 16, when the switching tube Q₄ of the leading bridge arm is turned off, the current on the primary side reaches the maximum value in each cycle. The current charges and discharges the parasitic capacitors C₃ and C₄, and the voltage at both ends of Q₄ decreases accordingly. Before the drive signal arrives, this voltage has been reduced to zero, thus achieving the ZVS. The waveform shows that the ZVS can be realized under the load condition of 10 A, which is similar to the traditional phase-shifting full bridge, and the ZVS of the advanced bridge is easier to realize. As can be seen from Figure 16, it is evident that before the driving signal of Q₂ arises, the primary current is zero. To achieve Q₂’s ZVS, the clamped switching tube Q_AC2 is switched on and the primary-side resonant inductor begins to resonate with the parasitic capacitors C₁ and C₂. The primary current increases rapidly in the positive direction and the parasitic capacitor C₂ of Q₂ discharges. During this process, the primary-side current provides energy for the primary-side lagging switching tube Q₂ to realize ZVS turn-on, and the voltage at the ends of Q₂ rapidly decreases to zero. At this time, the Q₂ drive signal arrives and ZVS turn-on is realized. The results show that soft switching can be realized in the lagging bridge arm at an output current of 10 A, which is consistent with the theoretical analysis that the lagging bridge arm switching tubes’ ZVS does not depend on the magnitude of the load current. In addition, it can be seen from the comparison of the two figures that it is more difficult to achieve the ZVS of the leading bridge arm compared to the lagging bridge arm. The main reason is that when the load current is too small, the energy in the resonant inductor available to the ZVS of the leading bridge arm is less.

Figure 18 shows the ZVS realization of the leading and lagging bridge arms under the conditions of V_in = 250 V, d = 0.7, V_o = 14.4 V, and I_out = 100 A. V_{gs_Q4} is the grid source voltage waveform of the switching tube Q₄, V_{ds_Q4} is the drain source voltage waveform of the switching tube Q₄, and i_p is the current waveform in the primary resonant inductor.

It can be seen from the figures that the ZVS of both the leading and lagging bridge arms has been realized. In addition, by comparing Figure 18 and Figure 19, it can be seen that although both the leading and lagging bridge switch tubes achieve the ZVS, the voltage reduction rate at both ends of the lagging bridge switch tubes is significantly slower than that of the overfront bridge switch tubes. This means that it is more difficult to achieve the lagging bridge arm’s ZVS compared to the leading bridge arm. The reason for this phenomenon is that with the increase in load, more energy is available in the resonant inductor of the advanced bridge arm’s ZVS, so it is easier to achieve the ZVS.

5.2. On-State Loss Analysis

Figure 20 shows the experimental waveforms at V_in = 250 V, d = 0.7, V_o = 14.4 V, I_out = 100 A, and I_out = 170 A under the condition of the rectifier tube being synchronized in the circulation stage. V_{gs_SR1} is the gate source voltage waveform of the switching tube Q_SR1, V_{gs_SR2} is the gate source voltage waveform of the switching tube Q_SR2, and i_p is the current waveform in the primary resonant inductor.

As can be seen from Figure 20, as the primary-side current gradually decreases to zero under the action of the clamping capacitor, the converter smoothly enters the circulation stage. At this stage, the on-state loss of the primary edge is almost zero. At the same time, two synchronous rectifier tubes Q_SR1 and Q_SR2 are in the on state, providing continuous current for the output inductors L_out1 and L_out2. Compared with the case of a single rectifier tube, this double-tube on-state mode significantly reduces the on-state loss of the secondary side, thus improving the overall efficiency of the converter.

By comparing Figure 20a,b, it can be seen that when the load current increases from 100 A to 170 A, the current on the primary side also increases, and the time required for the current to return to zero is correspondingly extended, resulting in the simultaneous on-state time of the two synchronous rectifier tubes; that is, the duration of the circulation stage is shortened.

Figure 21 shows the experimental waveforms at V_in = 350 V, d = 0.5, V_o = 14.4 V, I_out = 100 A, and I_out = 170 A. V_{gs_SR1} is the gate source voltage waveform of switching tube Q_SR1, V_{gs_SR2} is the gate source voltage waveform of switching tube Q_SR2, and i_p is the waveform of the current in the primary-side resonant inductor.

As the primary-side current gradually decreases to zero under the effect of the clamp capacitor, the converter enters the circulation phase smoothly. At this stage, the on-state loss of the primary edge is almost zero. At the same time, the two synchronous rectifier tubes Q_SR1 and Q_SR2 on the secondary side are in the on state, providing a continuous current for the output inductors L_out1 and L_out2, respectively. Compared with the case of a single rectifier tube, this double-tube on-state mode significantly reduces the on-state loss of the secondary side. As the input voltage increases from 250 V to 350 V, to keep the output voltage constant, the phase-shift angle between the leading and lagging bridge arms becomes larger and the duty cycle consequently reduces, which in turn leads to an increase in the duration of the circulating phase, thus improving the overall efficiency of the converter.

5.3. Efficiency Curve

Figure 22 shows the efficiency curve of the converter. The experiment tests the working efficiency of the output current from 10 A to 170 A under an input voltage of 250 V and 350 V.

It can be seen that with the increase in power, the efficiency of the power supply also increases and reaches the highest efficiency near 50% load. As the power continues to increase, the temperature of the converter increases, the thermal effect causes the line impedance to rise, and the on-state loss increases accordingly, so the efficiency decreases. In addition, the efficiency of the converter at a 250 V input voltage is higher than that at a 350 V input voltage. This is because after the input voltage increases, the on-state loss, transformer loss, and capacitive loss of the circuit increase, resulting in reduced efficiency. At an input voltage of 250 V and 350 V, the maximum efficiency is 92.8% and 92.1%, respectively.

6. Conclusions

In this paper, an improved active clamp phase-shifted full-bridge converter is proposed and compared with the traditional phase-shifted full-bridge converter. The secondary-side rectifier circuit is replaced by a double-current rectifier circuit. In addition, an appropriate dead-time compensation strategy can reduce the influence of dead time on switching devices and improve the performance of a ZVS. Compared with the full-wave rectifier circuit, the double-current rectifier circuit is more suitable for low-voltage and high-current output application scenarios, thus effectively improving the overall performance of the circuit. Secondly, according to the principle of current enhancement, an active clamp circuit is introduced in the secondary side. Not only does this design use the energy in the clamp capacitor to provide the energy needed for the ZVS’ s implementation, so as to solve the problem that of the ZVS being difficult to realize, but also the clamp circuit itself can stabilize the voltage, so as to effectively suppress the oscillation of the secondary voltage. Finally, by cleverly using the clamp capacitor voltage in the active clamp circuit and precisely controlling the timing of the clamp switching tube, the primary current is successfully zeroed, which not only significantly reduces the circulation loss but also solves the problem of duty cycle loss. The experimental results show that this scheme has realized the ZVS of the lagging bridge arm under a light load; during the loop current stage, the primary current is zero, and the two synchronous rectifier tubes are reliably conducting to share the output current together. The primary and secondary on-state losses are reduced. This scheme is suitable for application scenarios with a wide input voltage range and a high current output and overcomes the shortcomings of the traditional phase-shifted full-bridge secondary-voltage oscillation and duty cycle loss, improving the efficiency and power density of the converter.