A 4T1C Pixel Circuit with Threshold Voltage Compensation for Organic Light-Emitting Diode on Silicon Microdisplays

Abstract

In this paper, a pixel circuit consists of four MOSFETs and one capacitor is proposed for Organic Light-Emitting Diode on Silicon (OLEDoS) microdisplays. The proposed pixel circuit enhances luminance uniformity by compensating for the threshold voltage variation of the driving transistors by the capacitive coupling effect. Even with a threshold voltage variation of ±20 mV, the HSPICE simulation results reveal that the driving current offset stays between −0.89 and 0.70 LSB, which is more than seven times smaller than that of the conventional 2T1C pixel circuit. Additionally, a two-stage DAC driving scheme has been utilized to achieve 256 gray levels, aiming to reduce the accuracy requirements for the DAC circuit. The proposed pixel circuit demonstrates significant potential in high-performance OLEDoS microdisplay applications.

1. Introduction

In recent years, augmented reality (AR) and virtual reality (VR) have gained considerable attention across various fields, including entertainment, industry, and education [1,2,3]. VR creates fully immersive, simulated environments, while AR enhances the real world by overlaying digital content. Both technologies aim to change the way we perceive and interact with the world. Microdisplays, such as liquid crystal on silicon (LCoS) [4], the digital micromirror device (DMD) [5], and Organic Light-Emitting Diode on Silicon (OLEDoS) [6], serve as critical image-source components in AR/VR devices. Due to their self-emissive characteristic, OLEDoS microdisplays offer superior contrast ratios, wider viewing angles, and faster response times compared to LCoS. Therefore, OLED materials and the silicon-based backplane for OLEDoS have been extensively researched and developed. The luminance of an OLEDoS microdisplay is directly proportional to the driving current applied to the pixels at each grayscale level. Therefore, to produce high-quality images, pixel circuits implemented on the CMOS backplane must deliver a stable and uniform emission current. A conventional 2T1C (2 Transistors and 1 Capacitors) pixel circuit comprises a driving transistor ($M_1$), a switching transistor ($M_2$), and a coupling capacitor ($C_s$). $C_s$ maintains the gate voltage of $M_1$ throughout a frame duration. The driving transistor generates the driving current according to its gate-to-source voltage ($V_{gs}$) and threshold voltage ($V_{th}$). However, CMOS transistors are inherently prone to $V_{th}$ variations due to the physical properties of the transistors and the semiconductor fabrication process, such as bias temperature instability [7], hot carrier stress [8], and time-dependent defects [9]. As a result, the 2T1C pixel circuit has the simplest circuit structure, but it cannot effectively compensate for the $V_{th}$ variation in the driving transistor. This variation becomes a primary factor affecting the luminance uniformity [10,11] of the OLEDoS microdisplays. It is necessary to compensate for the $V_{th}$ variation of driving transistors to improve the luminance uniformity.

$V_{th}$ compensation schemes are generally classified into internal and external categories. External compensation schemes [12,13,14] generally feature simple pixel structures but rely on complex external driving circuits. They require a large area and exhibit a prolonged non-emissive phase, which limits their suitability for high-resolution, high-refresh-rate microdisplays. In contrast, internal compensation focuses on ensuring that the driving current is independent of $V_{th}$. Common techniques for $V_{th}$ compensation include the diode-connection method [15] and the capacitive coupling effect [16]. The diode connection method operates the MOSFET in the saturation region, allowing the storage capacitor to discharge through the MOSFET until the gate-to-source voltage equals the $V_{th}$, thereby extracting $V_{th}$. On the other hand, the capacitive coupling effect leverages the principle that the voltage across a capacitor cannot change abruptly. By controlling the voltage at one node of the storage capacitor, the voltage at another suspended node is adjusted, coupling the $V_{th}$ to the corresponding node. Several internal compensation OLEDoS pixel circuits have been developed to address pixel current mismatches and ensure luminance uniformity. Keum et al. [17] proposed a 7T2C pixel circuit that provides a uniform voltage delivery to the OLED, which makes the emission current independent of $V_{th}$ variations and subthreshold slop. Liu et al. [18] employed an 8T1C pixel circuit and a compensation scheme to significantly expand the input data voltage range and reduce emission current deviation. Kwak et al. [19] introduced a 5T1C pixel circuit employing a source follower with a diode-connected transistor as an active load, which effectively minimizes the electrical characteristic variations such as anode voltage and native oxide thickness on aluminum electrodes. Another 5T1C pixel circuit designed by Lee et al. [20] uses control signals instead of public high levels to reduce the impact of I-R drop on current stability while also incorporating $V_{th}$ compensation, thereby achieving current emission stability. However, previous pixel circuit designs often feature relatively complex structures with more than four transistors, which increases the die areal size, thereby increasing the power consumption and shortening the lifetime of the OLED and of the microdisplay devices. Achieving $V_{th}$ compensation and a tunable emission current in a compact pixel circuit remains a significant challenge.

In this work, a 4T1C pixel circuit for the OLEDoS microdisplay is proposed to compensate for $V_{th}$ variations. The circuit extracts and stores the $V_{th}$ of the transistors in the capacitor, reducing the impact of $V_{th}$ variation on the driving current through the capacitive coupling effect. Even with $V_{th}$ variations ranging from −20 mV to +20 mV, the HSPICE simulation results reveal that the driving current offset stays between −0.89 and 0.70 LSB, which is more than seven times smaller than that of the conventional 2T1C pixel circuit. Furthermore, a two-stage Digital-to-Analog Converter (DAC) driving scheme has been utilized to achieve 256 gray levels, aiming to reduce the accuracy requirements for the DAC circuit.

2. Proposed 4T1C OLEDoS Pixel Circuit and Driving Scheme

Figure 1a,b illustrate the circuit schematic and corresponding timing diagrams of the proposed pixel circuit, respectively. The proposed pixel circuit consists of 4 p-channel MOSFETs ($M_0$, $M_1$, $M_2$, and $M_3$) and 1 storage capacitor ($C_s$). The 4T1C pixel circuit is controlled by five signals: CTR1, CTR2, SCAN, DATA_L, and DATA_H. The CTR1 and CTR2 are periodic pulse signals with voltage levels ranging from GND to VDD. During the initialization phase and threshold voltage storing phase, the SCAN signal is a negative voltage lower than the $V_{th}$ of transistor $M_1$, supplied and tuned by an external regulator, ensuring that $V_b$ is fully discharged to 0 V. To optimize the die area, a two-stage DAC driving scheme is employed to achieve 8-bit 256 levels of grayscale. The voltage range of the DATA_L signal spans from $V_{DL}$ to VDD, and the voltage range of the DATA_H spans from GND to $V_{DH}$. The $V_{DH}$ signal carries high-order 3-bit display data, and $V_{DL}$ carries low-order 5-bit display data. $V_{DH}$ and $V_{DL}$ signals are generated by an external two-stage DAC circuit (3-bit and 5-bit), which offers several advantages over a single 8-bit DAC for peripheral driving circuits in terms of optimized die area, reduced power consumption, and easier scaling for higher resolution [21,22].

Figure 2 illustrates the three operation phases of the proposed pixel circuit, which are described below, and the operating regions of the MOSFETs in each phase are outlined in

Table 1. Operating regions of MOSFETs in different phases of the proposed 4T1C pixel circuit.

Initialization Phase		Threshold Voltage Storing Phase		Compensation and Emission Phase
MOSFET	Operating Region	MOSFET	Operating Region	MOSFET	Operating Region
$M_0$	Linear	$M_0$	Cutoff	$M_0$	Linear
$M_1$	Linear	$M_1$	Linear	$M_1$	Cutoff
$M_2$	Cutoff	$M_2$	Saturation	$M_2$	Cutoff
$M_3$	Cutoff	$M_3$	Cutoff	$M_3$	Saturation

.

(1) Initialization phase: During the initialization phase, as shown in Figure 2a, the control signals SCAN and CTR1 are set low, turning on transistors $M_0$ and $M_1$. Simultaneously, DATA_L and CTR2 are set high, while DATA_H remains low, keeping $M_2$ and $M_3$ off and preventing current from flowing through the OLED. Consequently, the voltage across $C_s$ is corrected by resetting the voltage at nodes A and B to the reference potential of VDD and GND, respectively. This step eliminates the effects of voltage fluctuations from the previous frame, thereby enhancing the accuracy of subsequent $V_{th}$ compensation. Furthermore, this phase is non-emissive, ensuring the OLED remains off to prevent reduced image contrast caused by transistor leakage currents.

(2) Threshold voltage storing phase: As shown in Figure 2b, DATA_H, SCAN, and CTR2 are set low, while CTR1 is set high, turning off $M_0$ and keeping $M_3$ inactive. DATA_L is pulled down to $V_{DL}$, activating $M_2$, while $M_1$ remains on, as in the initialization phase. Consequently, the voltage across $C_s$ is discharged through node A and $M_2$ to the voltage of $V_{DL}$ + $\left|V_{th2}\right|$, where $V_{th2}$ is the threshold voltage of $M_2$. The voltage at node B remains at GND, and the voltages at nodes A can be determined by Equation (1).

$$V_A=V_{DL}+\left|V_{th2}\right|>0$$

(1)

It is obvious that $V_A$ includes the threshold voltage |$V_{th2}$| in the expression, indicating that the 4T1C circuit performs threshold voltage extraction during this phase.

(3) Compensation and emission phase: In the final phase, CTR1 is pulled low to turn on $M_0$, while SCAN and DATA_L are set to VDD, turning off $M_1$, $M_2$ and disconnecting node B from GND. At this point, the voltage at node A returns to VDD. Due to the capacitive coupling effect, the voltage at node B is altered as described by Equation (2):

$$V_B=VDD-V_{DL}-\left|V_{th2}\right|$$

(2)

Since node B is directly connected to the gate of $M_3$, $V_B$ also serves as the gate voltage for $M_3$. The source of $M_3$ is connected to DATA_H, which is pulled up to $V_{DH}$. For $M_3$, the $V_{gs}$ is given by Equation (3):

$$V_{gs}=VDD-V_{DL}-\left|V_{th2}\right|-V_{DH}<0$$

(3)

The condition for $M_3$ can be expressed as:

$$\left|V_{gs}\right|-\left|V_{th3}\right|\le \left|V_{ds}\right|$$

(4)

By combining Equations (3) and (4), the following can be obtained:

$$V_{DH}-VDD+V_{DL}+{|V}_{th2}|-{|V}_{th3}|\le {|V}_{ds}|$$

(5)

Assuming the transistor manufacturing process of transistors is identical and the source positions of $M_2$ and $M_3$ are close in layout design, their electrical characteristics, including $V_{th}$, can be considered as identical [23]; thus, Equation (6) can be written as:

$$V_{DH}-VDD+V_{DL}\le {|V}_{ds}|$$

(6)

Under these conditions, $M_3$ operates in the saturation region, allowing its saturated leakage current flows through the OLED, as shown in Figure 2c. This current represents the driving current of the 4T1C pixel circuit, which can be expressed as Equation (7):

$$\begin{gathered} I_{oled}={\displaystyle \frac{1}{2}}·k·{\left(\left|V_{gs}\right|-\left|V_{th}\right|\right)}^2 \\ ={\displaystyle \frac{1}{2}}·k·{\left(V_{DH}-VDD+V_{DL}\right)}^2 \end{gathered}$$

(7)

where $k=$ $\mu C_{OX}{W}_{M3}/L_{M3}$. Based on Equation (7), the driving current is independent of the $V_{th}$, effectively eliminating the impact of the $V_{th}$ variation on the driving current.

3. Simulation Results and Discussion

HSPICE simulations with a 0.18 μm standard CMOS process were conducted to evaluate the compensation performance of the proposed 4T1C pixel circuit. The simulation parameters are summarized in

Table 2. Design parameters of the proposed pixel circuit.

Parameter	Value
Process	0.18 μm standard CMOS process with 6 V voltage devices
VDD (V)	5
GND (V)	0
$V_{DL}$ (V)	−0.55~−1.1
$V_{DH}$ (V)	5~6
$(\mathrm{W}/\mathrm{L}) \mathrm{of} M_2$ $\mathrm{and} M_3$ (μm)	0.5/4
$V_{th}$ $\mathrm{of} M_2$ $\mathrm{and} M_3$ (V)	−1.89
$(\mathrm{W}/\mathrm{L}) \mathrm{of} M_0$ $\mathrm{and} M_1$ (μm)	0.5/0.5
$V_{th}$ $\mathrm{of} M_0$ $\mathrm{and} M_1$ (V)	−1.5
$\mathrm{Capacitance} \mathrm{of} C_S$ (fF)	30

. Figure 3a illustrates the voltage and driving current at each node in the 4T1C pixel circuit under the condition of $V_{DH}$ = 5 V and $V_{DL}$ = −0.8 V. Intervals (1), (2), and (3) in this figure correspond to the initialization phase, threshold voltage storing phase, and compensation and emission phase, respectively. During the initialization phase, DATA_L and CTR2 are held high at 5 V, while DATA_H and CTR1 are set low at 0 V. The voltage at node A drops to 1.080 V due to capacitive discharge in the threshold voltage storing phase. Both phases are non-emissive, and their durations are determined by storage capacitance, operating voltage, device process parameters, and refresh rate. Moreover, because the duration time of these two intervals falls within human visual response times [24], the non-emissive phases does not significantly affect image quality. Finally, during the compensation and emission phase, $V_A$ rises to 5 V, while $V_B$ increases to 3.921 V due to the capacitive coupling effect, and the driving current reaches 103.56 pA.

As shown in Equation (7), since VDD represents the high-level voltage and can be considered constant, the driving current is directly influenced by $V_{DH}$ and $V_{DL}$. According to Equation (1), the variation of $V_{DL}$ is constrained by $V_{th2}$ to ensure $V_A>0$, while $V_{DH}$ can be slightly higher than the process voltage without causing a transistor breakdown. Therefore, using a two-stage DAC to supply $V_{DH}$ and $V_{DL}$ signals carrying display data can achieve multiple grayscale levels without excessive requirements for the high-resolution DAC. As shown in Figure 3b, under the same conditions but with $V_{DL}$ = −1 V, $V_B$ rises to 4.119 V during the compensation and emission phase. This demonstrates that the voltage at node B varies with the display data, with an error rate of approximately 0.1%, indicating that the 4T1C pixel circuit could track the changes in display data. Furthermore, as shown in Figure 3c, when $V_{DL}$ remains the same, if $V_{DH}$ rises from 5 V to 6 V, the driving current at the maximum gray level increases to 1463.8 pA, indicating that the 4T1C pixel circuit could achieve higher luminance.

The least significant bit (LSB) is commonly used to evaluate the smallest current difference that the device can output. A smaller LSB indicates that the device can produce finer analog outputs with minimal error. If the deviation keeps within ±1 LSB, any emission current error caused by the $V_{th}$ variation will not affect the display grayscale levels [25]. Figure 4a illustrates the relationship between driving current error and display grayscale for the 4T1C and 2T1C pixel circuits, respectively. Due to factors such as different process and temperature, the $V_{th}$ variations are typically within 20 mV [26,27]. In the 4T1C pixel circuit, the driving current remains stable, and the resulting image closely matches that of a circuit without such variations. Over the entire grayscale range, the driving current error stays between −0.89 and +0.70 LSB, which is more than seven times smaller than that of the traditional 2T1C pixel circuit. Additionally, as shown in Figure 4b, the relationship between driving current and grayscale follows a smooth S-shaped curve, which is beneficial for the design of image processing modules in microdisplays, such as gamma correction [28].

Manufacturing process variations often cause fluctuations in the current-to-voltage characteristics of CMOS transistors, which can lead to inconsistencies across pixels. To evaluate the performance of the proposed 4T1C pixel circuit under these variations, Gaussian statistical distribution was applied to model all process parameters, and Monte Carlo simulations were performed. Figure 5a,b illustrate the Monte Carlo simulation results for output current error with 1000 sampling iterations, corresponding to low grayscale current (10 pA) and high grayscale current (1 nA), respectively. For a low grayscale current, the coefficient of variation is 12.6%, whereas for a high grayscale current, the coefficient of variation is 5.6%. These results demonstrate that the proposed 4T1C pixel circuit exhibits strong resilience to process variations.

The layout of the proposed pixel circuit occupies an area of 9 μm × 3.08 μm, corresponding to a resolution of 2670 pixels per inch (ppi), as shown in Figure 6. Metal 1 (M1) and Metal 2 (M2) layers are used for interconnecting wires. The capacitor is implemented with the metal–insulator–metal (MIM) capacitor using metal layers Metal 3 (M3) and Metal 4 (M4). Metal 5 (M5) layer serves as the anode of OLED. A comprehensive comparison of the features of several previously reported microdisplay pixel circuits is provided in

Table 3. Comparisons between the proposed 4T1C pixel circuit and other works.

Reference	[29]	[30]	[31]	[32]	[15]	This Work
Pixel Components	2T1C	4T1C	2T1C	4T1C	4T1C	4T1C
CMOS Process	0.35 μm with 3.3 V device	0.18 μm with 4.5 V device	N/A	90 nm with 6 V device	110 nm with 5.5 V device	0.18 μm with 6 V device
Pixel Area (μm × μm)	12.6 × 4.2	12 × 4	11.8 × 5.9	9 × 3	5.76 × 1.92	9 × 3.08
DATA Voltage Range (V)	1.6~3.2	0.4~3.001	N/A	3.2~4.5	0~1.4	−0.55~−1.1 and 5~6
$V_{th}$ Compensation	Without compensation	With compensation	With compensation	With compensation	With compensation	With compensation
Spatial Resolution (PPI)	2016	2016	2153	2822	4410	2670
Color Depth (bit)	6	8	6	8	8	8
Minimum Grayscale Interval (mV/step)	25	10.1	N/A	5.1	5.5	17.2

. Among pixel circuits fabricated using 0.18 μm technology or processes with wider line widths, the proposed circuit in this work exhibits a relatively smaller size. Additionally, the proposed pixel circuit reduces the emission current errors caused by $V_{th}$ variations. The wide DATA voltage range (−0.55 to −1.1 V and 5 to 6 V), combined with a two-stage DAC driving scheme, offers greater design flexibility. The data voltage $V_{DL}$, corresponding to low-order 5-bit display data, generates the minimum grayscale interval of 17.2 mV/step, which reduces DAC precision requirements and expands the range of gray-level tuning.

4. Conclusions

A 4T1C pixel circuit for an OLEDoS microdisplay is proposed to compensate for $V_{th}$ variations. According to HSPICE simulations, when the $V_{th}$ variation is from −20 mV to +20 mV, the offset of the driving current remains between −0.89 and +0.70 LSB during the emission phase, which is more than seven times smaller than that of the conventional 2T1C pixel circuit. Furthermore, a two-stage DAC driving scheme has been implemented for the pixel to achieve 256 gray levels, aiming to reduce the accuracy requirements for the DAC circuit. The 4T1C pixel circuit features a compact structure, minimized pixel emission current mismatches, and a two-stage DAC driving scheme, making it well-suited for high-performance OLEDoS microdisplay applications.