A 512 KBytes Highly Reliable and High-Speed Embedded NOR Flash Memory

Abstract

With the increasing requirements for chip data storage capabilities in fields such as automotive electronics and the Internet of Things, Flash memory is becoming more and more widely used. This paper presents a 512 KBytes Flash memory array with high reliability, high-speed reading, and high noise immunity. By regarding one bit of the dual-bit NORD structure as a dummy bit, we simplify the operation mode and obtain a wider cell current window. Meanwhile, this paper minimized the influence of supply voltage fluctuation on the comparison between cell current and reference current through the optimization of the sense amplifier circuit. We tested whether this array depicts a high-endurance performance under 25 °C and 85 °C, as well as high-speed reading up to 18 ns. This enhanced Flash memory is expected to bring inspiration for achieving high reliability and endurance in the automotive field under harsh operating conditions.

1. Introduction

Flash memory is a type of electrically erasable programmable read-only memory (EEPROM), which mainly differs from conventional EEPROM through the erase operation conducted by Sector/Block as the basic unit instead of Byte. It combines the advantages of the simple structure and high density of previous EPROMs and the electrical erasability of EEPROM; therefore, Flash memory can achieve a high density, a low cost, and a high reliability. Since Fujio Masuoka of Toshiba presented his Flash memory invention in 1984 [1], various researchers and organizations throughout the world have devoted themselves to Flash memory technological innovations.

One of the key elements in Flash memory is the floating gate transistor [2]. Figure 1a shows the traditional structure of a Stack Gate NOR Flash cell. There are two polysilicon gates in this cell structure—the control gate and the floating gate. The floating gate is completely surrounded by an insulator; thus, it is electrically isolated from other nodes [3]. However, in practical applications, due to factors such as process fluctuations or oxide degradation, most of the threshold voltage distribution after the erasing process will be in the over-erase state [4,5]. That is, the opening voltage of this part of the device becomes too low or even negative, which will lead to an increase in leakage current on the same bit line in the Flash memory, causing read errors, increased power consumption, and other problems.

In order to solve the over-erase problem of Stack Gate Flash memory, Split Gate Flash memory was developed. SuperFlash memory cell technology has undergone significant advancements since its invention in 1989 by Bing Yeh [6], a co-founder of SST. The initial concept has evolved through several generations, enhancing cell scaling and performance while retaining key features such as the split gate structure, poly-to-poly Fowler–Nordheim (FN) tunneling erase, and source-side hot-channel electron (HCE) injection programming [7]. The first-generation SuperFlash (ESF1) cell has been used in stand-alone and embedded Flash memory products for over 20 years [8]. As shown in Figure 1b, the floating gate potential is mostly modulated by the voltage coupling from a highly doped drain, which provides a higher coupling ratio for programming. When the cell is under programming, the transistor channel is in saturation. The vertical field constructed by source-side injection (SSI) is favorable for electron injection, which contributes to the high programming efficiency of SST cells. The floating gate and select gate channels are separated by a source and drain, so the over-erase problem can be effectively prevented. However, since the program operation relies on the coupling of the source line (SL) and floating gate (FG), a large source junction is required to provide a sufficient overlap of the SL-FG, which goes against the scaling of the ESF1 cell.

The second-generation SuperFlash (ESF2) architecture shown in Figure 1c enables better scaling via self-aligned processing steps [9]. This self-aligned treatment allows for the scaling of the word line (WL) oxide and channel length, as the WL is decoupled from the high-voltage gate oxide. Adding SL polysilicon also increased SL-FG coupling, allowing the FG channel length to scale. It is reported that with 180 nm process nodes, there is a reduction of >40% in size compared to ESF1 [10]. Furthermore, the ESF2 cell introduced self-aligned processing steps in the formation of the floating gate, source line poly, and WL poly, reducing the number of masks required in the production of the Flash memory cell.

As Flash memory technology develops in the direction of higher integration, higher efficiency, and smaller area, the third-generation SuperFlash (ESF3) technology was born. As shown in Figure 1d, ESF3 introduced the coupling gate (CG) into the cell structure to control FG voltage and separate the erase gate (EG) from the WL to undertake the erase function compared to ESF2, allowing for a more aggressive scaling. In addition, the erase operation of ESF3 depends on the FN tunneling between FG and EG through a thinner dielectric [11], which differs from the sharp-tip requirement for the FG poly in previous SuperFlash cells. As a result, the thinner tunneling oxide not only improves the erase performance, but also enhances its endurance.

Figure 1. (a) Traditional structure of a Stack Gate NOR Flash cell, (b) illustration of the first-generation SuperFlash (ESF1) cell cross-section, (c) illustration of the second-generation SuperFlash (ESF2) cell cross-section, (d) illustration of the third-generation SuperFlash (ESF3) cell cross-section [10].

Figure 1. (a) Traditional structure of a Stack Gate NOR Flash cell, (b) illustration of the first-generation SuperFlash (ESF1) cell cross-section, (c) illustration of the second-generation SuperFlash (ESF2) cell cross-section, (d) illustration of the third-generation SuperFlash (ESF3) cell cross-section [10].

The NORD Flash cell used in this research, whose intellectual property rights belong to Shanghai Huahong Grace Semiconductor Manufacturing Corporation, Shanghai, China, is depicted in Figure 2b. Compared to an ESF3 cell, the NORD Flash cell has only one self-aligned select gate, which significantly reduces the number of photo layers and is beneficial in the further scaling of the Flash memory cell.

Figure 2. (a) Schematic diagram of the single-bit cell, (b) cross-section view of the NORD Flash cell [12], (c) read current distribution, (d) Flash array architecture based on enhanced Flash cell, (e) array top view of enhanced Flash cell.

Figure 2. (a) Schematic diagram of the single-bit cell, (b) cross-section view of the NORD Flash cell [12], (c) read current distribution, (d) Flash array architecture based on enhanced Flash cell, (e) array top view of enhanced Flash cell.

As one of the widely used nonvolatile memories, Flash memory has been extensively used as a key component of different applications such as electronic portable equipment and automotive electronics [13]. These developing application requirements for the Flash cell reflect in the concepts of fast read access, data memory endurance over the range of 500 K cycles, and a low power consumption [14]. Recent research has focused on robust reliability and high-speed applications [15,16,17]. Due to the scaling down of the memory cell and the advance of the semiconductor process node, the working voltage of the devices is degraded [18], as well as the cell current. As a result, the current window formed by the current differentiation between program status (“0” cell) and erase status (“1” cell) also reduces. A small “1” cell current will lead to a longer read access time and a poor program/erase cycle performance [19], while a narrower current window leads to a small read sense amplify window and weakens the data reliability.

To mitigate the problems above, this paper demonstrated an enhanced embedded Flash cell based on a virtual ground structure. Instead of the four kinds of current status (CELL00, CELL01, CELL10, and CELL11) [20] presented in conventional dual-bit cell NORD Flash structures, this enhanced Flash cell has only two statuses (CELL01 stands for “0” status, and CELL11 stands for “1” status), which effectively extend the current distribution window, thus significantly increasing the endurance cycle by 2,500,000 times. With the larger “1” status cell current brought forward by the enhanced Flash cell, the current sensing time will be shortened and the read speed will also be boosted to 18 ns under a normal 1.2 V supply voltage. At the same time, the enhanced Flash cell simplifies the operation voltage condition, which leads to a lower power consumption. Furthermore, we optimized the sense amplifier circuit to minimize the interference by supply voltage fluctuations on the read operation.

The remainder of this paper is organized as follows. Section 2 shows the implementation of the enhanced Flash memory architecture introduced in this paper and an optimized sense amplifier. Section 3 then presents the highly reliable and high-speed reading performance, as well as the corresponding measurement results. Conclusions are provided in Section 4.

2. Implementation of Enhanced Flash Architecture and Optimized Sense Amplifier

2.1. NORD Flash Cell Structure and Enhanced Flash Memory Array Architecture

Figure 2b illustrates the conventional dual-bit NORD Flash cell, which is made up of two control gates and floating gate structures (CG1-FG1 and CG2-FG2), as well as a shared select gate (SG) [21]. Each floating gate structure acts as an independent memory cell to store a single bit. Therefore, the whole NORD Flash cell has dual-bit functionality per cell. The operation conditions of this memory cell are summarized in

Table 1. Memory cell operation conditions of NORD Flash memory.

	Selected Bit(s)	Vwl	Vcg1	Vcg2	V(S)	V(D)	Time
read	bit 1	4	0	5	0	0.5
	bit 2	4	5	0	0.5	0
prog	bit 1	1.5	9	5.5	5	Vdp/Iprog	5 μs
	bit 2	1.5	5.5	9	Vdp/Iprog	5	5 μs
erase	2 bits	8.5	−8	−8	0	0	2 ms

.

By short-connecting these two control gates as shown in Figure 2a, there is only one FG used to store data, and the unused FG (labeled as “dummy bit” here) is always erased, so the whole cell has two states—CELL01 and CELL11. To address the poor program/erase cycle performance caused by a small “1” cell current, we always use CELL11, which has a larger cell current to refer to the erase status. The operating conditions are simplified in

Table 2. Memory cell operation conditions in this paper.

	Selected Bit(s)	Vwl	Vcg	V(S)	V(D)	Time
read	used bit	4	0	0	0.5
prog	used bit	1.5	9	5	Vdp/Iprog	5 μs
erase	2 bits	8.5	−8	0	0	2 ms

, since CGs always have the same voltage.

Compared to Table 1, the read operation in Table 2 only needs to charge/discharge the WL, which can greatly reduce the pump power consumption together with the sped up read. The simplified program voltage in Table 2 also makes the pump circuit design simpler.

According to Figure 2c, CELL11 has a larger current than CELL10, hence the cell current window can be widened by the enhanced Flash cell.

In this paper, a 32 K*144-bit Flash array is built based on the enhanced Flash cell; it was fabricated with 55 nm 4-poly 4-metal CMOS technology. Cells in the same column are controlled by two adjacent bit lines, and cells in the same row share the same word line and control gate line. Figure 2d,e show the equivalent circuit and the top view of the enhanced Flash cell array architecture, respectively.

Figure 3 shows the embedded NORD Flash process flow with a high voltage (HV) peripheral integrated into the 55 nm CMOS process. Only five extra mask layers are required for NORD Flash cell integration. Compared to the total 39 mask layers of the 55 nm embedded NORD Flash process with dual gate transistors and eight metal layers (8 M), the NORD Flash cell is very cost effective from a manufacturing cost perspective.

2.2. Implementation of High Noise Immunity Sense Amplifier

With the advancement of semiconductor process nodes, the operating voltage is decreasing too. It narrows the window of the flash sense amplify circuit. Power supply fluctuation is more likely to effect comparison results. In order to solve this problem and to achieve an effective improvement in reliability, we optimized the sense amplifier circuit for high noise immunity.

A commonly used sense amplifier circuit is shown in Figure 4 [22]. The IO signal clamp circuit in Figure 4 is constructed using the N02 and P01, N01 invertor. This clamp circuit works to keep the potential of each point in a stable range and eliminates the risk of overcharge [23]. Here, N02 acts as an amplifier; when working in the saturation region, Vds of P02 and N02 are assumed to be small enough to be ignored. The relationship between node E and node C satisfies the following equation:

$$V\left(\mathrm{E}\right)\approx Vdd-{\displaystyle \frac{{\mathsf{\mu }}_{\mathrm{n}}{\mathrm{C}}_{\mathrm{O}\mathrm{X}}}{2}}{\displaystyle \frac{\mathrm{W}}{\mathrm{L}}}{\left[V\left(\mathrm{C}\right)-{\mathrm{V}}_{\mathrm{T}\mathrm{H}}\right]}^2{\mathrm{R}}_{\mathrm{l}\mathrm{o}\mathrm{a}\mathrm{d}}$$

Here, ${\mathsf{\mu }}_{\mathrm{n}}$ means electronic mobility, ${\mathrm{C}}_{\mathrm{O}\mathrm{X}}$ means oxide capacitance, $\mathrm{W}$ and $\mathrm{L}$ refer to the width and length of N02, ${\mathrm{V}}_{\mathrm{T}\mathrm{H}}$ means the threshold voltage of N02 and ${\mathrm{R}}_{\mathrm{l}\mathrm{o}\mathrm{a}\mathrm{d}}$ means the resistance of IO–terminal load.

Figure 4. Commonly used sense amplifier circuit.

Figure 4. Commonly used sense amplifier circuit.

According to the equation, a small variation in V(C) will cause a great change to V(E). Additionally, the conductivity of P01 will be influenced if Vdd fluctuates because node IO is not in a common mode with Vdd. Especially under the circumstances of low Vdd and high-speed reading studied in this paper, the comparison margin between V(E) and Vref_E will be smaller, which leads to the reduction in the mis-reading tolerance.

High noise immunity is important for robust MCU operations. To cope with the challenge of the sense amplifier, a common coupling mechanism mode is used in this paper. Signal VBIAS is introduced via a current mirror circuit to replace the IO as the gate voltage of P01 in Figure 5a; this fluctuates in common mode with Vdd. The current mirror provides a constant current, which is generated by the bandgap mode, that can be equivalent to a constant current source, as shown in Figure 5a. So, the current of P2 can be calculated as follows:

$${\mathrm{I}}_{\mathrm{P}2}=\mathsf{\mu }{\mathrm{C}}_{\mathrm{o}\mathrm{x}}{\displaystyle \frac{\mathrm{W}}{\mathrm{L}}}{\left(V_{BIAS}-V_{dd}-{\mathrm{V}}_{\mathrm{T}\mathrm{H}}\right)}^2$$

Here, ${\mathrm{I}}_{\mathrm{P}2}$ is a constant, so $\left(V_{BIAS}-V_{dd}-{\mathrm{V}}_{\mathrm{T}\mathrm{H}}\right)$ is also equal to a constant. It is apparent that $V_{BIAS}$ fluctuates in common mode with $V_{dd}$. Then, this signal is imported into the sense amplifier. The improved circuit is shown in Figure 5b.

Figure 5. (a) Current mirror circuit produces a VBIAS signal. (b) Improved sense amplifier.

Figure 5. (a) Current mirror circuit produces a VBIAS signal. (b) Improved sense amplifier.

3. Highly Reliable and High-Speed Reading Performance and Measurement Results

3.1. High Endurance Performance

Figure 6 depicts the cell current distribution degradation of this enhanced cell in various range of program/erase (P/E) cycling times; the test is carried out according to the operation conditions in Table 2 under 25 °C and 85 °C. Ir01 and Ir11 correlate to the cell current of CELL01 and CELL11, respectively. The test results show that under the conditions of room temperature and high temperature, after 2500 K cycles, all bits remain withing the margin according to the reference current, ~5 μA. Both Ir01 and Ir11 become smaller along with the endurance cycles, which indicates that the program operation of selected FGs becomes stronger and the erase operation becomes weaker.

We used a stronger erase condition (erase Vwl 9.6 V and Vcg −8.5 V, shown with the red line) to erase the cell post 2500 K cycles under room temperature. The Ir11 distribution can be recovered to a level comparable to 300 K cycles. It indicates that the degradation of the select gate oxide under WL is not the major root cause of this cell current drop; instead, the shallow energy level trap within the oxide surrounding the select FG is. This mainly benefits from the erase operation splitting the high voltage on both the CG and WL, which reduces the stress on the WL gate oxide.

3.2. High-Speed Reading Performance

As shown in Figure 7, we can divide the read operation into two stages—pre-charge, comparison, and output. When pre-charge starts, corresponding to Figure 4, signal BL_PREb opens P02 to pre-charge the node E (V(E)) to the supply voltage. At the same time, the WL and CG also pre-charge to the read voltage (Vwl and Vcg). In the comparison and output stage, BL_PREb closes P02, and V(E) is determined by the cell current Icell and reference current Iref, which is mirrored from the average current of the reference cells by using the current mirror circuit. Then, signal Sense2 pulls up to enable the comparator, comparing V(E) with the reference voltage Vref_E, and displays the result of the read operation.

In the embedded NORD Flash cell process, the WL is processed with poly-silicide, while the CG remains as non-silicide poly. The much larger CG resistance than WL makes CG pre-charging a bottleneck that has limited the implementation of high-speed reading in prior work. When the signal READ gives a positive pulse to start the read operation, the reference IP has to pre-charge the CG to the specified voltage first; then, the comparison and output process can proceed.

In our design, the CG read pre-charge can be bypassed and in the pre-charge stage, only WLs need to be pre-charged. Through this method, the time of pre-charge can be remarkably shortened, as depicted in Figure 7b. The implementation of high-speed reading can be explained through two mechanisms. First, it is obvious that the CG pre-charge process is much slower than the WL in the reference IP, which will effect the overall pre-charge time (the pre-charging time is defined as the delay from the READ signal raising margin to Vwl/Vcg up to 90%). In addition, in the comparison stage, the enhanced cell structure has a larger cell current, which can shorten the comparison time between the cell current and the reference current, so the read time can sped up too.

Compared with the reference IP using the conventional NORD Flash cell structure, our method demonstrates a significant high-speed reading performance improvement. The reading speed can be boosted to 18 ns under a normal 1.2 V supply voltage. Moreover, because the Flash IP with this enhanced cell structure only requires one WL charge pump to pre-charge word lines during the read operation, all other charge pumps can be turned off. Therefore, the read and standby power consumption can be greatly reduced.

Figure 7. (a) Timing diagram of the read operation in reference IP. (b) Timing diagram of the read operation in this IP.

Figure 7. (a) Timing diagram of the read operation in reference IP. (b) Timing diagram of the read operation in this IP.

3.3. High Noise Immunity Performance

It turns out that when the supply voltage is unstable, the read “0” error will be more likely to appear, as the simulation result shows in Figure 8a with Vdd fluctuating within 1.05–1.2 V and the fluctuate frequency is 125 MHz. The E point fluctuates along with the power supply, which will cause it to cross over the Vref_E and the output incorrect signals during read ”0”. Figure 8b illustrates that after introducing the common-mode coupling mechanism, data misreading caused by supply voltage fluctuation can be solved.

3.4. Full-Chip Measurement and Comparison Results

Figure 9a shows the layout of the Flash memory IP, where the IP size is 1.39 mm². We test the Flash IP with a test chip including a Flash IP and an IO pad ring. The signal inside the Flash IP was probed with pico-probes, which is shown in Figure 9b. Figure 10 depicts the measured waveforms of the read. The delay from the READ command to the output node DOUT is about 18 ns (Signal READ increases slowly due to the delay among the test chip).

Table 3. Key process parameters and chip performance.

	ESF3 [24]	This Work
Sector Size	256 × 38 Kbits	512 KBytes
Power Supply	1.1 V ± 10%; 2.5 V ± 10%	1.2 V ± 10%
Program Time	10 μs	5 μs
Read access Time	Random 10 ns	18 ns
Sector Erase Time	10 ms	2 ms
P/E Endurance	≥100 K	≥2500 K

compares the key process parameters and chip performance of the advanced ESF3 cells and the enhanced Flash cell in this work. It is depicted that our research can achieve a better program/erase cycling endurance performance than third-generation SuperFlash with a high-speed operation.

4. Conclusions

Overall, the results indicate that our work is efficient in high-reliability and high-speed reading Flash cell designs. The Flash array proposed in this paper, which has a larger current sensing window under the read operation, can solve the problem of the cell current attenuation and device reliability decrease in Flash memory due to the high integration and low-cost evolution trends of the system-on-chip (SOC).

Moreover, the P/E cycling test conducted in this research shows a similar cell current degradation performance at 25 °C and 85 °C, coupled with a recoverable current window under enhanced erase conditions; this technology is promising for automotive applications. More subsequent studies can be conducted to further optimize the sequential circuits and device manufacturing processes in the future to achieve high reliability and high endurance in even harsher operating environments.

We will take advantage of the NORD structure to evolve to smaller and more advanced technology nodes. In relation to the application outlook of Flash memory technology, it is expected to continue to evolve in line with Moore’s Law to meet the demands of portable systems for high-density and high-write throughput, which will also guide the subsequent refinement of our future design.