A Programmable Gain Amplifier Featuring a High Power Supply Rejection Ratio for a 20-Bit Sigma-Delta ADC

Abstract

A programmable gain amplifier (PGA) is commonly used to optimize the input dynamic range of high-performance systems such as headphones and biomedical sensors. But PGA is rather sensitive to electromagnetic interference (EMI), which limits the precision of these systems. Many capacitor-less low-dropout regulator (LDO) schemes with high power supply rejection have been proposed to act as the independent power supply for PGA, which consumes additional power and area. This paper proposed a PGA with a high power supply rejection ratio (PSRR) and low power consumption, which serves as the analog front-end amplifier in the 20-bit sigma-delta ADC. The PGA is a two-stage amplifier with hybrid compensation. The first stage is the recycling folded cascode amplifier with the gain-boost technique, while the second stage is the class-AB output stage. The PGA was implemented in the 0.18 μm CMOS technology and achieved a 9.44 MHz unity-gain bandwidth (UGBW) and a 57.8° phase margin when driving the capacitor of 5.9 pF. An optimum figure-of-merit (FoM) value of 905.67 has been achieved with the proposed PGA. As the front-end amplifier of a high-precision ADC, it delivers a DC gain of 162.1 dB, the equivalent input noise voltage of 301.6 nV and an offset voltage of 1.61 μV. Within the frequency range below 60 MHz, the measured PSRR of ADC is below −70 dB with an effective number of bits (ENOB), namely 20 bits.

1. Introduction

As consumer electronics products such as audio sensors keep demanding and chip integration develops rapidly, all the collaborating chips tend to be integrated into a single SoC system, resulting in EMI coupled on the supply rails [1,2,3,4,5]. As the important module of a high-performance analog front-end chip, the performance of PGA in the sigma-delta ADC is apparently affected by the interference coupled to the positive supply rail rather than the negative supply rail [3]. Consequently, the front-end amplifier of a high-precision sigma-delta ADC should provide a high power supply rejection ratio (PSRR) of a wide frequency range, low gain error, low offset and low noise with low power consumption.

A variety of circuit schemes have been used to circumvent this problem. Some techniques can effectively improve PSRR by increasing the unity-gain bandwidth (UGBW). R. S. Assaad et al. proposed a novel recycling folded cascode amplifier, which delivers a generally improved performance over that of the conventional folded cascade amplifier, with a figure-of-merit (FoM) value of 939.4 [6]. Furthermore, Y. L. Li et al. proposed the improved recycling folded cascade (IRFC) amplifier, which can provide a wider UGBW by separating the AC path from the DC path [7]. But the phase margin is reduced due to the presence of an additional high-impedance node and a pole–zero pair. M. Ahmed et al. utilized transistors in the triode region at current mirror nodes, which act as resistors in the improved recycling cascode amplifier to raise the second pole and enhance the phase margin [8]. Meysam Akbari et al. proposed the conjugated current mirror (CM) amplifier, which increases the transconductance and UGBW of the amplifier by providing an internal high-impedance node. Due to the larger non-dominant pole, the phase margin is decreased when driving low capacitance loads and this CM amplifier technology cannot be used in multistage amplifiers [9].

Two-stage amplifiers with the gain-boost technique are often used to attain high open-loop gain, which can decrease the linearity gain error and enhance the settling accuracy [10,11]. The scheme mentioned above is extensively implemented in the high-precision ADC. Yu Liu et al. proposed a single-stage gain-boost cascode amplifier with a three-layer feedback amplifier (FA) in the 14-bit pipelined ADC, achieving a gain enhancement of more than 20 dB [12]. Several frequency compensation techniques such as miller compensation [13] and cascode [14] compensation are used to design stable two-stage amplifiers. The miller compensation scheme suffers from the low speed and the low high-frequency PSRR [14], whereas cascode compensation achieves higher PSRR and UGBW at the expense of a more complex analog analysis procedure [13,14,15]. G.A. Fahmy et al. proposed the two-stage recycling folded cascade amplifier with split-length devices for indirect compensation to enhance the output impedance, attaining a gain value of 60dB and a FoM value of 872.6 [1]. Y. Xin et al. proposed a two-stage amplifier with inner feedforward path compensation with high current efficiency to eliminate the right half-plane (RHP) zero [16].

In this work, we proposed a PGA featuring high PSRR together with high UGBW, and low power consumption for a 20-bit sigma-delta ADC. We use the recycling folded cascode amplifier with the gain-boost technique as the first stage of the two-stage amplifier to enhance the performance of UGBW and PSRR with high current efficiency. The second stage is the rail-to-rail output stage with the floating class-AB control to enhance the driving ability. Furthermore, we adopt hybrid compensation for the two-stage amplifier, which can enhance PSRR compared with cascode compensation. The chopper technique is adopted to eliminate offset and low-frequency 1/f noise [17,18,19]. And the corresponding filter and calibration modules are in the digital section. As a result, the PGA achieved the UGBW of 9.44 MHz and the DC gain of 162.1 dB at the load capacitor of 5.9 pF, consuming the current of 61.5 μA, while the corresponding FoM value is 905. The experimental high-frequency PSRR of the ADC is less than −70 dB, which indicates that the proposed PGA can resist high-frequency power supply noise.

The following is the structure of this paper. Section 2 presents the proposed structure of the front-end PGA in the 20-bit sigma-delta ADC and the open-loop small-signal transfer function of the proposed amplifier is obtained here to calculate its poles and zeros accurately. Furthermore, the analysis of input offset and noise is also included in Section 2. Experimental and simulation results are discussed in Section 3. Finally, the discussion and conclusion are presented in Section 4.

2. Design of the Proposed PGA

2.1. The Architecture of the 20-Bit Sigma-Delta ADC

The overall architecture of the proposed sigma-delta ADC is presented in Figure 1. The closed-loop gain of PGA is as follows:

$$A_{close\mathrm{d}-loop}=1+2\times {\displaystyle \frac{R_1}{R_2}}$$

(1)

The variation range of the closed-loop gain is 1–32. The values of feedback resistors should be carefully considered because their values will affect many indicators such as noise, loop stability and gain. The noise contribution of feedback resistors and the open-loop gain is proportional to the values of resistors, while the value of the loop pole is inversely proportional to them. A trade-off is thus needed and the values of these resistors should be reasonable to balance these metrics.

The front-end PGA is employed to amplify small electrical signals to the detectable range of the sigma-delta ADC and improve the signal–noise ratio (SNR). However, the PGA may bring power supply interference, extra noise, offset and gain error, which can damage the quality of the input signal. Considering an error margin of LSB/2, the DC gain, the UGBW and the noise voltage of the PGA in the 20-bit sigma-delta ADC should adhere to the following standards:

$${\displaystyle \frac{1}{A\mathsf{\beta }}}\le {\displaystyle \frac{LSB}{2}}$$

(2)

$$e^{-{\displaystyle \frac{t}{\mathsf{\tau }}}}\le {\displaystyle \frac{LSB}{2}},\mathsf{\tau }={\displaystyle \frac{1}{2\mathsf{\pi }\mathsf{\beta }·UGBW}},t={\displaystyle \frac{N}{f_s}}$$

(3)

$$V_{n,out}\le {\displaystyle \frac{LSB}{2}}$$

(4)

where $A$, $\mathsf{\beta }$, $t$ and $\mathsf{\tau }$ are the DC gain, the feedback factor ($1/A_{closed}$), establishment time and the time constant of the amplifier, $f_s$ is the modulation frequency of the ADC. The 20-bit sigma-delta ADC requires the amplifier to achieve a DC gain of 127 dB, a UGBW of 5 MHz and an output noise voltage of 2 μV (assuming that $f\_s=256 \mathrm{K}\mathrm{H}\mathrm{z}, N=10, Data Rate=20 \mathrm{S}\mathrm{P}\mathrm{S}$). In this paper, we proposed a scheme which can effectively meet the above requirements.

2.2. The Small-Signal Model

A proposed two-stage amplifier with hybrid compensation using a recycling folded cascade amplifier as the first stage is illustrated in Figure 2. As shown in Figure 2, two compensation capacitors, C_cn and C_cp, are used in the signal path and the non-signal path separately. The amplification factor (K) of the current mirror is set to 3. This technique offers much improved high-frequency PSRR and UGBW. The second stage is a class-AB output stage controlled by translinear loops to drive the sampling capacitor and increase the slew rate [20,21].

2.2.1. The Proposed RFC1

In order to guarantee the stability of this two-stage amplifier, it is essential to simplify an appropriate small-signal model that can be used to deal with the complicated poles and zeros. The simplified small-signal model for RFC1 is shown in Figure 3.

The two current sources with the value of $2g_{m1a}{V}_i$ originate from the input source-coupled MOSFETs $M_{3a}\sim M_{4b}$; the right one corresponds to the sum of the currents of $M_{4a}$ and mirrored $M_{3b}$ and connects to $C_{cn}$ and the source of $M_{10}$; the left one refers to the small-signal current generated by $M_{3a}$ and mirrored $M_{4b}$ after being copied by the current mirrors formed by $M_{15}$ and $M_{16}$. $M_{11}$ and $M_{12}$ are implemented as floating voltage sources in the small-signal state and can be shorted without a signal leaked to the virtual ground in the small-signal model. In addition, the transconductances of $M_{11}$ and $M_{12}$ are usually designed to be approximately equal and the impedances of them should be low enough compared with the impedances of cascode current mirrors to implement ideal voltage sources [21]. The current source $g_{m2}{V}_1$ corresponds to the small-signal current of $M_{10}$. The current source $g_{m3}{V}_2$ corresponds to the small-signal current of $M_{14}$.

The small-signal equations of the circuit shown in Figure 2 are as follows:

$$2g_{m1a}{V}_i+g_{m2}{V}_1+\left(V_1-V_o\right){\mathrm{C}}_{cn}s+V_1/R_1+V_1{C}_{1}s=0$$

(5)

$$-g_{m2}{V}_1-g_{m3}{V}_2+V_3{C}_{3}s+V_3/R_3=0$$

(6)

$$g_{m3}{V}_2+\left(V_2-V_o\right)C_{cp}s+{\mathrm{V}}_2/R_2+V_2{C}_{2}s+2g_{m1a}{V}_i=0$$

(7)

$$\left(g_{m4}+g_{m5}\right)V_3+\left(V_o-V_1\right)C_{cn}s+\left(V_o-V_2\right)C_{cp}s+V_o{C}_{L}s+V_o/R_L=0$$

(8)

where $R_1,R_2,R_3,R_L$ and $C_1,C_2,C_3,C_L$ are the resistances and capacitances seen at the nodes V1, V2, V3 and Vo, respectively, and can be expressed as follows:

$$R_1=r_{ds8b}\parallel r_{ds4a}\parallel \left(g_{m14}{r}_{ds14}{r}_{ds16}\right)/\left(1+g_{m10}{r}_{ds10}\right)$$

(9)

$$R_o=r_{ds25}\parallel r_{ds26}$$

(10)

$$R_2=r_{ds16}\parallel \left(g_{m10}{r}_{ds10}\left(r_{ds8a}\parallel r_{ds4a}\right)\right)/\left(1+g_{m14}{r}_{ds14}\right)$$

(11)

$$R_3=\left(g_{m14}{r}_{ds14}{r}_{ds16}\right)\parallel \left(g_{m10}{r}_{ds10}\left(r_{ds8a}\parallel r_{ds4a}\right)\right)$$

(12)

$$C_1=C_{gs10}+C_{sb10}+C_{gd8b}+C_{db8b}+C_{gd4a}+C_{db4a}$$

(13)

$$C_2=C_{gd16}+C_{db16}+C_{gs14}+C_{sb14}$$

(14)

$$C_3=C_{gd14}+C_{db14}+C_{gd10}+C_{db10}$$

(15)

$$C_o=C_{gd25}+C_{db25}+C_{gd26}+C_{db26}$$

(16)

After solving the above equations, the fourth-order open-loop transfer function can be obtained as follows:

$$H\left(s\right)={\displaystyle \frac{-2\left(s^3{e}_3+s^2{e}_2+s^1{e}_1+e_0\right)}{s^4{d}_4+s^3{d}_3+s^2{d}_2+s^1{d}_1+d_0}}$$

(17)

where $e_0$~$e_3$ and $d_0$~$d_4$ can be calculated accurately in terms of the circuit parameters. But the accurate values of these coefficients are so complex that they cannot give any intuitive guidance in the circuit design. Therefore, we make the following assumptions:

• $C_{cn}$ is set to be equal to $C_{cp}$.
• Parasitic capacitors are much less than compensation capacitors and load capacitors.
• The intrinsic gain of a transistor in the saturation region is much larger than one.

After simplification, we can obtain expressions of the above coefficients as follows:

$$e_0=-2R_1{R}_2{R}_3{R}_L{g}_{m2}{g}_{m3}{g}_{m1a}\left(g_{m4}+g_{m5}\right)$$

(18)

$$e_1=-C_{cn}{R}_1{R}_2{R}_3{R}_L{g}_{m1a}\left(g_{m2}+g_{m3}\right)\left(g_{m4}+g_{m5}\right)$$

(19)

$$e_2=C_3{C}_{cn}{R}_1{R}_2{R}_3{R}_L{g}_{m3}{g}_{m1a}+C_3{C}_{cn}{R}_1{R}_2{R}_3{R}_L{g}_{m2}{g}_{m1a}$$

(20)

$$e_3=2C_3{C}_{cn}^2{R}_1{R}_2{R}_3{R}_L{g}_{m1a}$$

(21)

$$d_0=R_1{R}_2{g}_{m2}{g}_{m3}$$

(22)

$$d_1=2C_{cn}{R}_1{R}_2{R}_3{R}_L{g}_{m2}{g}_{m3}\left(g_{m4}+g_{m5}\right)$$

(23)

$$d_2=C_{cn}^2{R}_1{R}_2{R}_3{R}_{\mathrm{L}}\left(g_{m2}+g_{m3}\right)\left(g_{m4}+g_{m5}\right)$$

(24)

$$d_3=C_3{C}_{cn}{R}_1{R}_2{R}_3{R}_L\left(g_{m2}+g_{m3}\right)\left(C_{cn}+C_L\right)$$

(25)

$$d_4=C_3{C}_L{C}_{cn}^2{R}_1{R}_2{R}_3{R}_L$$

(26)

The system has three zeros and four poles seen from Equation (17). We assume that the first left-half plane zero is much less than the other two zeros. It is given as follows:

$${\mathit{\omega }}_{z1}=-{\displaystyle \frac{e_0}{e_1}}={\displaystyle \frac{-2g_{m2}{g}_{m3}}{C_{cn}\left(g_{m2}+g_{m3}\right)}}$$

(27)

The expressions of the remaining two zeros are as below:

$${\mathsf{\omega }}_{z2,3}=\pm \sqrt{{\displaystyle \frac{\left(g_{m2}+g_{m3}\right)\left(g_{m4}+g_{m5}\right)}{2C_{cn}{C}_3}}}$$

(28)

The dominant pole is also assumed to be much smaller than the other poles, which is shown as follows:

$${\mathsf{\omega }}_{p1}=-{\displaystyle \frac{d_0}{d_1}}=-{\displaystyle \frac{1}{2C_{cn}{R}_3{R}_L\left(g_{m4}+g_{m5}\right)}}$$

(29)

In order to obtain the second real pole, it is assumed that its value is much lower than the other two non-dominant poles. It is given as follows:

$${\mathsf{\omega }}_{p2}=-{\displaystyle \frac{d_1}{d_2}}=-{\displaystyle \frac{2g_{m2}{g}_{m3}}{C_{cn}{g}_{m2}{g}_{m3}}}$$

(30)

The other two non-dominant poles are conjugate poles, which can be characterized by the natural frequency ${\mathsf{\omega }}_{op}$ and the quality factory $Q$ [14].

$${\mathsf{\omega }}_{op}=\sqrt{{\displaystyle \frac{\left(g_{m2}+g_{m3}\right)\left(g_{m4}+g_{m5}\right)}{C_3{C}_L}}}$$

(31)

$$Q={\displaystyle \frac{\sqrt{d_2{d}_4}}{d_3}}=\sqrt{{\displaystyle \frac{C_{cn}^2{C}_L\left(g_{m4}+g_{m5}\right)}{C_3\left(g_{m2}+g_{m3}\right){\left(C_{cn}+C_L\right)}^2}}}$$

(32)

Based on the expressions of the above poles and zeros, we can obtain the following important conclusions:

• To avoid peaking in the magnitude response, the quality factory Q should be decreased by reducing $C_{cn},g_{m4},g_{m5}$ and increasing $g_{m2},g_{m3}$.
• The value of ${\mathsf{\omega }}_{p2}$ is equal to the value of ${\mathsf{\omega }}_{z1}$, so the order of the system is reduced to three.
• The values of ${\mathsf{\omega }}_{\mathrm{z}2,3}$ are much greater than the value of UGBW, so these two zeros cannot affect the frequency response within UGBW. The expression of UGBW is as follows:

  $$UGBW={\displaystyle \frac{4g_{m1a}}{C_{cn}}}$$

  (33)

2.2.2. The Proposed RFC2

In order to reduce offset and 1/f noise, we adopt the chopper technique in the first stage. The offset and 1/f noise of the second stage can be ignored, which is divided by the gain of the first stage when offset and noise are considered in the input terminal. Furthermore, the gain-boost technique is added in the first stage to enhance the DC gain. The UGBW values of these two gain-boost amplifiers should be larger than the UGBW value of the original amplifier shown in Figure 2 and be smaller than the second pole of the original amplifier [10,22]. As a result, the final proposed two-stage amplifier with the gain-boost circuit and chopper circuit in the 20-bit sigma-delta ADC is shown in Figure 4a.

The small-signal model of RFC2 is similar to that of RFC1. The zeros and poles within the UGBW values of the two amplifiers should be generally similar. There are two differences between them, as follows:

• The values of $g_{m2}$ and $g_{m3}$ should be multiplied by the gain values of the GainboostP stage and GainboostN stage separately.
• The values of $C_1$ and $C_2$ should be added by the values of corresponding parasitic capacitors in the GainboostP and GainboostN, respectively.

The CMOS switch in Figure 4b is used in the input end to suppress the imperfect characteristics of the switch. Meanwhile, we use the PMOS switch in the CH_p and the NMOS switch in the CH_n, which are shown in Figure 4c. The GainboostP and GainboostN are the cascode amplifiers using PMOS input and NMOS input, respectively. Since the corner frequency for a CMOS amplifier is 10 kHz typically, we set the value of the chopper frequency $f_{CH}$ to 128 kHz, which is half of the value of the modulation frequency.

2.3. Input Offset

Supposing that $g_m/I_D$ is generally maximized, the gate–source voltage variance of a MOS device can be approximately defined as follows [6,9]:

$${\mathsf{\sigma }}^2(V_{GS})={\displaystyle \frac{A_{VTH}^2}{WL}}$$

(34)

where $A_{VTH}$ is a constant provided by process characterization. From the standpoint of circuit analysis, ${\sigma }^2\left(V_{GS}\right)$ can be treated as the small signal added in the gate and referred to as the input through the transconductance of a MOS device. Assuming the offset of the second stage amplifier can be neglected, the input offset variances are expressed as follows:

$$\begin{array}{l}{\mathsf{\sigma }}^2\left(V_{os},RFC2\right)={\displaystyle \frac{A_{VTHP}^2}{{\left(WL\right)}_{4a}}}\left(1+{\displaystyle \frac{{\left(WL\right)}_{4a}}{16{\left(WL\right)}_{16}}}{\displaystyle \frac{g_{m16}^2}{g_{m4a}^2}}\right)+{\displaystyle \frac{A_{VTHN}^2{g}_{m7b}^2}{4{\left(WL\right)}_{7b}{g}_{m4a}^2}}\\ +{\displaystyle \frac{1}{16g_{m4a}^2}}\left({\displaystyle \frac{{\mathsf{\sigma }}^2\left(V_{os},GBN\right)}{r_{o16}^2}}+{\displaystyle \frac{{\mathsf{\sigma }}^2\left(V_{os},GBP\right)}{{\left(r_{o4a}//r_{o8b}\right)}^2}}\right)\end{array}$$

(35)

where ${\sigma }^2\left(V_{os},GBN\right)$ and ${\sigma }^2\left(V_{os},GBP\right)$ are the output offset variances of the GainboostN and GainboostP stages.

2.4. Noise

The noise power spectral density seen at the gate of a MOS device can be given by the following:

$$\overline{V_n^2}={\displaystyle \frac{4kT\mathsf{\gamma }}{g_m}}+{\displaystyle \frac{K}{C_{ox}WLf}}$$

(36)

where the first and second terms represent thermal noise and flicker noise, respectively. Similarly to the expression of offset, the input noise power spectral density is as given in (37).

$$\begin{array}{l}\overline{V_{n,RFC2}^2}=\overline{V_{n.4a}^2}\left(1+{\displaystyle \frac{{\left(WL\right)}_{4a}}{16{\left(WL\right)}_{16}}}{\displaystyle \frac{g_{m16}^2}{g_{m4a}^2}}\right)+{\displaystyle \frac{\overline{V_{n.7b}^2}{g}_{m7b}^2}{4g_{m4a}^2}}+\\ {\displaystyle \frac{1}{16g_{m4a}^2}}\left({\displaystyle \frac{\overline{V_{n.GBN}^2}}{r_{o16}^2}}+{\displaystyle \frac{\overline{V_{n.GBP}^2}}{{\left(r_{o4a}//r_{o8b}\right)}^2}}\right)\end{array}$$

(37)

where $\overline{V_{n,GBN}^2}$ and $\overline{V_{n,GBP}^2}$ are the output noise power spectral density values of the GainboostN and GainboostP stages. Substituting Equation (36) into Equation (37), we can obtain the input thermal noise and input flicker noise of RFC2, respectively, in (38) and (39).

$$\begin{array}{l}\overline{V_{thermal,RFC2}^2}=4kT\mathsf{\gamma }\left({\displaystyle \frac{1}{g_{m,4a}}}+{\displaystyle \frac{{\left(WL\right)}_{4a}{g}_{m,16}^2}{16{\left(WL\right)}_{16}{g}_{m,4a}^3}}\right)+{\displaystyle \frac{kT\mathsf{\gamma }{g}_{m,7a}}{g_{m,4a}^2}}+\\ {\displaystyle \frac{1}{16g_{m4a}^2}}\left({\displaystyle \frac{\overline{V_{n.GBN}^2}}{r_{o16}^2}}+{\displaystyle \frac{\overline{V_{n.GBP}^2}}{{\left(r_{o4a}//r_{o8b}\right)}^2}}\right)\end{array}$$

(38)

$$\begin{array}{l}\overline{V_{flic\ker ,RFC2}^2}={\displaystyle \frac{K}{C_{ox}{\left(WL\right)}_{4a}f}}\left(1+{\displaystyle \frac{{\left(WL\right)}_{4a}}{16{\left(WL\right)}_{16}}}{\displaystyle \frac{g_{m16}^2}{g_{m4a}^2}}\right)+{\displaystyle \frac{K}{C_{ox}{\left(WL\right)}_{7b}f}}{\displaystyle \frac{g_{m7b}^2}{4g_{m4a}^2}}+\\ {\displaystyle \frac{1}{16g_{m4a}^2}}\left({\displaystyle \frac{\overline{V_{n.GBN}^2}}{r_{o16}^2}}+{\displaystyle \frac{\overline{V_{n.GBP}^2}}{{\left(r_{o4a}//r_{o8b}\right)}^2}}\right)\end{array}$$

(39)

3. Experimental and Simulation Results

RFC1 and RFC2 have been fabricated in the TSMC 0.18 μm CMOS process. Figure 5 shows the die micrograph highlighting the RFC1 and RFC2 with the biasing circuits. The 5 V devices were used to reduce the cost of manufacture so the area was a little larger than that using 3.3 V or 1.8 V devices. RFC1 was simulated and measured, while RFC2 is in the 20-bit sigma-delta ADC, so only the indicators of the ADC can be measured and displayed. To quantify the power-efficiency characteristics of amplifiers, figures of merit were proposed [6,16] as follows:

$$\mathrm{F}o{M}_s={\displaystyle \frac{GBW\ast C_L}{I_{total}}}$$

(40)

$$Fo{M}_L={\displaystyle \frac{SR\ast C_L}{I_{total}}}$$

(41)

where $GBW$ refers to the unity-gain bandwidth of the amplifier, $SR$ is the slew rate of the amplifier, $C_L$ is the capacitive load and $I_{total}$ is the current consumption containing the bias current. The $I_{total}$ values of RFC1 and RFC2 are 53.5 μA and 61.5 μA.

3.1. Simulated Results

3.1.1. Small-Signal Frequency Response Simulation

Figure 6a presents the simulated open-loop AC response of the amplifiers when driving the capacitive load of 5.9 pF and using the simulation tool of iprobe. The UGBW of RFC1 and RFC2 is 9.07 MHz and 9.44 MHz, respectively, while the phase margin is 53.75° and 57.8° at their respective UGBW. Furthermore, the DC gain of RFC1 and RFC2 is 120.85 dB and 162.1 dB. It is worth mentioning that during the simulation progress, RFC1 does not drive the resistive load, while RFC2 drives the restive loads (R₁ and R₂) of 40 kΩ, which is more advantageous for testing its performance in the application environment. Figure 6b shows the variation in UGBW of RFC1 and RFC2 with temperature. In the worst situation, the value of UGBW meets the requirement of a 20-bit sigma-delta ADC.

3.1.2. Slew Rate Simulation

Figure 7 shows the large-signal characteristic of RFC1 at a load of 5.9 pF. Different from typical amplifiers, the first and second stages of the proposed architecture can respond more quickly to a large-signal square, resulting in a higher slew rate under the condition of the same consumption and load. The RFC1 is connected in the unity-gain negative feedback form. The average slew rate of RFC1 is 7.93 V/μs with the 1 Vpp square wave at 100 kHz applied to the input.

3.1.3. PSRR Simulation

Figure 8a is the simulation schematic diagram. The PSRR simulation results are shown in Figure 8b. The expression of PSRR is as below:

$$PSRR={\displaystyle \frac{A_{dm}|v_{dd}=0}{A_{dd}|v_{in,dm}=0}}$$

(42)

where $A_{dm}$ is the differential gain from input to output and $A_{dd}$ is the gain from the positive supply rail to output. The DC PSRR values of RFC1 and RFC2 are 78.45 dB and 134.57 dB, respectively, while the unity-PSRR bandwidth values of RFC1 and RFC2 are 23.89 MHz and 72.82 MHz.

3.1.4. Simulations of Noise and Offset

To demonstrate the ability of the chopper technology to reduce low-frequency noise and offset, the simulation of noise and offset has been completed with the noise power spectral density results and Monte Carlo simulation results shown in Figure 9 and Figure 10 separately. The equivalent output noise voltage value of RFC1 with the frequency range of 1 Hz to 100 MHz is 27.16 μV and the equivalent output noise voltage values of RFC2 with the chopper technique on and down are 301.6 nV and 24.63 μV, respectively. Significantly, the noise is modulated to the odd harmonics of the chopper frequency, so chopping should be equipped with a low-pass filter, which is an RC first-order filter in the simulation schematic design for simplicity. The offset value of RFC1 is 4.78 mV (one sigma). The offset values of RFC2 with and without the chopper circuit are 1.61 μV and 3.54 mV (one sigma), respectively.

3.2. Measured Results

3.2.1. Unity-Gain Bandwidth Measurement

The measurement setup is given in Figure 11. This circuit was connected to the DC closed-loop state and the AC open-loop state owing to the characteristic of resistors that pass through the DC current and block the AC current. To better utilize this characteristic, the value of R₁ should be as large as possible. Similarly, the value of C₁ should be as large as to fulfill the function of passing through the AC current and blocking the DC current. However, their values should not be too large so that the RC settling time is too long, which is not conducive to measurement. Here, the values of C₁ and R₁ are set to be 1 μF and 300 MΩ, respectively. C₂ represents the pad capacitance with a value of approximately 2 pF. Along with 3.9 pF of the TPP1000 probe, the total capacitance load is 5.9 pF. The RIGOL DG4062 was used to generate the 100 mV sinusoidal wave as the positive input, while the negative input was connected to virtual ground. The output wave was captured by the Tektronix MSO64B. As shown in Figure 12, the open-loop gain value of RFC1 decays to 1 when the input of a sine wave is at 9 MHz. In other words, the UGBW of RFC1 is 9 MHz. In addition, it can be seen that the phase margin is 47.16° from the phase delay of the input and output sine waves.

3.2.2. Slew Rate Measurement

As given in Figure 13, RFC1 was connected to unity-gain negative feedback. The RIGOL DG4062 was used to generate a 1 Vpp square wave at 100 kHz and the Tektronix MSO64B was applied to detect the output wave. In Figure 14, we can obtain the average slew rate as 6.96 V/μs, which is less than the simulation result of 7.93 V/μs. The discrepancy is partly due to the fact that the rising speed of the input square wave in the testing is not as fast as that in the simulation.

3.2.3. PSRR Measurement

As shown in Figure 15a, sine waves of different frequencies were added to the AVDD, while a fixed DC differential signal was applied to the input. The APx500 was used to provide a high-precision DC differential signal. The RIGOL DG4062 was employed to generate sine waves at different frequencies with an offset of 3.3 V. The expression of the measured PSRR is as below:

$$PSRR=20\lg \left({\displaystyle \frac{\left|V_{out,f}-V_{out,dc}\right|}{V_{AVDD,pp}}}\right)$$

(43)

where $V_{out,f}$ and $V_{out,dc}$ are the measured output voltage values at the specific frequency and the DC condition, $V_{AVDD,pp}$ refers to the peak-to-peak value of the sine wave applied to AVDD. The testing result of PSRR defined above is shown in Figure 15b. When the peak-to-peak values of sine waves are 33 mV and 66 mV at frequencies ranging from 100 Hz to 60 MHz, the values of PSRR are all lower than −70 dB.

Table 1. Performance comparisons with prior works.

PARAMETER	[16] *	[6]	[23] *	[24]	[25]	RFC1	RFC2
Technology	0.18 μm	0.18 μm	0.18 μm	0.065 μm	0.18 μm	0.18 μm	0.18 μm
Supply voltage (V)	1.8	1.8	3.3	1.2	1.8	3.3	3.3
Current (μA)	1200	800	88	10,500	4300	53.5	61.5
Area (μm2)	8694	4958	-	40,000	14,900	19,740	27,570
Architecture	2st	1st	2st	3st	3st	2st	2st
DC gain (dB)	83	53.6	72	71.3	99.83	120.85 *	162.1 *
Phase margin	80	70.6 *	57	82.6	51.7	47.16	57.8 *
GBW (MHz)	187	134.2	51	2410	86.96	9	9.44 *
Slew rate (V/μs)	74	94.1	-	1725	90	6.96	-
Capacitive load (pF)	5.6	5.6	1	2	32	5.9	5.9
Offset (μV)	-	7600	-	-	-	4780 *	1.61 *
PSRR (dB) at DC	-	-	94.66	-	-	78.45 *	134.57 *
FoMs (MHz•pF/mA)	872.66	939.4	579.54	459.05	647.144	992.52	905.67
FoML (V/μs•pF/mA)	345.33	658.7	-	328.57	669.76	767.55	-

* Simulation results. The slew rate of RFC2 cannot be simulated because of the chopper circuit. When the chopper switches are switched, the circuit state is also reestablished, which will influence the process of large-signal establishment.

represents a performance summary of our work and the performance comparisons with other different architectures. As shown in Figure 16, two of the most important metrics are extracted to compare the performance of RFC1 and RFC2 with that of prior works. The value of FoM_s implies the efficiency of the obtained bandwidth and the value of bandwidth is related to PSRR at high frequencies. And the value of DC gain partly determines PSRR at low frequencies. In Figure 16, the DC gain of RFC1 and RFC2 is larger than that of prior works. The FoM_s value of RFC2 is a little less than that of [5] due to the power dissipation of the gain-boost circuit. Therefore, the proposed PGA achieves higher PSRR within the entire frequency band range than prior works.

4. Discussion and Conclusion

In this paper, the PGA with high PSRR and low power consumption is proposed to serve as the front-end amplifier of a high-precision sigma-delta ADC. To increase the settling accuracy and decrease the linearity gain error, the gain-boost technique was employed in the first stage, resulting in improvements of roughly 42 dB in DC gain and 56 dB in DC PSRR. The chopper circuit was also adopted in the first stage to obtain μV-level offset in Monte Carlo simulation and noise to fulfill the requirement of the 20-bit sigma-delta ADC. The RFC amplifier and hybrid compensation were used to achieve higher PSRR at high frequencies compared with prior works. However, if a more advanced manufacturing process is used, the phase margin can be improved at the expense of increased cost and decreased gain, while UGBW remains unchanged. As a result, the FoM_s of PGA reach 905.67 and the DC PSRR value comes to 134.57 dB. In addition, the values of PSRR are all below −70 dB when coupling high-frequency noise on the positive supply rail. In conclusion, the above performance of the proposed PGA indicates that it can resist high-frequency power supply noise interference in the 20-bit sigma-delta ADC.