Comparative Study on Device Type Configurations of 2T0C DRAM for Compute-in-Memory Applications

Round 1

Reviewer 1 Report

Comments and Suggestions for Authors

1. The authors state that they used a 65 nm CMOS-based 2T DRAM. However, compared to the latest DRAM technology node (1c nm, 6^th generation 10-nm node), it seems to be a highly outdated technology. It appears to contradict the authors’ statement that 2T DRAM offers advantages such as high speed and low power (line 41). Despite these points, is there any reason for choosing the 65 nm CMOS node, which first appeared about 20 years ago? Please clarify this point.

 

2. The authors state that the VTG 2T DRAM shows improved retention time and unit cell size compared to the planar 2T0C DRAM (line 45). However, the manuscript appears to investigate the planar 2T0C DRAM. What is the rationale for using a structure that is inferior to the VTG 2T DRAM? Please clarify this point.

 

3. In Fig. 3, it is unclear whether the presented transfer characteristics are based on calibrated data. If the NMOS and PMOS devices were calibrated, the reliability of an impartial comparison among the 2T0C DRAM unit cells could reasonably be maintained without enforcing identical doping concentrations between the NMOS and PMOS transistors. Please clarify the rationale behind adopting this simulation approach.

 

4. The authors present the physical parameters of the CMOS transistors used in Figure 2 and Table 1. Please provide appropriate references supporting the specific numerical values chosen. Furthermore, in Figure 4, the 2T DRAM cell size is shown as 0.54 µm². For comparison, the SRAM cell size in the TSMC 65 nm process is 0.499 µm², suggesting that the 2T DRAM exhibits even lower density than SRAM. Please provide the rationale for selecting parameters such as Contact Poly Pitch (CPP) and Metal Pitch.

 

5. The manuscript suggests that the NN-type and PP-type 2T0C DRAM demonstrate superior characteristics suitable for CIM compared to the NP-type and PN-type in terms of On/Off ratio and retention time. However, regarding the retention time for Data '0', the NN-type and PP-type exhibit significantly inferior characteristics compared to the NP-type and PN-type (Fig. 6). At this point, before merely claiming that a homogeneous case shows superior characteristics, methods to compensate for the insufficient retention characteristics in the respective devices should be discussed.

 

6. Parameters such as the on/off ratio and retention time can vary significantly depending on how the transistor off-state leakage current and threshold voltage are defined. Were these factors considered? If different criteria were used, please specify what they were. Please also include information on the read and write times.

 

7. The conclusions are derived under the specific conditions of Si 65 nm 2T0C DRAM, characterized by small storage-node capacitance and relatively high subthreshold hole leakage. These characteristics do not apply to oxide-semiconductor devices such as IGZO or SnO, which exhibit much lower leakage and operate under different bias and scaling conditions. It would be appropriate for the authors to clarify or explicitly limit the applicability of their conclusions to Si-based devices. Separating or revising the OSFET-related discussion could also help prevent misinterpretation of the study’s scope.

Author Response

Comment 1. The authors state that they used a 65 nm CMOS-based 2T DRAM. However, compared to the latest DRAM technology node (1c nm, 6th generation 10-nm node), it seems to be a highly outdated technology. It appears to contradict the authors’ statement that 2T DRAM offers advantages such as high speed and low power (line 41). Despite these points, is there any reason for choosing the 65 nm CMOS node, which first appeared about 20 years ago? Please clarify this point.

 Response 1: Thank you for your comment. The 2T0C DRAM structure used in this work is not compatible with the fabrication process of commercial 1T1C DRAM; therefore, a CMOS-based process is required. Although smaller CMOS technology nodes generally provide higher performance, the objective of this study is to analyze the electrical characteristics determined by the device-type configurations (NN, NP, PN, and PP), rather than to optimize a specific technology node. For this reason, we adopted the 65 nm CMOS technology, which is a technically mature and widely used node in embedded DRAM and CIM research.

 

Comment 2. The authors state that the VTG 2T DRAM shows improved retention time and unit cell size compared to the planar 2T0C DRAM (line 45). However, the manuscript appears to investigate the planar 2T0C DRAM. What is the rationale for using a structure that is inferior to the VTG 2T DRAM? Please clarify this point.

 Response 2: Thank you for your response. As mentioned, the VTG 2T DRAM structure can provide improved retention time and reduced unit cell area compared to the planar 2T0C DRAM. However, because the VTG structure is not compatible with standard CMOS fabrication processes, its practical implementation remains limited. Therefore, we selected the planar 2T0C DRAM structure for this work, as it can be fabricated within a CMOS-compatible process environment.

 

Comment 3. In Fig. 3, it is unclear whether the presented transfer characteristics are based on calibrated data. If the NMOS and PMOS devices were calibrated, the reliability of an impartial comparison among the 2T0C DRAM unit cells could reasonably be maintained without enforcing identical doping concentrations between the NMOS and PMOS transistors. Please clarify the rationale behind adopting this simulation approach.

 Response 3: Thank you for your comment. We understand “calibration” in this context to refer to matching the transfer characteristics of NMOS and PMOS devices in a symmetric manner. In this study, however, our primary objective is to compare the intrinsic device-type dependence among the NN-, NP-, PN-, and PP-type 2T0C DRAM unit cells. To ensure that the observed differences in electrical characteristics arise solely from the device-type configuration, we intentionally removed the influence of structural and process-related variations by using identical physical dimensions and doping concentrations for the NMOS and PMOS transistors. This approach allows a fair and isolated comparison of device-type behavior, independent of NMOS-PMOS mismatch effects. Additionally, the y-axis unit in Figure 3, which was mistakenly labeled as ‘A’ instead of ‘μA’, has also been corrected in the revised manuscript.

Figure 3. Transfer characteristics of NMOS and PMOS transistors with V_th of 0.29 V and -0.30 V, respectively.

 

Comment 4. The authors present the physical parameters of the CMOS transistors used in Figure 2 and Table 1. Please provide appropriate references supporting the specific numerical values chosen. Furthermore, in Figure 4, the 2T DRAM cell size is shown as 0.54 µm². For comparison, the SRAM cell size in the TSMC 65 nm process is 0.499 µm², suggesting that the 2T DRAM exhibits even lower density than SRAM. Please provide the rationale for selecting parameters such as Contact Poly Pitch (CPP) and Metal Pitch.

 Response 4: Thank you very much for your comment. The 2T0C DRAM unit cells in this work were initially designed based on the 4T2C eDRAM layout presented in Reference [14], which is implemented using a 65 nm logic process. Because our design followed CPP and Metal Pitch used in the reference, the shallow trench isolation (STI) region became relatively wide, which increased the calculated area to 0.54 μm². To address this, we reduced the unnecessary STI region and minimized the unit cell area to 0.39 μm². Although the unit cell area can be further reduced by minimizing CPP, such optimization was not pursued because the objective of this work is to compare electrical characteristics determined by the device-type configurations. In addition, Section 2 already notes the potential for further area reduction in the NN- and PP-type cells, as they share a common well region, unlike the NP- and PN-type cells. We have revised Section 2 to clarify the design basis and area reduction, and Figure 4 has been updated to show the 2T0C DRAM unit cells with an area of 0.39 μm².

Figure 4. 3D structures of 65 nm CMOS-based 2T0C DRAM unit cells with (a) NN, (b) NP, (c) PN, and (d) PP device types.

(Section 2) “Subsequently, 65 nm CMOS-based 2T0C DRAM unit cells with the NN, NP, PN, and PP device types were designed with a unit cell area of 0.54 μm²0.39 μm² for fair comparison, as shown in Figure 4. The unit cell layout was derived from the 4T2C eDRAM presented in [14].”

[14] Yu, C.; Yoo, T.; Kim, H.; Kim, T.T.; Chuan, K.C.T.; Kim, B. A Logic-Compatible eDRAM Compute-In-Memory With Embedded ADCs for Processing Neural Networks. IEEE Trans. Circuits Syst. I, Reg. Papers, 2021, 68, 667–679.

 

Comment 5. The manuscript suggests that the NN-type and PP-type 2T0C DRAM demonstrate superior characteristics suitable for CIM compared to the NP-type and PN-type in terms of On/Off ratio and retention time. However, regarding the retention time for Data '0', the NN-type and PP-type exhibit significantly inferior characteristics compared to the NP-type and PN-type (Fig. 6). At this point, before merely claiming that a homogeneous case shows superior characteristics, methods to compensate for the insufficient retention characteristics in the respective devices should be discussed.

 Response 5: Thank you for your response. We agree that the retention time for data ‘0’ of the NN- and PP-type cells is shorter than that of the NP- and PN-type cells, as shown in Figure 6. However, in a 2T0C DRAM array, the refresh window (t_REFW) is determined by the shorter of the retention times for data ‘1’ and data ‘0’. When considering t_REFW, the NP- and PN-type cells exhibit extremely small t_REFW values (< 1 ns) due to their severely degraded retention time for data ‘1’, making them unsuitable for CIM applications because they would require excessively frequent refresh operations and lead to substantial power consumption. In contrast, the NN- and PP-type cells provide t_REFW values that are orders of magnitude larger, enabling practical refresh operation with significantly lower refresh power than NP- and PN-type cells. Therefore, despite their shorter retention time for data ‘0’, the NN- and PP-type 2T0C DRAM cells are more suitable for CIM applications.

 

Comment 6. Parameters such as the on/off ratio and retention time can vary significantly depending on how the transistor off-state leakage current and threshold voltage are defined. Were these factors considered? If different criteria were used, please specify what they were. Please also include information on the read and write times.

 Response 6: Thank you for your comment. We agree that both the on/off current ratio and the retention time strongly depend on how the off-state leakage current and the threshold voltage (V_th) of the transistors are defined. As V_th of the read transistor increases, the on/off current ratio becomes larger, and as V_th of the write transistor increases, the off-state leakage current decreases, resulting in a longer retention time. Although a higher on/off current ratio and longer retention time are favorable, excessively increasing V_th restricts proper write and read operations. Therefore, considering the operating conditions—WWL voltages (1.5 V/0 V), WBL voltages (1 V/0 V), and the read voltage of 0.4 V—we designed the NMOS and PMOS transistors to have V_th values of 0.29 V and -0.30 V, respectively, to ensure reliable write and read operations.

 

Comment 7. The conclusions are derived under the specific conditions of Si 65 nm 2T0C DRAM, characterized by small storage-node capacitance and relatively high subthreshold hole leakage. These characteristics do not apply to oxide-semiconductor devices such as IGZO or SnO, which exhibit much lower leakage and operate under different bias and scaling conditions. It would be appropriate for the authors to clarify or explicitly limit the applicability of their conclusions to Si-based devices. Separating or revising the OSFET-related discussion could also help prevent misinterpretation of the study’s scope.

 Response 7: Thank you very much for your comment. We agree that the analysis presented in this work cannot be directly applied to oxide-semiconductor FET (OSFET)-based 2T DRAM structures because they exhibit fundamentally different leakage behavior and operate under different biasing conditions. Accordingly, we have revised Conclusion to explicitly state that our findings are limited to silicon channel-based 2T DRAM.

(Conclusion) “This work is anticipated to make a significant contribution to not only the analysis of silicon channel-based 2T DRAM but also OSFET-based 2T DRAM.”

Author Response File: Author Response.pdf

Reviewer 2 Report

Comments and Suggestions for Authors

Overall, this work is interesting and worthy of further investigation. The reviewer recommends the publication of this manuscript, while also suggesting that several issues should be addressed.

1. The paper focuses on the timing of write and read operations. However, CIM (Computing-In-Memory) applications often involve frequent and repetitive computations. It is recommended to include multi-cycle read/write simulations, supplement performance degradation testing after repeated read/write cycles, quantify the degradation in retention time and switching ratio, and compare the endurance differences between NN/PP and NP/PN types.
2. The figures do not indicate the data error range or confidence intervals. It is recommended to provide this information.
3. The paper uses an equivalent RC model to explain VSN fluctuations, which is overly qualitative. A sensitivity analysis could be added to quantify the contribution of each capacitor.
4. The y-axis current in Figure 3 shows a value of over 100 A. If the device can indeed output such a high current, this would be extremely dangerous. Please further verify the value and units.

Author Response

Comment 1. The paper focuses on the timing of write and read operations. However, CIM (Computing-In-Memory) applications often involve frequent and repetitive computations. It is recommended to include multi-cycle read/write simulations, supplement performance degradation testing after repeated read/write cycles, quantify the degradation in retention time and switching ratio, and compare the endurance differences between NN/PP and NP/PN types.

 Response 1: Thank you for your response. Since the planar 2T0C DRAM is fabricated using a CMOS process, it is expected to exhibit virtually permanent endurance similar to logic transistors and commercial DRAM. Therefore, the impact of repetitive read/write operations is considered negligible in CIM applications.

 

Comment 2. The figures do not indicate the data error range or confidence intervals. It is recommended to provide this information.

 Response 2: Thank you for your comment. The data presented in this work are obtained from deterministic TCAD simulations; therefore, no statistical error or confidence interval exists.

 

Comment 3. The paper uses an equivalent RC model to explain VSN fluctuations, which is overly qualitative. A sensitivity analysis could be added to quantify the contribution of each capacitor.

 Response 3: Thank you for your comment. To quantitatively clarify the contribution of each coupling component to V_SN fluctuation, we performed a sensitivity analysis of the capacitive components connected to the storage node (SN). As shown in Table A, the capacitances between SN and WWL (C_SN-WWL), WBL (C_SN-WBL), RWL (C_SN-RWL), RBL (C_SN-RBL), and Body (C_SN-Body) were extracted using TCAD simulation. Since C_SN-Body includes C_OX of the read transistor along with depletion and junction capacitances, and TCAD does not provide C_OX separately, C_OX was calculated using  .

 Figure A presents the coupling ratios, defined as the ratios of C_SN-WWL, C_SN-WBL, C_SN-RWL, C_SN-RBL, and C_SN-Body to total C_SN. This metric directly represents the sensitivity of V_SN to each node. For the NN-type cell, C_SN-RWL shows a coupling ratio of 26.47 %, while for the PP-type cell, C_SN-RBL exhibits 23.12 %. These results explain why V_SN is coupled up or down, respectively, during a read pulse, as shown in Figures 8(b) and 9(b) of the manuscript.

 In addition, C_OX contained within C_SN-Body plays a critical role in determining the amplitude of ΔV, as shown in Figures 8(c) and 9(c). The coupling ratios of C_SN-Body are 14.93 % (NN-type) and 23.75 % (PP-type), indicating that the body node also provides a significant contribution to V_SN fluctuation.

 Overall, this quantitative sensitivity analysis shows that C_SN-RWL (NN-type), C_SN-RBL (PP-type), and C_OX are the dominant contributors to V_SN fluctuation after the read pulse, and that the magnitude of the fluctuation interval directly follows their coupling strengths.

 

Table A. Capacitive components in the NN- and PP-type 2T0C DRAM unit cells.

Figure A. Coupling ratios between SN and WWL, WBL, RWL, RBL, and Body in the (a) NN- and (b) PP-type 2T0C DRAM unit cells.

 

Comment 4. The y-axis current in Figure 3 shows a value of over 100 A. If the device can indeed output such a high current, this would be extremely dangerous. Please further verify the value and units.

 Response 4: Thank you for your recommendation. We noticed that the y-axis unit in Figure 3 was mistakenly labeled as ‘A’ instead of ‘μA’, and this has been corrected in the revised manuscript.

Figure 3. Transfer characteristics of NMOS and PMOS transistors with V_th of 0.29 V and -0.30 V, respectively.

Author Response File: Author Response.pdf

Round 2

Reviewer 1 Report

Comments and Suggestions for Authors

Good work.

Reviewer 2 Report

Comments and Suggestions for Authors

This manuscript can be accepted.