A Novel Strategy for Preventing Commutation Failures During Fault Recovery Using PLL Phase Angle Error Compensation

Abstract

Existing studies on commutation failure during fault recovery (CFFR) in line-commutated converter high-voltage direct current (LCC-HVDC) systems often neglect the critical influence of phase-locked loop phase tracking error (PLL-PTE) and fail to provide effective control strategies to address this issue. This paper investigates the influence of PLL-PTE on CFFR through electromagnetic transient simulations based on a modified CIGRE benchmark model. The study reveals that phase angle jump (PAJ) caused by DC power fluctuations (DPF) and AC network reconfigurations (ANR) is the fundamental source of PLL-PTE, which in turn leads to the occurrence of CFFR. To mitigate this, a novel control strategy is proposed that dynamically adjusts the extinction angle based on historical and predicted PAJ data. Simulation results demonstrate that the proposed method effectively suppresses CFFR under various fault conditions, including different fault types, locations, resistances, and initiation times. Compared with existing control schemes, the proposed approach avoids adverse side effects while exhibiting strong robustness and adaptability. The proposed control strategy significantly enhances the stability and reliability of LCC-HVDC systems, offering great potential for practical application in increasingly complex power grid environments.

1. Introduction

Line-commutated converter-based high-voltage direct current transmission (LCC-HVDC) has been widely deployed for long-distance and bulk power transfer due to its economic and technical advantages [1,2]. However, the commutation process in LCC-HVDC is inherently dependent on the availability and quality of the AC system voltage. When AC faults occur, the distortion or depression of the AC voltage may cause commutation failures (CFs), leading to DC current extinction, system oscillations, and even severe power outages. In particular, commutation failure during fault recovery (CFFR)—the occurrence of CF after fault clearance—has emerged as a critical challenge that hampers the reliability and recovery speed of LCC-HVDC systems [3,4,5].

Existing research has extensively explored the mechanisms and mitigation strategies of CFs, with a predominant focus on external electrical disturbances such as AC voltage dips [6], reactive power shortages [7], or controller interactions [8]. However, limited attention has been paid to the intrinsic role of the Synchronous Reference Frame Phase-Locked Loop (SRF-PLL), which is widely used in existing LCC-HVDC projects and is responsible for the synchronization and control of the thyristor firing angle [9,10,11]. In fact, during and after AC faults, severe DC power fluctuations (DPF) and AC network reconfigurations (ANR) often lead to PLL phase tracking errors (PLL-PTE), which can persist even after the AC voltage waveform has visibly recovered. Despite the apparent restoration of normal system conditions, these errors result in inaccurate thyristor triggering and significantly increase the likelihood of CFFR. Multiple commutation failures in a short period might force the converter to block, resulting in a severe power deficit in the receiving-end system. For example, the blocking of inverter stations caused by commutation failure in the East China Power Grid in 2013 [9] led to a 4530 MW power deficit, leading to a sharp drop in system frequency. Therefore, preventing CFFR is necessary for system operation stability.

While the adverse impact of PLL-PTE on thyristor firing accuracy has been acknowledged, limited research has systematically investigated its root causes and effective mitigation strategies. Some studies have proposed new types of PLL technologies, or correction strategies based on tracking deviations. Refs. [11,12,13] compared and summarized the advantages and disadvantages of various new types of PLL technologies. Ref. [13] pointed out that the SRF-PLL performs well in power grids without harmonics, but tends to become unstable when the three-phase voltage contains harmonic components. However, two typical new PLL technologies, namely moving average filter PLL(MAF-PLL) and cascaded delayed signal cancellation PLL(CDSC-PLL), also have shortcomings. When phase jumps occur, both the frequency overshoot and the peak phase error of the MAF-PLL measurement results are higher than those of the SRF-PLL (by approximately 50%); in contrast, the filtering capability of the CDSC-PLL decreases as the harmonic amplitude increases, and it cannot completely avoid the risk of instability. Ref. [14] added a frequency positive sequence extraction module in addition to the cascaded delayed signal cancellation. It can be seen from this that new PLLs require the addition of extra control modules, such as the sliding window of MAF and the cascaded delay unit of CDSC. This not only necessitates the reconstruction of hardware interfaces but also increases the order of state equations [12] that need to be established during parameter tuning. At present, SRF-PLL has been widely used in the existing high-voltage direct current (HVDC) transmission systems in operation [12]. If new PLLs are adopted to replace SRF-PLL, additional costs may be incurred, including hardware modification, software upgrading, and parameter retuning.

Therefore, the scheme of correction strategies based on tracking deviations is more suitable for practical engineering applications. Ref. [15] observed that DC current dips from rectifier-side AC system (RS) faults can trigger phase angle jumps (PAJ) at the inverter-side commutation bus (ISB), indirectly contributing to CF. However, these studies often regard PLL-PTE as a localized control deficiency, without adequately accounting for its systemic coupling with broader power system dynamics—particularly DPF and ANR.

In this context, this paper identifies PLL-PTE as the core dynamic driver of CFFR, rather than merely a consequence of voltage disturbances. Building upon this insight, the mechanisms through which DPF and ANR trigger CFFR are thoroughly investigated. Furthermore, a novel CFFR prevention strategy is proposed, incorporating PLL-PTE prediction and adaptive firing angle adjustment. The major contributions of this paper are as follows:

1. This work reveals that PLL-PTE is not merely a consequence of AC voltage disturbances but a critical driver of CFFR, especially under post-fault conditions. It further identifies DPF and ANR as the root causes of PLL-PTE, and investigates the mechanism that triggers CFFR. The relationships among various influencing factors could be illustrated as Figure 1.

2. A novel control strategy is proposed, which incorporates PLL-PTE prediction and adaptive firing angle adjustment. Case studies conducted in PSCAD using the modified CIGRE LCC-HVDC benchmark model have validated its effectiveness and generalizability.

The remainder of this paper is organized as follows. Section 2 investigates the underlying mechanisms leading to CFFR. Section 3 presents the proposed control strategy for CFFR prevention. Section 4 provides simulation-based validation using PSCAD. Conclusion was drawn in Section 5.

2. Investigation of the Leading Influence of PLL-PTE on CFFR

2.1. Mechanism of CF in LCC-HVDC Systems

CF is a common fault in LCC-HVDC. It occurs when the thyristors in the converter station fail to regain their blocking capability after being turned off, which requires the application of a reverse voltage for a sufficient duration to achieve deionization. This required reverse voltage period is typically characterized by the extinction angle γ, and a minimum value of 7.2° is generally regarded as the critical threshold for successful turn-off, as shown in (1). If γ falls below this threshold, a CF will occur [16,17].

$${\gamma }_{\min }=7.2°$$

(1)

γ can be calculated by (2), where I_d is the DC current, X_r is the transformer leakage reactance, U_LL is the RMS value of the AC line to line voltage, and β is the advance firing angle. According to (2), a larger I_d and a lower U_LL will result in a smaller γ. Therefore, during AC faults, the increase in DC current and the drop in AC voltage jointly contribute to the reduction in γ, which in turn increases the risk of commutation failure. Consequently, many studies have focused on mitigating CF through DC current suppression or AC voltage compensation. Figure 2 illustrates the CF mechanism (adapted from [6,7,8]).

$$\gamma =\arccos ({\displaystyle \frac{\sqrt{2}n{I}_d{X}_r}{U_{LL}}}+\cos \beta )$$

(2)

However, existing studies generally overlook the critical impact of PLL-PTE. As the core component for synchronization and firing angle control in LCC-HVDC systems, the SRF-PLL directly determines the accuracy of the firing angle β. During and after AC faults, DPF and ANR may prevent the PLL from accurately tracking the actual phase of AC voltage, resulting in significant phase leads or lags. For example, in the CIGRE LCC-HVDC BENCHMARK model (SCR = 2.5), when an over-resistance fault of 1 Ω occurred at the inverter commutation bus with a fault duration of 0.1 s, the PLL-PTE reached 52.7° after the fault, ultimately leading to the occurrence of CFFR. Unlike voltage magnitude, PLL-PTE does not disappear immediately after fault clearance; instead, it often persists during the post-fault recovery stage, leading to miscalculated firing angles, as shown in Figure 3. Consequently, commutation failures may occur even when the extinction angle γ is theoretically sufficient, explaining the frequent occurrence of CFFR under seemingly normal conditions.

This paper identifies that PLL-PTE mainly originates from PAJ, which are induced by DPF and ANR under fault conditions. The mechanisms by which DPF and ANR lead to PAJ, and subsequently cause PLL-PTE, are elaborated in Section 2.2 and Section 2.3.

2.2. Mechanism of PLL-PTE Induced by PAJ

The SRF-PLL is the widely adopted phase synchronization unit in LCC-HVDC systems due to its high steady-state accuracy and dynamic response [9]. As illustrated in Figure 4, it operates by transforming the three-phase AC voltage into a synchronous rotating reference frame (dq frame), where the q-axis voltage ideally reaches zero when synchronization is achieved. A PI controller adjusts the oscillator frequency to minimize the q-axis voltage, enabling accurate tracking of the input voltage phase. In the steady state, the SRF-PLL synchronizes accurately with the system voltage, with the estimated phase angle matching the actual phase angle, as expressed in (3).

$$\widehat{\theta }=\theta$$

(3)

However, the PI controller parameters of the SRF-PLL are typically tuned for nominal operating conditions, resulting in inadequate dynamic performance under transient conditions [18]. During dynamic disturbances, especially fault conditions, the distortion components introduced in the system voltage waveform hinder the q-axis voltage from converging effectively to zero. Consequently, the PLL output $\widehat{\theta }$ fails to accurately track the actual voltage phase θ, giving rise to a PLL-PTE.

The occurrence of PLL-PTE can also be interpreted using the small signal model of SRF-PLL (as shown in Figure 5) and corresponding step response (as shown in Figure 6). As can be seen from Figure 5, this paper implements ideal linearization of the PLL small-signal model. The error between the linearized PLL small-signal model and the nonlinear model is within an acceptable range (less than 10%), and the calculated result of PLL-PTE based on the linearized model is higher than that of the nonlinear model (as shown in Figure A1). Compensation based on this result can provide a higher operating margin.

As depicted in Figure 6, when a fault occurs at t = 0, causing a PAJ, the integral nature of the SRF-PLL cannot promptly follow the phase change. This results in a mismatch between the actual firing angle α_act and order firing angle α_ord of the thyristor valves in the LCC-HVDC system. In such cases, the α_act becomes smaller than the α_ord, which is beneficial for mitigating CF. However, since the primary factor triggering CF during the fault is the reduced AC voltage magnitude, the potential benefit of a negative PLL-PTE cannot be fully realized. After the fault is cleared at t = T_f, θ rapidly returns to its pre-fault value. At this point, a positive PLL-PTE emerges, typically ranging from 10° to 60°, with the upper bound reaching up to four times the typical commutation margin of an LCC-HVDC inverter. Such a large positive PLL-PTE causes the α_act to exceed the α_ord, which significantly compresses the commutation margin of the thyristor valves, increasing the risk of CFFR. This phenomenon can be expressed by Equation (4).

$$\left\{\begin{array}{l}During Fault : \theta -\widehat{\theta }<0\Rightarrow {\alpha }_{act}<{\alpha }_{ord}\Rightarrow \gamma >{\gamma }_{\min }\\ After Fault : \theta -\widehat{\theta }>0\Rightarrow {\alpha }_{act}>{\alpha }_{ord}\Rightarrow \gamma <{\gamma }_{\min }\end{array}\right.$$

(4)

Following AC faults at either RS or inverter-side AC system (IS), DPF and ANR jointly induce a PAJ, which inevitably gives rise to PLL-PTE. The mechanisms underlying DPF and ANR are detailed in Section 2.3.

2.3. Mechanism of PAJ After AC Fault Clearance

The IS network difference after AC fault clearance can be typically modeled as Thevenin equivalent circuit, as shown in Figure 6. The PAJ can be illustrated by the phasor representation of voltages in equivalent system, as shown in Figure 7. Considering AC fault location is close to commutation bus of LCC and far from the equivalent generator, the voltage magnitude (E_eq) and phase angle (θ_eq) of equivalent generator remain unchanged during fault clearance.

According to the fundamental concept of PAJ, it is defined as the phase angle difference during the fault (Ȗ_{LCC_f}) and after fault recovery (Ȗ_LCC), as shown in Figure 7. Since it is practically challenging to directly measure the phase angle difference in the same electrical quantity at different time instants in engineering applications, this measurement should be converted into calculable angle from other electrical quantities by trigonometric functions. Due to the minimal change in equivalent voltage source of IS network (Ȇ_eq) during the fault and after fault recovery, it is preferable to compute PAJ using the angles between Ȇ_eq and other electrical quantities. As illustrated in Figure 7, PAJ can be derived by adding the angle difference between the voltage of fault point (Ȗ_f) and Ȇ_eq to the angle difference between Ȗ_LCC and Ȇ_eq, and then subtracting the angle difference between Ȗ_{LCC_f} and Ȗ_f, as shown in Equation (5):

$${\theta }_{PAJ}=\arg \left({\displaystyle \frac{{\stackrel{⌢}{U}}_{LCC}}{{\stackrel{⌢}{U}}_{LCC\_f}}}\right)=\arg \left({\displaystyle \frac{{\stackrel{⌢}{U}}_{LCC}}{{\stackrel{⌢}{E}}_{eq}}}\right)+\arg \left({\displaystyle \frac{{\stackrel{⌢}{E}}_{eq}}{{\stackrel{⌢}{U}}_f}}\right)-\arg \left({\displaystyle \frac{{\stackrel{⌢}{U}}_{LCC\_f}}{{\stackrel{⌢}{U}}_f}}\right)$$

(5)

Based on the fundamental principles of voltage drop and power loss in electric power transmission components, the phase difference between Ȗ_LCC and Ȇ_eq shown in Figure 8, satisfies Equations (6) and (7). Considering the inductance is much larger than resistance (in 110 kV transmission line, inductance is 10–50 times larger than resistance) and active power is much larger than reactive power in practical system (if power factor is 0.95, reactive power is about 10% of active power), ΔU_LCC (during normal operation, the voltage magnitude difference between the two ends of transmission lines above 110 kV is usually very small, generally within the range of 2–5% of the rated voltage) and Q_acR_eq in δU_LCC can be ignored, Equation (8) can be derived as shown below:

$$\mathrm{\Delta }{U}_{LCC}={\displaystyle \frac{P_{LCC}{R}_{eq}+Q_{LCC}{X}_{eq}}{U_{LCC}}}$$

(6)

$$\delta U_{LCC}={\displaystyle \frac{P_{LCC}{X}_{eq}-Q_{LCC}{R}_{eq}}{U_{LCC}}}$$

(7)

$$\arg \left({\displaystyle \frac{{\stackrel{⌢}{U}}_{LCC}}{{\stackrel{⌢}{E}}_{eq}}}\right)=\arctan \left[{\displaystyle \frac{\delta U_{LCC}}{U_{LCC}-\mathrm{\Delta }{U}_{LCC}}}\right]\approx \arctan \left({\displaystyle \frac{P_{LCC}{X}_{eq}}{{\left|{\stackrel{⌢}{U}}_{LCC}\right|}^2}}\right)$$

(8)

where X_eq = X₁ + X₂. Similarly, the phase difference between Ȗ_{LCC_f} and Ȗ_f during the fault can be express as Equation (9):

$$\arg \left({\displaystyle \frac{{\stackrel{⌢}{U}}_{LCC\_f}}{{\stackrel{⌢}{U}}_f}}\right)=\arctan \left({\displaystyle \frac{P_{LCC\_f}{X}_1}{{\left|{\stackrel{⌢}{U}}_{LCC\_f}\right|}^2}}\right)\approx 0$$

(9)

Based on the LCC operation characteristic, the DC voltage U_{dc_I} can be calculated:

$$U_{dc\_I}=N({\displaystyle \frac{3\sqrt{2}\left|{\stackrel{⌢}{U}}_{LCC}\right|}{\pi }}\cos \alpha -{\displaystyle \frac{3X_r{I}_{dc}}{\pi }})$$

(10)

According to Equation (10), the fault on the IS results in a decrease in DC voltage and power. Moreover, the sharp voltage dip at the IS often leads to the first commutation failure (FCF). From the converter’s perspective, FCF is equivalent to the formation of a short-circuit path within the converter bridge, resulting in nearly zero power being delivered. This process is illustrated in Figure 9, where red arrows indicate the direction of current flow, red-colored thyristors represent conducting devices, and solid lines represent current paths. According to Equation (9), the phase difference between Ȗ_{LCC_f} and Ȗ_f during the fault can be ignored.

Furthermore, considering the active power injected to the fault point from LCC is nearly zero, the magnitude of current |Ȋ_{LCC_f}| shown in Figure 7 can also be considered as zero. It is known that the closer the electrical distance between the fault point and the PCC, the more likely commutation failure is to occur. Thus, in this mechanism analysis, assuming that X₁ is relatively small and close to zero, the voltage magnitude drops from |Ȗ_{LCC_f}| to |Ȗ_f| is almost zero. Therefore, the voltage phaser shown in Figure 8 satisfies Equation (11).

$$\arg \left({\displaystyle \frac{{\stackrel{⌢}{E}}_{eq}}{{\stackrel{⌢}{U}}_f}}\right)=\arccos \left({\displaystyle \frac{\left|{\stackrel{⌢}{U}}_f\right|}{\left|{\stackrel{⌢}{E}}_{eq}\right|}}\right)\approx \arccos \left({\displaystyle \frac{\left|{\stackrel{⌢}{U}}_{LCC\_f}\right|}{\left|{\stackrel{⌢}{E}}_{eq}\right|}}\right)$$

(11)

Combining Equations (8), (9) and (11) into Equation (5), Equation (5) can be rewritten as Equation (12):

$${\theta }_{PAJ}=\underset{\mathrm{Part} \mathrm{I}}{\underbrace{\arctan \left({\displaystyle \frac{P_{LCC}{X}_{eq}}{{\left|{\stackrel{⌢}{U}}_{LCC}\right|}^2}}\right)}}+\underset{\mathrm{Part} \mathrm{II}}{\underbrace{\arccos \left({\displaystyle \frac{\left|{\stackrel{⌢}{U}}_{LCC\_f}\right|}{\left|{\stackrel{⌢}{E}}_{eq}\right|}}\right)}}$$

(12)

From Equation (12), it is obvious that the PAJ during the fault clearance contains two parts. Part I is caused by the active power recovery when the fault is cleared. Ignoring the commutation loss in LCC, the active power output of LCC is equal to the DC active power injection. The AC faults in both the RS and IS system can cause PAJ, the restoration of DC power after fault clearance leads to a sudden phase shift in Ȗ_LCC. It can be seen that the greater variation in the restored DC power after fault clearance, the larger value of Part I of PAJ.

Moreover, a lower magnitude of Ȗ_{LCC_f} during the fault results in a higher value of Part II of PAJ. This relationship is primarily determined by the fault location and fault resistance, summarizing the influence of ANR on PAJ during fault conditions.

This abrupt phase shift is directly reflected in the input of the SRF-PLL, leading to a transient disturbance. Due to its limited dynamic response, the SRF-PLL is unable to accurately and promptly track the voltage phase, thereby resulting in a significant PLL-PTE.

3. Proposed Strategy for Preventing CFFR

3.1. Overall Control Strategy and Its Advantages

In LCC-HVDC systems, PAJ caused by AC system faults can induce significant PLL-PTE, which in turn affect the firing angle control of the converter and may trigger CFFR. Based on the small-signal model of SRF-PLL as shown in Figure 5, the PLL-PTE caused by θ_PAJ could be derived in Equations (13) and (14).

$$\mathrm{\Delta }{\theta }_{PLL}(s)={\displaystyle \frac{s^2}{s^2+K_{p}s+K_i}}\theta (s)={\displaystyle \frac{s(1-e^{-T_{f}s})}{s^2+K_{p}s+K_i}}{\theta }_{PAJ}$$

(13)

$$\left\{\begin{array}{l}{(\mathrm{PLL}-\mathrm{TE})}_{\max }=\mathrm{\Delta }{\theta }_{PLL}(T_f)={\theta }_{PAJ}({\displaystyle \frac{P_1}{P_1-P_2}}{e}^{P_1{T}_f}-{\displaystyle \frac{P_2}{P_1-P_2}}{e}^{P_2{T}_f}-1)\\ P_{1,2}=-{\displaystyle \frac{K_p}{2}}\pm j\sqrt{{\displaystyle \frac{4K_i-K_p^2}{4}}}\end{array}\right.$$

(14)

Based on the analysis of the voltage phase variations in Section 2 and the small-signal analysis, the PLL-PTE value can be calculated and compensated into the LCC firing angle feedback control, thereby achieving suppression of secondary commutation failures during fault clearance. The proposed method introduces a rational control structure to compensate for PLL-PTE and effectively mitigate the risk of CFFR. The structure of the proposed control strategy is illustrated in Figure 10 and Figure 11. As shown in Figure 10, the proposed control strategy compensates the operation margin of γ by reducing the α of LCC inverter. And the compensation control signal is generated by the mechanism shown in Figure 11.

As shown in Figure 11, the real-time measured data required for the ACC control loop is |U_LCC|; U_{LCC_N} and E_eq are steady-state operating values, which can be obtained by big data recording or adopted as the system rated values (constant values). The preset threshold of the ACC is set to 0.9 p.u. U_{LCC_N} to avoid false triggering of the ACC caused by small-range fluctuations of U_LCC. Similarly, the real-time measured data required for the DCC control loop is P_DCI; X_eq is the system equivalent impedance value, which can be acquired through real-time big data analysis or adopted as the constant equivalent impedance value under the worst-case scenario (three-phase low-impedance ground fault at the PCC point). The preset threshold of the DCC is set to 0.1 p.u. P_{DCI_N} to prevent false triggering of the DCC due to small-range fluctuations of P_DCI or active power adjustment of the LCC. The discussion on big data analysis and calculation is relatively complex; due to space constraints of this paper, the effectiveness of the proposed control strategy is prioritized for verification, and constant values are adopted as the steady-state operating values in all PSCAD simulation case studies.

The required real-time measured data, |U_LCC| and P_DCI are internal electrical quantities for real-time monitoring during the normal operation of the LCC station [19]. Though there is no communication delay, considering the signal processing delay, a 16 ms delay processing element is added to the real-time measured electrical quantities during simulation, as shown in Figure A2.

Compared with existing methods, the proposed strategy offers the following advantages:

1. It explicitly models the two primary sources of PLL-PTE and implements targeted compensation, effectively addressing the root causes of CFFR.

2. Through intuitive trigonometric relationships to calculate θ_PAJ and based on small-signal analysis to derive the PLL-PTE value, the overall control structure does not include the integral component. This avoids complex parameter tuning experiments in engineering applications and reduces the time and labor costs for modification and optimization.

3. The controller utilizes locally measurable variables such as |Ȗ_LCC| and P_dcI, which provide high accuracy and are well-suited for practical engineering implementation.

The control principles of the controller shown in Figure 11 will be introduced in Section 3.2 and Section 3.3.

3.2. ANR Compensation Controller (ACC)

This sub-controller is designed to compensate for PLL-PTE caused by ANR.

In practical engineering applications, measuring the voltage at the fault point and the fault resistance is challenging, and accuracy needs improvement. Based on the analysis in Section 2, it can be observed that during a fault, the active power output from the LCC is significantly limited, and the active power transfer and AC current between the ISB and the fault point are essentially zero. As a result, the magnitude and phase of ISB voltage are approximately consistent with the fault point. Therefore, the control strategy proposed in this paper employs U_LCC as the measured electrical quantity and trigger signal for the ACC. If U_LCC is below the rated value, the ACC compensation control is activated. Based on Equation (12) and the measured values of U_LCC and E_eq (which could be considered as constant), the value of θ_PAJ Part I is calculated, effectively compensating for the PLL-PTE value caused by ANR after fault clearance according to the severity of voltage sag.

3.3. DPF Compensation Controller (DCC)

This sub-controller is designed to compensate for PLL-PTE caused by DPF.

Based on the analysis in Section 2, the fundamental principle of Part II of θ_PAJ caused by DPF is the sudden restoration of active power delivered from the ISB to IS network after fault clearance., which leads to a phase jump in PCC voltage. Therefore, the compensation value for the firing angle should be based on the active power variation. Given that the fault duration is typically within 0.1 s [4], the proposed control strategy calculates Part II of θ_PAJ based on the increase in active power within 0.1 s. Considering that the proposed control targets the restoration of active power after fault clearance, the per-unit value of active power variation is limited to [0, 1]. During the steady-state operation, the variation in active power is essentially zero, thus ensuring that the SSO of LCC system remains unaffected. Additionally, this control strategy can also mitigate commutation failures caused by a sudden surge in LCC active power during the AC fault recovery in the RS.

4. Case Studies and Validation

This section presents validation studies performed using the electromagnetic transient simulation platform PSCAD/EMTDC based on the modified CIGRE LCC-HVDC Benchmark model. The critical influence of PLL-PTE on CFFR, the effectiveness of the proposed control strategy, and its general applicability are evaluated sequentially.

4.1. Test System

The simulation model used for validation is based on a modified CIGRE LCC-HVDC Benchmark system, as shown in Figure 12. In the original model, both RS and IS are represented by Thevenin equivalent circuits. To enable fault placement at different distances from the commutation bus along overhead transmission lines, the Thevenin equivalent circuits are replaced with physical transmission lines characterized by an impedance of 0.0529 + j0.529 (Ω/km) in both Model I and Model II. And the voltage level of both Models remains unchanged (230 kV).

Model I (SCR = 2.42) and Model II (SCR = 2.69) reflect different AC system configurations at the receiving end. These structures are designed to induce varying PLL-PTE at the ISB during AC system faults. Specifically, Model II includes a load of L₁ = 2000 MW placed at a specified distance from the inverter bus. To maintain the voltage level at ISB, shunt capacitors C₁ = 15.45 μF and C₂ = 18.05 μF are installed at the ISB and the load node, respectively. Next, by comparing the PLL-PTE of different power grid topologies during fault recovery, it is demonstrated that PLL-PTE is the root cause of CFFR.

4.2. Validation of the Critical Role of PLL-PTE

This subsection validates the hypothesis that PLL-PTE is a critical factor in the occurrence of CFFR. Based on the test system shown in Figure 12, a three-phase AC fault is imposed at the ISB of Model I and Model II under varying transition resistances R_f, ranging from 0 to 200 Ω in steps of 20 Ω. The maximum PLL-PTE and the corresponding occurrence of both Model I and Model II are summarized in

Table 1. PLL-PTE and CFFR Occurrence under Various R_f.

Transition Resistance (Ω)	PLL-PTE (deg)		CFFR		γmin (deg)
	Model I	Model II	Model I	Model II	Model I	Model II
1	55.7	37.7	Yes	No	0	21
20	41.7	26.7	Yes	No	0	14.9
40	33.5	19.2	Yes	No	0	17.2
60	28.5	14.9	Yes	No	0	8.8
80	25.1	14.0	Yes	No	0	12.5
100	21.4	13.5	Yes	No	0	11.3
120	20.0	12.6	Yes	No	0	11.4
140	18.9	12.0	Yes	No	0	13.3
160	17.1	11.0	Yes	No	0	12.9
180	16.5	10.9	No	No	7.3	14.4

.

As shown in Table 1, there are significant differences in the PLL-PTE values and the occurrence of CFFR between Model I and Model II under different fault resistance values. This further highlights the decisive role of PLL-PTE in CFFR. Under the same fault conditions, Model I experiences larger PLL-PTE and thus suffers from CFFR, whereas no CFFR is observed in any of the cases for Model II. Furthermore, for Model I, as R_f increases, the fault severity gradually decreases and the PLL-PTE correspondingly reduces. When R_f = 180 Ω, CF does not occur. These findings demonstrate that large PLL-PTE is the direct cause of CFFR, which confirms the theoretical analysis in Section 2. After the theoretical analysis in this paper is verified, Section 4.3, Section 4.4, Section 4.5 and Section 4.6 will further demonstrate the effectiveness of the proposed control strategy under various scenarios.

4.3. Validation of the Proposed Controller’s Effectiveness Under Varying Fault Type

This subsection evaluates the effectiveness of the proposed controller using Case 1 and Case 2, as shown in Figure 13. Three control strategies are compared: the conventional CIGRE controller (Method 1) [20], the controller proposed in (Method 2) [21], and the controller proposed in this paper (Method 3).

Case 1: At t = 2.0 s, a three-phase-to-ground fault occurs at the RSB of model I with R_f =1 Ω. The fault is cleared at t = 2.1 s.

Case 2: At t = 2.0 s, a three-phase-to-ground fault occurs at the ISB of model I with R_f =1 Ω. The fault is cleared at t = 2.1 s.

The corresponding simulation results are presented in Figure 14, and the key observations are summarized as follows:

As shown in Figure 14(a1), Method 1 results in CFFR when the fault is cleared at RS, where γ_mea drops to 0° at 2.26 s. In contrast, Method 2 maintains γ_mea above 12° (minimum value is 12.43°), and Method 3 keeps it above 9° (minimum value is 9.55°) after fault clearance. This is because Method 1 does not account for the decisive impact of PLL-PTE on CFFR. After fault clearance, PLL-PTE causes the actual firing angle to exceed the reference firing angle α_ord, leading to CFFR. In Figure 14(a2), the I_dc of Method 1 surges over 4 kA at 2.26 s while Method 2 and 3 can sustain I_dc at roughly 2 kA after 2.3 s. This also indicates that the adaptive extinction angle control strategy in Method 2 and the proposed strategy in Method 3 could avoid CFFR after fault clearance, and thereby prevent the overcurrent problem after fault is cleared. Method 2 increases the γ_ord in CEA control in LCC shown in Figure 10 to enlarge the thyristor commutation margin. Similarly, Method 3 directly reduces α_ord to enhance the commutation margin, preventing CFFR. In Case 1, Method 2 could provide larger commutation margin than Method 3 (12.43° > 9.55°), but the steady-state value of γ_mea in Method 2 after fault clearance is 5° higher than its pre-fault operating value. This indicates that the compensation of Method 2 is not terminated promptly after fault recovery. In summary, under Case 1, Method 3 exhibits the optimal dynamic performance and effectively avoids CFFR.

As shown in Figure 14(b1), both Method 1 and Method 2 similarly result in CFFR from the three-phase fault at the IS: their γ_mea drop to 0° at 2.18 s. In contrast, Method 3 can successfully prevent CFFR (γ_mea above 15° throughout the process), allowing the system to smoothly resume stable operation after fault clearance. This demonstrates that Method 3 is applicable to both RS and IS AC faults. As can be seen from Figure 14(b1), the γ_mea of Method 2 (green line) and Method 1 (orange dotted line) become zero at 2.18 s, indicating that another commutation failure occurred after fault recovery. At 2.25 s, the γ_mea of Method 2 (39.83°) is larger than that of Method 1 (24.52°), demonstrating that Method 2 experienced a maloperation: it fails to trigger prior to the CFFR and subsequently resulted in an increased gamma angle after the CFFR action. In contrast, Method 3 effectively compensates PLL-PTE based on electrical parameters after fault clearance (γ_mea = 21.27° at 2.18 s, the minimum value is 14.4733°). In addition, in Figure 14(b2), both Method 1 and Method 2 will result in another DC overcurrent due to CFFR after fault clearance (Idc > 5 kA at 2.18 s). This also indicates that Method 3 is more accurate than Method 2, which solely relies on the post-fault commutation angle variation to activate compensation control. Consequently, Method 3 provides sufficient commutation margin and, as shown in Figure 14b, successfully prevents CFFR.

Furthermore, the simulation comparison results of asymmetric faults and faults with dynamic impedance changes are detailed in Appendix A Figure A3 and Figure A4. As can be seen from Figure A3 and Figure A4, under the same grounding impedance value, the voltage amplitude sag at the PCC caused by asymmetric faults and faults with dynamic fault impedance are smaller than that of three-phase ground faults. Since the control strategy proposed in this paper can suppress CFFR of three-phase ground faults, it can also be applied to asymmetric faults and faults with dynamic fault impedance scenarios. In conclusion, compared with existing methods, the proposed controller can effectively suppress CFFR and ensure stable system operation under variable fault scenarios. In addition to being able to apply to different fault types, the proposed control strategy is necessary to demonstrate its effectiveness under different levels of system strength, which will be illustrated in Section 4.4.

4.4. Validation of the Proposed Controller’s Effectiveness Under Varying System Strengths

This subsection aims to validate the effectiveness of the proposed method under varying system strength conditions illustrated in Figure 15, based on the simulation results of Cases 3–5 provided in Figure 16. Both the conventional CIGRE controller (Method 1) and the controller proposed (Method 3) are employed for comparative analysis.

Case 3: At t = 2.0 s, a three-phase-to-ground fault occurs at the ISB of Model I with a fault resistance of R_f = 0.1 and a short-circuit ratio (SCR) of 2.5, as shown in Figure 15a. This case also serves as a supplement to Case 2, demonstrating the effectiveness of the proposed method under extremely severe fault conditions.

Case 4: At t = 2.0 s, a three-phase-to-ground fault occurs at the ISB of Model I, with R_f = 0.1 and SCR = 2.0, as shown in Figure 15b.

Case 5: At t = 2.0 s, a three-phase-to-ground fault occurs at the ISB of Model I, with R_f = 0.1 and SCR = 5.0, as shown in Figure 15c.

As shown in Figure 16, all three cases experienced FCF when the severe three-phase-to-ground fault occurred at ISB. After fault clearance, Cases 3 and 4 experienced CFFR under the control of Method 1, where γ_mea dropped to 0° at 2.16 s in Case 3 and 2.15 s in Case 4, whereas Case 5 did not, with γ_mea maintaining above 15°. This is because Case 5 corresponds to a strong AC system, which provides better voltage support.

In contrast, under the control of Method 3, none of the three cases exhibit CFFR. In Case 3 (Figure 16(a2)), Method 3 keeps γ_mea above 12° (minimum value is 12.03°), and in Case 4 (Figure 16(b2)), it maintains γ_mea above 11° (minimum value is 11.52°), ensuring sufficient commutation margin for thyristor operation. In Case 4, as shown in Figure 16b, oscillations occur in the system after fault clearance, with γ_mea oscillating between 10–30° and I_dc fluctuating within 1.2 kA–2.2 kA, prolonging the time required for the system to return to stable operation (about 0.5 s later than Method 1). According to IEEE Std 1204-1997 [22], in practical engineering, the operation of systems with very low short-circuit ratio (SCR ≤ 2) must rely on fast static var compensators (SVCs) to maintain voltage stability. Case 4 is merely to verify the effectiveness of the proposed control strategy under extreme scenarios. Even if there is AC voltage oscillation, it can still suppress CFFR (I_dc is smaller than 1.2 p.u. of reference value). Compared with Case 3 and 5, it can be seen that the oscillations are caused by insufficient AC voltage support capability in the extreme weak system (SCR ≤ 2.0), not induced by the proposed control strategy. Adding additional reactive power compensation equipment can avoid the oscillation problem. In Case 5, according to Figure 16(c2,c4), after the fault clearance, both Method 1 (minimum value of γ_mea is 14.29°) and Method 3 (minimum value of γ_mea is 14.23°) can avoid CFFR. This demonstrates that in this scenario, the support capability of the ISB voltage can prevent CFFR, while the proposed method does not adversely affect successful commutation.

In conclusion, the proposed method proves effective in preventing CFFR across a wide range of system strength conditions, including very weak, weak, and strong systems. In order to further enhance the credibility of the effectiveness of the proposed control strategy, summary simulation results covering more scenarios are provided in Section 4.5.

4.5. Applicability Verification of the Proposed Controller

To further verify the adaptability and robustness of the proposed controller under various fault conditions, a series of simulation cases (Case 6 and Case 7) are conducted using Model I.

Case 6: Three-phase fault at the RS. The fault resistance R_f varies from 0 to R_{f_max}, the fault location distance D_f varies from 0% to 100%, and the fault duration T_f is set to 0.1 s or 0.05 s. Here, R_{f_max} denotes the maximum R_f at which CFFR still occurs under this fault condition.

Case 7: Three-phase fault at the ISB. R_f ranges from 0 to R_{f_max}, T_ini varies within one cycle, T_f = 0.05 s.

The simulation results are presented in Figure 17. Under various combinations of fault resistance, fault location, and initiation time, the proposed controller effectively prevents the occurrence of CFFR. Furthermore, in scenarios where the conventional CIGRE controller does not result in CF, the proposed controller similarly does not induce CF, indicating that it introduces no adverse side effects.

These findings demonstrate the proposed controller’s excellent generalizability and robustness across a wide range of fault conditions. It can reliably suppress CFFR, making it a highly promising control strategy for practical engineering applications in LCC-HVDC systems. Section 4.3, Section 4.4 and Section 4.5 present simulation results all based on an equivalent receiving-end system. In order to further verify that the proposed control strategy can be applied to actual large power grid systems, Section 4.6 will demonstrate the dynamic performance of the proposed control strategy in the IEEE 39-bus system.

4.6. Validation of the Proposed Controller’s Effectiveness in IEEE 39-Bus System

To further verify the proposed controller’s effectiveness in the large power grid system, three simulation cases (Case 8–Case 10) with different fault locations in classical IEEE 39-bus system (shown as Figure 18) are conducted.

Case 8: At t = 2.0 s, a three-phase-to-ground fault at Location A, with R_f = 10 Ω. The fault is cleared after 0.1 s.

Case 9: At t = 2.0 s, a three-phase-to-ground fault at Location B, with R_f = 1 Ω. The fault is cleared after 0.1 s.

Case 10: At t = 2.0 s, a three-phase-to-ground fault at Location C, with R_f = 1 Ω. The fault is cleared after 0.1 s.

As shown in Figure 19, the voltage sag levels in Case 8 and Case 9 are approximately the same (minimum value of |U_LCC| is 126.11 kV and 128.82 kV respectively). Therefore, as shown in (a3) and (b3) of Figure 19, the calculated results of PAJ using Method 3 are basically consistent. The PAJ reaches its maximum value (46.48° in Case 8 and 49.19° in Case 9) at around 2.1 s, increasing the commutation angle operating margin before fault clearance. After 2.1 s, due to the recovery of |U_LCC|, the PAJ drops rapidly (with a descending rate of 339.58°/s). Around 2.15 s, the DCC loop is activated by power recovery, maintaining the PAJ at approximately 15° for 0.4 s. Finally, the PAJ drops to 0 after 2.54 s, and Method 3 ceases to compensate for the LCC commutation angle operating margin. According to (a4), (a5), (b4) and (b5) of Figure 19, there is no sudden increase in I_dc of Method 3 after 2.1 s, and the γ_mea remains greater than 12°. It can be seen that the proposed control strategy can effectively suppress CFFR after fault clearance (after 2.1 s). That is, under the same level of |U_LCC| voltage sag, the proposed control strategy remains effective even when faults occur at different locations in the large-scale power grid.

It is worth noting that for Method 1 without additional control strategies, the closer the electrical distance between the fault point and the PCC, the more commutation failures occur during fault recovery (4 times in Case 8 and 1 time in Case 9), and the longer the post-fault system stabilization time (stabilization time of Case 8: 2.6 s > stabilization time of Case 9: 2.37 s).

Furthermore, the comparison between Case 9 and Case 10 shows that under the same grounding impedance (1 Ω), the farther the electrical distance between the fault point and the PCC, the smaller the magnitude of the PCC voltage sag (205.08 kV in Case 10 > 128.82 kV in Case 9). Therefore, neither Method 1 nor Method 3 experiences commutation failure after fault recovery in Case 10. In summary, if the proposed control strategy can effectively suppress CFFR of the most severe ground fault at the PCC, it will also be effective in other fault scenarios within the IEEE 39-bus power grid system.

5. Conclusions and Future Work

This paper has comprehensively analyzed the influence of PLL-PTE on the occurrence of CFFR in LCC-HVDC systems. Both theoretical insights and electromagnetic transient simulations confirm that large PLL-PTE is a decisive factor triggering CFFR, particularly in topologies with weak IS.

To mitigate this issue, a novel control strategy was proposed, incorporating phase-aware dynamic adjustments of extinction angle and firing angle references. All real-time measured electrical quantities required by this control strategy are real-time monitoring values during the operation of the converter station, eliminating the need for additional measurement equipment or communication systems. Furthermore, the proposed control strategy does not include an integral component, which reduces the parameter tuning experiment and software upgrade costs when practically applied to existing projects, demonstrating excellent engineering applicability.

Simulation studies demonstrate that this approach effectively suppresses CFFR across a wide range of fault types, including single-phase-to-ground faults, two-phase-to-ground faults, and three-phase-to-ground faults, as well as faults at the sending and receiving ends. Moreover, the proposed controller exhibits strong adaptability to variations in fault resistance, fault location, and fault initiation time. In addition, the proposed control strategy is also applicable to receiving-end systems with various grid strengths and large power grid systems. In a total of 131 simulation cases in this paper, the proposed control strategy can avoid CFFR in all cases, while the original LCC control strategy fails to prevent CFFR except in 25 of these cases. This indicates that the proposed control strategy can effectively enhance the ability of the LCC-HVDC system to resist CFFR.

In summary, the proposed control strategy significantly enhances the operational safety and stability of LCC-HVDC systems, preventing them from forced blocking due to multiple commutation failures caused by faults, showing promising potential for practical deployment in increasingly complex and uncertain power grid environments. After demonstrating the effectiveness of the proposed control strategy in this paper, the authors will further optimize the strategy based on the coupling characteristics between multiple HVDC links to make it applicable to more complex multi-infeed HVDC systems, and develop a low-power experimental prototype to verify its feasibility.