Fabrication and Characterization of Back-Gate and Front-Gate Ge-on-Insulator Transistors for Low-Power Applications

Abstract

Germanium (Ge) has long been regarded as a promising channel material, owing to its superior carrier mobility and highly tunable electronic band structure. The new generation of low-power electronics is approaching the formation of fully depleted (FD) transistors on Si-on-insulator (SOl) and Ge-on-insulator (GOl) substrates. In this work, we present a full process of a novel FDGOI transistor formed on a strained GOI with low defect density. This scalable and industry-compatible approach enables the formation of uniform 50 nm thick Ge layers by using spinning wet etch with ultrasmooth surfaces (RMS roughness = 0.262 nm) and a low etch-pit density of ~10⁵ cm⁻². Electrical measurements reveal excellent carrier transport properties, with back-gate (BG) transistors achieving mobilities of 550–600 cm²/V·s, while front-gate (FG) devices exhibit sharp switching behavior and steep subthreshold slopes, yielding I_ON/I_OFF ratios up to 10⁵. Temperature-dependent measurements further demonstrate a pronounced enhancement of device performance: the I_ON/I_OFF ratio increases to 106, the subthreshold swing (SS) decreases from 179 mV/dec at room temperature to 137 mV/dec at 120 K, and the threshold-voltage shift with temperature is as low as 1.87 mV/K across the range of 30–300 K. Such behavior highlights the potential of band-gap engineering for precise threshold-voltage control. Taken together, these results establish GOI as a CMOS-compatible material platform and provide a solid technological basis for the development of next-generation low-power transistors beyond conventional CMOS scaling.

1. Introduction

As conventional transistor scaling approaches its physical and technological limits, further reductions in device dimensions face increasingly stringent constraints, driving the search for high-mobility, energy-efficient channel materials and advanced device architectures [1,2,3,4,5,6,7,8]. Fully depleted silicon-on-insulator (FDSOI) devices, including fin field-effect transistors (FinFETs) [9,10,11,12,13,14,15,16,17,18,19,20,21] and ultra-thin-body silicon-on-insulator (SOI) transistors [22,23,24,25,26,27,28], have demonstrated low power consumption and effective suppression of short-channel effects (SCEs), establishing them as preferred candidates for current technology nodes. Nevertheless, even advanced architectures such as gate-all-around (GAA) [29,30,31] and complementary field-effect transistors (CFETs) [32], while offering superior electrostatic control and minimal off-state leakage, remain fundamentally constrained by the low on-state current (I_ON) of Si-based channels. These limitations arise from the relatively low carrier mobility of Si, which is further reduced under high electric fields due to velocity saturation and enhanced surface scattering, as well as the difficulty of maintaining subthreshold swing during aggressive gate length scaling. Accordingly, identifying alternative channel materials capable of higher intrinsic mobility, enhanced strain response, and energy-efficient operation has become imperative to sustain transistor performance scaling.

Silicon-germanium (SiGe) alloys have been widely used as embedded source/drain (S/D) regions to induce uniaxial or biaxial strain, enhancing carrier mobility through band splitting and effective mass modulation in both p-type metal-oxide-semiconductor (pMOS) and n-type metal-oxide-semiconductor (nMOS) devices [33,34,35]. In pMOS transistors, compressive strain lifts valence band degeneracy, reducing hole effective mass and improving hole mobility, whereas tensile strain in nMOS devices lowers conduction band effective mass and enhances electron transport [8]. However, the intrinsic mobility of Si channels remains a fundamental bottleneck, and SiGe-based strain engineering alone cannot fully address the limitations of drive current and switching performance [10]. Germanium (Ge), with its narrower bandgap, higher intrinsic mobilities for both electrons and holes, and stronger coupling to strain-induced band structure modifications, presents a compelling alternative [36,37,38,39]. GOI platforms integrate ultrathin, high-mobility Ge channels with low-leakage insulator substrates, offering a unique opportunity to decouple short-channel effects from material limitations [40,41,42,43,44,45,46,47]. Precise control over dislocation density, interface states, and channel strain enables systematic mitigation of scattering centers, while maintaining wafer-scale uniformity. Furthermore, the dependence of carrier transport on Ge thickness, strain distribution, surface morphology, and defect density can be explored through complementary back-gate (BG) and front-gate (FG) architectures. Investigating temperature-dependent electrical behavior further reveals the interplay between Coulomb scattering, defect-mediated scattering, and carrier freeze-out phenomena. Collectively, these considerations provide a roadmap for understanding how channel engineering, interface optimization, and strain modulation converge to determine transistor performance and set the stage for the detailed experimental analyses presented in the subsequent sections.

In this study, we present the fabrication of novel FDGOI transistors along with integrating materials characterization and electrical evaluation to reveal the complex interplay of channel thickness, strain, interface quality, and defect density. BG devices provide a simplified architecture for examining fundamental carrier transport and gate-channel coupling, whereas FG devices facilitate assessment of enhanced electrostatic control and realistic device operation. This dual-device strategy allows us to disentangle architecture-dependent effects from material- and process-induced variations. Ultrathin Ge layers were grown on Si wafers via reduced-pressure chemical vapor deposition (RPCVD) using a two-step process: low-temperature (LT) nucleation followed by high-temperature (HT) growth to suppress defects [48,49]. Channels were patterned and isolated using the buried oxide (BOX) layer as shallow trench isolation (STI), resulting in low-dislocation-density, uniformly strained Ge channels, as confirmed by high-resolution X-ray diffraction (HR-XRD). Temperature-dependent and strain-sensitive electrical measurements, combined with systematic interface characterization, enable a closed-loop optimization of channel thickness, interface quality, and gate design. By presenting both materials and device perspectives, this integrated approach establishes a direct link between high-quality GOI substrates and the superior electrical performance of the resulting transistors, while leaving specific experimental details and quantitative performance metrics to be revealed in the subsequent sections.

2. Experimental and Characterization Method

Ultrathin GOI substrates were fabricated using Si wafers as the starting templates. Ge was deposited using germane (GeH₄, 10% diluted in H₂) as the precursor. The heteroepitaxial growth of Ge on Si substrates was accomplished via a well-established two-step process. This method consists of an initial LT nucleation step at 450 °C, which forms a continuous layer despite containing a high defect density, followed by a HT growth step at 650 °C that substantially reduces the defect density through thermal annealing and recrystallization [50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65]. The resulting Ge/Si heterostructures were subsequently wafer-bonded onto thermally oxidized SiO₂ handle wafers, after which the defective nucleation layer was selectively removed to obtain ~50 nm-thick Ge channels with reduced dislocation density. Uniform thinning was further achieved through rotational wet etching with precisely controlled etchant delivery, a critical step in producing highly uniform ultrathin GOI layers. HRXRD measurements [66,67] confirmed low dislocation density, uniform strain distribution, and high crystallinity, thereby establishing a reproducible high-mobility materials platform well suited for advanced device fabrication.

To evaluate carrier transport and gate-channel coupling, BG transistors were fabricated on separate GOI substrates (Figure 1a). Ultrathin Ge channels were patterned by plasma etching, with the BOX layer serving as shallow trench isolation for the source/drain (S/D) regions. Bottom-gate electrodes were formed by depositing 200 nm Ti on the wafer backside after buffered oxide etch (BOE). S/D contacts employed a Ni (200 nm)/TiN (5 nm) bilayer, followed by rapid thermal annealing at 400 °C for 60 s in flowing N₂ to form low-resistance ohmic contacts [68,69,70,71,72,73,74,75,76]. This simplified BG configuration isolates gate-channel interactions, enabling direct assessment of intrinsic mobility and strain effects. FG transistors were fabricated on separate GOI substrates to investigate electrostatic control under practical device architectures (Figure 1b). P-type and n-type devices were realized by ion implantation, with boron implanted at 8 keV and a dose of 5 × 10¹⁴ cm⁻² for p-type channels using a 10 nm sacrificial oxide mask. Plasma oxidation followed by deposition of an Al₂O₃ (30 nm)/TiN (10 nm)/Ni (75 nm) gate stack completed the FG structure, while S/D contacts were formed identically to the BG devices. Post-implantation annealing was performed under the same conditions as BG devices. This separation of BG and FG device fabrication ensures that observed performance differences are attributable to gate architecture rather than material or process variations. The device structures are shown in Figure 1c,d.

Electrical characterization of both BG and FG transistors was conducted across 30–300 K using an Agilent B1500 analyzer (from Keysight Technologies) integrated with a CRX-VF cryogenic probe system located in Malaysia. Transfer and output characteristics were measured to extract mobility, on/off current ratio, and subthreshold swing, while Hall effect measurements provided complementary evaluation of intrinsic transport. These results directly link material quality with device performance, enabling iterative optimization of Ge thickness, BOX interface quality, and gate design. The combined methodology demonstrates reproducible device fabrication, highlights the complementary roles of BG and FG architectures, and establishes a robust framework for advancing high-mobility GOI-based nanoscale electronics.

3. Results and Discussion

To establish a solid foundation for understanding the subsequent device behavior, the top Ge layer, which initially exceeded 100 nm after wafer bonding, was thinned to ~50 nm through precisely controlled wet etching [77,78,79]. The etchant consisted of To provide a comprehensive understanding of the factors governing GOI-based transistor performance, it is essential to consider the synergistic interplay among Ge layer thinning, strain redistribution, surface morphology, and threading dislocation density (TDD). Precise control of the thinning process establishes the foundational layer thickness while preserving crystalline integrity, whereas strain evolution induced by selective material removal modulates carrier effective mass and mobility. Concurrently, ultra-smooth surface morphology, with root-mean-square roughness on the sub-nanometer scale, minimizes interface scattering and contact resistance, and low TDD ensures minimal defect-mediated scattering, collectively enhancing reproducibility and electrical performance. In the following discussion, we systematically examine these interrelated factors-integrating insights from wet etching kinetics, HR-TEM and AFM analyses, X-ray diffraction, defect characterization, and temperature-dependent electrical measurements elucidate their combined influence on carrier transport and gate modulation. This integrated perspective not only establishes a solid foundation for interpreting the observed BG and FG transistor characteristics but also highlights wafer-scale strategies for optimizing etching parameters, thermal treatments, interface engineering, and layer design to achieve superior uniformity and high-performance GOI devices.ammonium hydroxide-hydrogen peroxide-deionized water (APM) mixtures, with volume ratios (NH₄OH:H₂O₂:H₂O) ranging from 1:4:2000 to 1:4:20. This systematically varied concentration range enabled quantitative assessment of etching kinetics, balancing oxidative Ge removal by H₂O₂ and dissolution of the resulting GeO₂ by NH₄OH, while ensuring minimal impact on the underlying SiO₂ and Si layers [80,81,82,83,84]. The measured etch rate varied from ~0.05 nm/s at the most dilute condition to ~15 nm/s at the most concentrated condition, as summarized in Figure 2a, showing an approximately linear dependence on H₂O₂ concentration that allows nm-scale control of Ge thickness. High-resolution transmission electron microscopy (HR-TEM) was employed to assess structural integrity, interface quality, and uniformity of the thinned Ge layer. As shown in Figure 2b, the cross-sectional image clearly resolves the layered structure comprising the Si substrate, the oxide SiO₂ layer and the top Ge layer (~50 nm). Atomically sharp interfaces and the absence of observable extended defects confirm that the optimized wet etching preserves crystalline quality and interfacial smoothness. Figure 2c presents an optical image of a fully processed 8-inch GOI wafer, exhibiting uniform Ge layer thickness and ultra-smooth surface morphology. These results highlight not only the reproducibility and scalability of the wafer bonding and thinning processes but also highlight their novelty in achieving ultrathin Ge with sub-nanometer precision, uniform strain, and wafer-scale smoothness. Moreover, the structural integrity confirmed by HR-TEM directly correlates with the high carrier mobility obtained in subsequent device measurements, establishing a direct materials-to-devices link.

While precise thickness control and interface preservation provide the initial framework for high-quality GOI substrates, the mechanical effects of thinning—particularly the redistribution of strain—play a critical role in modulating carrier mobility and thus require systematic investigation. During the etching-induced thinning process, selective removal of Ge perturbs the internal stress equilibrium, leading to wafer-scale strain redistribution. Quantitative evaluation of this effect was performed using laser interferometry in conjunction with the Stoney formula, allowing correlation of wafer bow (curvature) with biaxial stress changes. The crystalline quality of the thinned GOI layer was evaluated by high-resolution X-ray diffraction (HRXRD). Figure 3a shows the Ge (004) diffraction profiles of the Ge/Si substrate (before bonding), the GOI substrate (before etching), and after etching, represented by the black, blue, and red curves, respectively. It can be observed that the position of the Ge diffraction peak from the substrate shows no significant change before and after bonding. The narrowing of the Ge diffraction peak (i.e., the decrease in FWHM) along with the change in intensity after thinning can be attributed to the successful removal of the low-temperature Ge layer with a high density of defects, which thereby enhances the diffraction signal from the underlying high-quality Ge layer. In the Ge channel of transistors fabricated on the GOI substrate, the strain measured by NBD [85] is 1.75%, whereas the strain in the pure Ge substrate is zero. This result has been reported in Ref. [20]. This modest broadening arises from residual strain gradients and minor lattice distortions during thinning; nevertheless, the top Ge layer retains excellent crystallinity, ensuring minimal defect-mediated scattering. Surface morphology, particularly root-mean-square (RMS) roughness, is another key factor influencing carrier scattering at the source/drain contacts and channel interface. Atomic force microscopy (AFM) analysis (Figure 3b) reveals an ultra-smooth surface with RMS roughness of 0.262 nm over a 10 × 10 μm² area and height variations confined within ±0.9 nm, comparable to atomically flat interfaces. Such atomically smooth surfaces minimize interface scattering and contact resistance, complementing the optimized strain profile and crystalline quality to further improve device performance. The uniform surface morphology across the wafer also reduces materials-to-device friction.

In addition to thickness and strain considerations, TDD and spatial distribution critically limit carrier transport, making quantitative defect analysis essential for reliable device performance. While prior studies have reported material characterization of GOI substrates, systematic evaluation of surface threading dislocations remains scarce. To address this, we employed a selective iodine-assisted etching method using a 49% HF:69% HNO₃: CH₃COOH mixture in a 5:10:11 volume ratio, supplemented with 30 mg of iodine [86]. In this formulation, HNO₃ acts as a general oxidizer, iodine introduces reaction-controlled selectivity for specific crystallographic orientations, and HF dissolves the resulting GeO_x, while acetic acid and water dilution fine-tune the etch rate to reveal dislocations without inducing additional surface damage. GOI samples were etched for few seconds, and nine randomly distributed regions (~107 × 143 μm²) were examined via metallurgical microscopy. Post-etch micrographs (Figure 4a) reveal dark etch pits, each corresponding to a threading dislocation. Statistical analysis (Figure 4b) indicates defect counts ranging from ~10 to ~120 per region, yielding a maximum TDD of ~105 cm⁻², comparable to high-quality epitaxial Ge layers grown on Si [64,65]. Although a localized peak appears at region 7, the overall low density and relatively uniform distribution confirm the excellent crystalline quality of the thinned GOI layers. The low TDD is primarily attributed to two mechanisms: (i) high-temperature annealing during buffer and cap layer growth, effectively annihilating dislocations in underlying layers, and (ii) lattice matching between the low-temperature buffer and high-temperature Ge cap, suppressing the formation of new threading dislocations. These factors ensure minimal structural defects, supporting robust carrier transport, reduced scattering, and reliable transistor operation. Importantly, these defect analyses complement our previous observations of uniform thickness, ultra-smooth surface morphology, and controlled strain evolution, establishing a coherent framework linking material quality with device performance.

BG transistors were selected for this study due to their structural simplicity, well-defined interface properties, and strong gate controllability, making them ideal for probing the intrinsic electronic behavior of Ge channels while minimizing extrinsic effects from complex fabrication processes. Figure 5a shows the I_ds-V_gs characteristics of a p-type Ge BG transistor with a gate width of 40 μm and a gate length of 10 μm at V_ds = −1 V. The device exhibits an on/off current ratio (I_ON/I_OFF) exceeding 10⁵, demonstrating the effectiveness of substrate thinning in reducing defect density and suppressing leakage currents. The I_ds-V_ds characteristics are presented in Figure 5b, confirming strong gate-channel coupling despite the relatively thick buried oxide (~720 nm), which can be attributed to the high carrier mobility of Ge and enhanced modulation of the internal electric field in the thinned substrate. The field-effect mobility was extracted from the I_ds-V_gs curve replotted as a function of surface carrier density (Ns), as shown in Figure 5c. The hole mobility exceeds 550 cm²/V·s, significantly higher than that of conventional Si-based devices. For comparison, several reference devices are included: a GOI junctionless transistor (JLT) with Na = 10¹⁹ cm⁻³ [46], another with Na = 10¹⁸ cm⁻³ [79], and a conventional Si pMOSFET with Nd = 6.6 × 10¹⁷ cm⁻³ [87]. The Ge BG transistor demonstrates superior mobility across all doping levels, particularly at high carrier concentrations, underscoring the potential of Ge for high-performance pMOSFET applications. These results highlight that substrate thinning combined with wafer bonding effectively preserves lattice integrity and minimizes defect density, providing an ideal platform for high-mobility Ge BG transistors. The high I_ON/I_OFF ratio, strong gate control, and enhanced hole mobility collectively demonstrate the unique advantages of the thinned GOI substrate (Na = 10¹⁶ cm⁻³) over conventional silicon platforms.

Figure 6a,b presents the I_ds-V_gs and I_ds-V_ds characteristics of a p-type FG GOI transistor with a gate width of 50 μm and a gate length of 4 μm. At V_ds = −1 V, the device achieves an I_ON/I_OFF ratio exceeding 10⁵, indicating excellent crystalline quality and low defect density after substrate thinning and wafer bonding. These results further validate the structural integrity of the fabricated GOI substrates. The mobility characteristics of p-channel FG transistors with a fixed gate width (50 μm) and varying gate lengths are shown in Figure 6c. A clear increase in mobility with longer gate lengths is observed, which can be attributed [88]: (i) mitigation of velocity saturation; (ii) reduced impact of lateral electric fields on carrier transport. Meanwhile, Figure 6d reveals a monotonic decrease in gm with increasing gate length, indicating a gradual reduction in gate control efficiency. The shortest-channel device (L = 4 μm) achieves a maximum g_m of 16.2 μS/μm, confirming the effectiveness of the FG structure in short-channel modulation. Compared with BG transistors, FG devices exhibit significantly stronger gate controllability, reflected by a much steeper subthreshold swing (SS) of 179 mV/dec, in contrast to 5370 mV/dec for BG devices. However, BG transistors retain fabrication simplicity and yield higher extracted hole mobility (~550 cm²/V·s vs. ~400 cm²/V·s for FG), highlighting an intrinsic trade-off between mobility enhancement and gate controllability. For a transistor with a constant gate width, the I_ds decreases with increasing gate length due to the corresponding increase in series resistance. This is consistent with the charge carrier mobility extraction formalism [20], in which I_ds scales inversely with L. As a result, the mobility extracted from devices with channel lengths between 10 and 50 μm remains remarkably stable. These results demonstrate that the FG structure provides excellent gate control and low-voltage operation, while the BG structure offers superior mobility and simplified processing. The complementary merits of both device types underscore the versatility of the GOI platform for advanced CMOS technology.

To provide valuable insights into the operational mechanisms and intrinsic electrical properties of GOI devices, temperature-dependent characteristics of transistors were analyzed. Insulating-layer substrates such as SOI and GOI are particularly prone to localized self-heating due to the low thermal conductivity of the buried oxide (BOX) layer compared with bulk Si [73], which necessitates a careful study of device performance across a wide temperature range. To investigate the cryogenic behavior of FG transistors, I_ds–V_gs measurements were performed at a fixed drain bias of −1 V, chosen to mitigate carrier freeze-out effects and ensure accurate evaluation of intrinsic transport. As shown in Figure 7a, the I_ON/I_OFF ratio increases to ~10⁶ at low temperatures, primarily owing to the stronger temperature dependence of the OFF-state current. This trend is consistent with Shockley-Read-Hall (SRH) recombination theory, in which the leakage current scales as exp(E_t/kT), where Et is the trap energy, k is the Boltzmann constant, and T is the absolute temperature [89]. The threshold voltage (V_t) can be expressed as:

$${\displaystyle \frac{\partial V_{\mathrm{t}}}{\partial T}}={\displaystyle \frac{\partial V_{fb}}{\partial T}}+q[{\displaystyle \frac{WH}{C_{ox}}}+{\displaystyle \frac{1}{\epsilon }}\cdot {({\displaystyle \frac{WH}{2H+W}})}^2]\times {\displaystyle \frac{\partial N_a}{\partial T}}$$

(1)

where the first term represents flat-band voltage variation and the second term accounts for incomplete ionization effects [90]. The temperature-dependent V_t is shown in Figure 7b (right axis). Across the temperature range of 30–300 K, the extracted slope of Vt variation with temperature is 1.87 mV/K, indicating excellent thermal stability. This relative invariance of Vt can be attributed to the combination of low channel doping (NA = 10¹⁶ cm⁻³) and the large lateral device dimensions (gate length of 50 μm), which effectively suppresses short-channel effects and mitigates thermally induced fluctuations. The temperature-dependent subthreshold slope (SS) is plotted in Figure 7b (left axis). The relative stability of V_t across the studied range can be attributed to the low channel doping concentration (N_a = 10¹⁶ cm⁻³) and the large lateral device dimensions (50 μm gate length), which effectively suppress short-channel and thermal instabilities. The temperature-dependent SS exhibits a non-linear dependence on T due to the combined influence of Coulomb scattering and interface trap states. The SS can be expressed as follows:

$$SS={\displaystyle \frac{kT}{q}}q\ln 10{\displaystyle \frac{C_{ox}+C_{Ge}+q{D}_{it}}{C_{ox}}}$$

(2)

where Cox is the gate-stack capacitance, CGe the Ge film capacitance [91].

Figure 7c shows the extracted I_ON/I_OFF ratio and I_OFF as functions of temperature (T) under V_ds = −1 V. As illustrated in Figure 7b,c, within the temperature range of 90–300 K, device characteristics are predominantly governed by ionized-impurity scattering, resulting in consistent variations in the extracted parameters, including V_t, SS, I_ON/I_OFF, and I_OFF. The device exhibits an exceptionally low off-state current of 3.59 × 10⁻¹⁰ A, which in turn enables a remarkable enhancement of the I_ON/I_OFF ratio from 2.2 × 10⁵ to 3.2 × 10⁶. Moreover, the subthreshold swing (SS) improves significantly with decreasing temperature, dropping from 179 mV/dec at 300 K to 137 mV/dec at 120 K. This electrical behavior originates primarily from improved carrier transport at low temperatures. On one hand, phonon and defect scattering are strongly suppressed, leading to enhanced carrier mobility; on the other hand, the low interface trap density (D_it) mitigates interface-assisted recombination and tunneling, thereby reducing leakage current and strengthening gate electrostatic control over the channel potential. Together, these mechanisms yield excellent off-state characteristics and sharp subthreshold slopes under cryogenic operation, providing critical physical insights for the design and optimization of high-performance, low-power electronic devices. However, the observed trap-related behavior can be attributed to three dominant sources: (i) point defects within the epitaxial Ge film, (ii) a thermodynamically unstable Ge/oxide interface characterized by a high density of D_it, and (iii) a defective boundary between the Ge channel and the BOX layer [92]. These scattering and charge fluctuation mechanisms account for the deviations from ideal linear temperature scaling. At cryogenic temperatures below 90 K, the physical mechanisms governing electrical behavior undergo a fundamental transition. Carrier freeze-out becomes dominant, thereby disrupting the conventional transport regimes valid at higher temperatures. Under these conditions, charge carriers no longer propagate through extended states but instead become localized in band-tail states [93,94]. As a consequence, transport proceeds predominantly via quantum-mechanical tunneling or hopping conduction, both of which exhibit highly complex and non-linear dependencies on temperature and electric field. Accordingly, critical device parameters such as V_t, SS, I_ON/I_OFF, and I_OFF show pronounced deviations from their high-temperature trends. To further advance device performance, reducing the interface trap density at the Ge/high-k dielectric interface remains essential. Potential strategies include optimizing atomic layer deposition (ALD) parameters, introducing effective interface passivation schemes, and employing engineered gate-stack architectures. Simultaneously, enhancing epitaxial Ge crystalline quality through the suppression of point defects and dislocations will improve carrier mobility. Moreover, as device dimensions continue to scale, suppressing gate leakage current becomes increasingly critical, necessitating the exploration of advanced gate engineering or alternative electrode materials.

Large-scale BG and FG transistors fabricated on high-quality GOI substrates were systematically investigated. We present a summary of the parameters of transistors with Si/Ge channels reported in recent years in

Table 1. Summary of extraction parameters for the transistor in recent years.

Year	Type	W/L (μm)	SS (mV/dec)	ION/IOFF	μeff (cm2/V·s)	Ref.
2016	p-Ge-BG	100/500	——	104	350	[95]
2017	p-Si-FG	0.015/0.02	79	105	——	[96]
2021	p-Ge-BG	10/100	500	105	300	[97]
2022	p-Si-FG	0.033/0.5	61	105	——	[98]
2023	p-GeSi-BG	100/100	6000	107	380	[99]
2023	p-SiGe-FG	0.025/0.5	86	106	——	[34]
2024	p-Ge-FG	10/50	37.7	104	300	[20]
2025	p-Ge-BG	40/10	5370	105	550	This work
2025	p-Ge-FG	50/4	179	105	400	This work

1. “—” indicates data not available in the original reference. 2. Abbreviations: p-Ge-BG = pMOS Ge-channel back-gate; p-Ge-FG = pMOS Ge-channel front-gate.

. This approach minimizes short-channel effects interference, enabling a focused examination of intrinsic material and interface properties—despite diverging from device scaling trends. To highlight the innovation and performance benefits, we compared our results with recent GOI transistor studies, demonstrating notable improvements in both device metrics and physical understanding. Leveraging an optimized GOI substrate fabrication process, the BG and FG transistors developed herein exhibit high hole mobilities of 550 cm²/V·s and 400 cm²/V·s, respectively, representing state-of-the-art performance within their device category. Importantly, the transistors in this study employ a relatively large gate length of 50 μm—significantly exceeding the micro/nanoscale dimensions typically reported in the literature—and a relatively thick germanium channel. These design features effectively modulate carrier transport and strengthen gate control, thereby serving as critical determinants of overall device performance. In terms of electrical characteristics, the device with a channel W/L of 100 μm/500 μm fabricated on a GOI substrate via the smart-cut technology [95] demonstrates a higher on-state current (~1 mA) and a superior I_ON/I_OFF ratio compared to its counterpart. Furthermore, when benchmarked against devices produced through the germanium condensation method [95], our structure achieves comparable I_ON/I_OFF ratios yet offers markedly enhanced gate controllability and significantly improved I_OFF stability. This improvement is largely attributed to the 50 nm back-channel thickness employed in our devices, which is substantially greater than the ~3.8 nm germanium channel layers used in condensation-based approaches, thereby effectively suppressing short-channel effects and mitigating drain-induced barrier lowering (DIBL). It is worth noting that the device reported in Ref. [96], transistors of identical dimensions fabricated on GOI substrates using wafer bonding, exhibit higher mobility. But exceptional electrical characteristics were achieved at the minimal gate width of 67 nm: an I_ON/I_OFF ratio of 10⁸ and a mobility of 1000 cm²/V·s, offering valuable insights for device scaling. Compared to the germanium condensation technique (W/L = 10/50 μm, G_m = 0.25 μS, SS = 500 mV/dec), the transistor fabricated by wafer bonding technology demonstrates superior gate controllability (G_m = 64.8 μS), evidenced by a significantly lower SS of 180 mV/dec. This performance advantage, combined with the inherent benefits of a simple, low-temperature process and excellent CMOS compatibility, underscores the competitiveness of this approach. Although not the highest, this I_ON/I_OFF is sufficient for low-power applications: our devices provide adequate on-state current and low off-state leakage, and compared to comparable GOI transistors of similar dimensions ([95,97]), a combination of a comparable I_ON/I_OFF (10⁵⁾, higher mobility (~300 cm²/V·s), and improved subthreshold swing (SS = 179 mV/dec) ensures effective switching and energy-efficient operation.

Despite the poorer SS and switching performance observed in our devices, the Ge channel demonstrates a significant advantage in carrier mobility over silicon. While Ge channel materials hold significant promise for post-silicon electronics due to their superior intrinsic carrier transport properties, they are also hampered by substantial integration challenges. On one hand, Ge offers dramatically higher bulk electron and hole mobility—approximately twice and four times that of silicon, respectively—enabling the potential for higher drive currents and faster switching speeds in future CMOS technology. This, coupled with its lower bandgap, also suggests a path toward lower operating voltages and reduced power consumption. On the other hand, these advantages are offset by critical drawbacks: the poor electronic quality and instability of native Ge oxides lead to high interface state densities, severely degrading channel mobility and increasing gate leakage. Furthermore, Ge’s narrow bandgap exacerbates junction leakage currents, and its high material cost and integration challenges with prevailing silicon-based manufacturing processes have thus far prevented its widespread commercialization. Consequently, current research focuses on mitigating these issues through advanced architectures like GOI, high-κ dielectric integration, and strain engineering within silicon-based platforms. By contrast, the performance gains in our study arise from two principal innovations: (i) the integration of wafer bonding with selective etch-back, which entirely avoids the crystal lattice damage typically induced by ion implantation and thereby substantially enhances channel crystallinity; (ii) precise oxidation of both BG and FG interfaces, which significantly reduces the interface trap density (D_it) and effectively suppresses gate leakage and off-state current increases. At V_gs = 1 V, the off-state current (I_OFF) increases only slightly from 1.51 × 10⁻⁸ A at V_ds = −0.1 V to 1.86 × 10⁻⁸ A at V_ds = −1 V, demonstrating strong gate electrostatic control and indirectly indicating a low interface trap density (D_it). During substrate fabrication, a certain degree of intrinsic strain is inevitably introduced through the epitaxial growth process and the pressure exerted during wafer bonding. While this built-in strain yields moderate improvements in electrical performance, further optimization through intentional strain engineering is still required. Building on our current findings, future investigations into germanium-based device technologies should focus on the following directions: (I) Integration with complementary materials. Advancing interface passivation and bandgap engineering techniques will be essential for enabling seamless integration with photodetectors and other functional components; (II) Scaling and heterogeneous 3D integration. Wafer-scale bonding and selective epitaxial growth strategies should be pursued to realize vertically stacked device architectures that combine germanium channels with silicon CMOS platforms; (III) Sub-5 nm device scalability. Addressing short-channel effects through atomic-scale etching precision, strain engineering, and device geometry optimization will be critical for extending germanium technology into future technology nodes. These research directions collectively provide a roadmap for achieving high-performance, densely integrated post-Moore electronic systems.

4. Conclusions

In summary, this study successfully fabricated high-quality GOI substrates through wafer bonding and etch-back techniques, achieving an ultra-smooth surface with a root-mean-square (RMS) roughness of only 0.262 nm. Back-gate transistors fabricated on both GOI and GeSnOI substrates demonstrated excellent electrical performance, with germanium channel transistors exhibiting an I_ON/I_OFF of ~10⁵ and hole mobilities exceeding 550 cm²/V·s and 400 cm²/V·s, respectively. Systematic investigation of the transfer characteristics (I_ds-V_gs) of GOI front-gate transistors across temperatures revealed the significant temperature dependence of the IOFF. In the low-temperature regime, charge transport was dominated by Coulomb scattering and neutral defect scattering at elevated temperatures. These findings not only elucidate the carrier scattering mechanisms in Ge-based transistors but also provide clear guidance for interface engineering and defect control, offering important insights for developing high-performance Ge-based CMOS devices in the post-Si era.