Discrete Switching Sequence Control for Universal Current Tracking in Wind Power Converters

Abstract

With increasing wind power penetration in modern grids, high-performance current control of converters is essential for efficient power transfer, harmonic reduction, and system stability. A novel discrete switching sequence control (dSSC) is proposed to ensure power converters universally track current references without steady-state error. A discrete model of the H-bridge converter is developed, together with a detailed, systematic design methodology to realize the dSSC. The resulting controller is applicable to arbitrary current references and guarantees zero steady-state error. Compared with pulse width modulation (PWM), the dSSC accounts for converter switching characteristics and provides a systematic design framework for both dynamic performance and steady-state accuracy. Moreover, the average switching frequency is approximately half that of PWM, which reduces maintenance and improves converter efficiency in wind-turbine applications. Simulation and experimental results validate the proposed method.

1. Introduction

Clean and renewable energy sources, such as wind power, photovoltaic power, and hydrogen power, are environmentally friendly and have an increasing penetration degree in the modern power grid [1]. However, the wider adoption of wind power is limited by factors such as energy capture efficiency, structural loading, and operation and maintenance costs [2,3]. To accommodate more renewable resources and to improve power quality, a variety of power devices, including grid-connected power converters [4], active power filters [5], and static synchronous compensators [6], must be accurately controlled. Among these, power electronic devices play a central role in determining the effectiveness of power extraction and the overall performance of the system [7,8].

For power electric devices, current reference tracking is one of the most important control objectives [9]. In different applications like power injection in grid-connected systems and active power filters, current references are different. For example, they can be sinusoidal signals, steps, and distorted signals. Considering different current references, a universal control strategy is desired to achieve precise current tracking for any arbitrary references [1]. In addition, power electronic converters are assembled with many power-switching devices [10], e.g., MOSFETs, IGBTs, SiCs, and GaNs, and the switching frequency is increasing drastically forward several hundred kHz. Such high switching frequency places stricter demands on the control system—reducing phase margin, amplifying the effects of measurement noise and delays, and consequently degrading system stability and steady-state accuracy [11,12,13,14].

In the past several decades, along with the development of power electronics, many classical methods [15,16,17,18], e.g., PWM and MPC [19], have been extensively developed to track various current references in converters. Among these, the PWM is the most widely used one for many kinds of converters [20,21,22]. Figure 1a shows the general control structure of PWM-based power converter systems. In Figure 1, the system contains the controller, PWM generator, and power converters. Generally, a PWM-based controller is designed as follows. Ignoring the switching characteristics of converters, the average model is established. Then, a continuous-time controller is designed according to the average model. Finally, the PWM generator converts the continuous outputs of the average-model-based controller into switching signals to drive the power-switching devices. The low-frequency response performance of the continuous controller and its PWM signal is similar when applied as the inputs of an inertial block. Hence, with the PWM generator, the continuous control signal can be replaced. Benefiting from the PWM, controller designers only focus on the average-model-based continuous controllers and the control objectives of power electronic converters are achieved relatively easily [23].

However, PWM-based controllers ignore the switching characteristics of power converters and the difference in high-frequency responses between continuous controllers and PWM inputs is not considered either. Hence, the theoretical analysis of the converter control performance is inaccurate, including stability, dynamics performance, and steady-state errors. For example, in [24], it has been reported that PWM-based multi-parallel converters caused high-frequency oscillations, while with the classical PWM frame, the average model-based discussion cannot disclose this issue properly.

In addition, the principle of PWM generators is shown in Figure 1b. As observed in Figure 1b, the PWM signals are obtained by comparing continuous signals with carriers. In general, the PWM frequency is selected as the sampling frequency. According to Figure 1b, the power-switching devices are switched twice during a sampling period. In order to reduce the loss of power converter systems, it is desirable to obtain a controller with a lower switching frequency, which increases the efficiency of converters.

Advanced PWM approaches reported in [25,26,27], for example sinusoidal PWM [28] and space-vector PWM [29], are commonly employed to enhance steady-state accuracy in power converters. Still, these techniques usually assume averaged models and fail to account for the actual switching dynamics. Hence, the theoretical analysis in terms of stability, dynamics, and steady-state errors are not strictly accurate.

Building on the foregoing, this paper develops a novel discrete switching sequence control (dSSC) to address current tracking in wind power converters, and validates the proposed scheme on an H-bridge converter. The proposed dSSC is demonstrated on an H-bridge converter. First, considering the switching characteristics of the power electronic elements, the current tracking problem is formulated as a switching sequence control issue, and the discrete-time model is accordingly established for the H-bridge converter. Then, a systematic stepwise design procedure is developed to derive the dSSC. The designed controller is available for any arbitrary current references, e.g., sinusoidal signals, steps, and harmonics, and it has zero steady-state errors. Furthermore, the control parameter is adjustable, which ensures the dynamics of power converters. As a special case, the control parameter is selected as 0, where the system can reach the steady-state with zero errors only in one sampling period. Simulations and experimental facts are presented to verify the effectiveness of the proposed method. Compared with classical PWM methods, the design of dSSC has the following advantages:

(1) The proposed method accounts for the switching behavior of power converters and provides a systematic procedure to design converter control for both dynamic response and steady-state accuracy.

(2) The average switching frequency of the proposed method is just half of that with the PWM control. In a sampling period, power electronic devices are switched twice with the PWM control, while the designed dSSC only changes once. This leads to lower power losses.

The paper is structured as follows: Section 2 analyzes the problem formulation of the dSSC, Section 3 presents the dSSC design, and Section 4 illustrates a special case; Section 5 and Section 6 provide simulation and experimental results, respectively, and Section 7 concludes the paper.

2. Problem Formulation of the dSSC

Consider the H-bridge converter presented in Figure 2, which comprises a DC source U, an inductor L, a load resistor R, and four switching devices SW1–SW4. The converter’s continuous-time model is expressed as

$$u(t)=L{\displaystyle \frac{di\left(t\right)}{dt}}+Ri\left(t\right)$$

(1)

where $u\left(t\right)$ is the input voltage and $i\left(t\right)$ is the load current as shown in Figure 2. According to the switching characteristics of the four switching devices $S{W}_{1–4}$, the input $u\left(t\right)$ belongs to a finite set

$$U_{\mathrm{set}}=\{U,-U,0\}$$

(2)

where U is the voltage of DC source. Hence, the controller design for the H-bridge converter can be formulated as an SSC problem:

Switching Sequence Control (SSC): Given a reference current $i_{\mathrm{ref}}\left(t\right)$, designing the input sequence $U_{\delta }=\{U_1,\dots ,U_k,\dots \}$ from the finite input set $U_{\mathrm{set}}$ and the corresponding time switching sequence $t_{\delta }=\{t_1,t_2,\dots ,t_k,\dots \}$ satisfying

$$u\left(t\right)=U_k, t\in [t_{k-1},t_k),$$

(3)

such that the current $i\left(t\right)$ can accurately track the reference current $i_{\mathrm{ref}}\left(t\right)$.

To achieve this, the discrete-time model of the H-bridge converter is established by considering the switching characteristics of the power devices $S{W}_{1–4}$. By a mathematical transformation, the continuous-time model (1) of the H-bridge converter is rewritten as

$${\displaystyle \frac{di\left(t\right)}{dt}}=-{\displaystyle \frac{R}{L}}i\left(t\right)+{\displaystyle \frac{1}{L}}u\left(t\right)$$

(4)

Integrating both sides of Equation (4) over $t\in [kT,(k+1\left)T\right]$ gives

$${\int }_{kT}^{(k+1)T}di=-{\displaystyle \frac{R}{L}}{\int }_{kT}^{(k+1)T}i\left(t\right)dt+{\displaystyle \frac{1}{L}}{\int }_{kT}^{(k+1)T}u\left(t\right)dt$$

(5)

It is then easy to deduce that

$${\int }_{kT}^{(k+1)T}di=i\left[(k+1)T\right]-i\left(kT\right)$$

(6)

Clearly for a small sampling period, it has

$${\int }_{kT}^{(k+1)T}i\left(t\right)dt\approx i\left(kT\right)T$$

(7)

By substituting Equations (6) and (7) into Equation (5), the discrete model in Equation (4) is obtained

$$i\left[(k+1)T\right]=\left(1-{\displaystyle \frac{RT}{L}}\right)i\left(kT\right)+{\displaystyle \frac{1}{L}}{\int }_{kT}^{(k+1)T}u\left(t\right)dt$$

(8)

The system in (8) is the discrete-time model for the H-bridge converter. In the next section, a discrete-time model-based solution of the SSC is proposed, which is called dSSC. The proposed method tracks any arbitrary current reference $i_{\mathrm{ref}}\left(kT\right)$ with zero steady-state errors.

3. Discrete Switching Sequence Control Design

The dSSC design proceeds according to the following steps:

Step 1. The input sequence $U_{\delta }=\{U_1,U_2,\dots ,U_k,\dots \}$ is selected according to

$$U_k=\left\{\begin{array}{cc}U,& \mathrm{if}k=2m+1,\\ -U,& \mathrm{if}k=2m+2\end{array}\right. , m=0,1,2,\dots$$

(9)

Step 2. The switching time sequence $t_{\delta }=\{t_1,t_2,\dots ,t_k,\dots \}$ satisfies

$$t_k\in [(k-1)T,kT]$$

(10)

Step 3. If $t_1,t_2,\dots ,t_k,\dots$ are properly designed, the switching sequence controller is given by

$$u\left(t\right)=\left\{\begin{array}{cc}U,& \mathrm{if}t\in [t_{2m},t_{2m+1})\\ -U,& \mathrm{if}t\in [t_{2m+1},t_{2m+2})\end{array}\right. m=0,1,2,\dots$$

(11)

In addition, Figure 3 shows the above steps for the dSSC. In Figure 3, the input sequence $U_{\delta }$ consists of the converter inputs, and its elements belong to the finite set $U_{\mathrm{set}}$. The switching time sequence $t_{\delta }$ determines the start time and end time of each element of $U_{\delta }$. For example, the beginning and ending times of $U_k$ in the input sequence are $t_{k-1}$ and $t_k$, respectively. When the input sequence and the switching time sequence $t_{\delta }$, are well-designed, the controller is constructed by $U_k$ and $t_k$, according to Step 3.

As follows, the switching time sequence $t_k, k=1,2,\dots ,$ is designed such that $i\left(kT\right)$ tracks the reference $i_{\mathrm{ref}}\left(kT\right)$ without steady-state errors. The tracking error is defined as

$$e\left(kT\right)=i\left(kT\right)-i_{\mathrm{ref}}\left(kT\right)$$

(12)

From (8), the tracking error at time $(k+1)T$ is defined as

$$\begin{array}{ccc}\hfill e\left[\right(k+1\left)T\right]& =& \left(1-{\displaystyle \frac{RT}{L}}\right)i\left(kT\right)-i_{\mathrm{ref}}\left[(k+1)T\right]\hfill \\ & & +{\displaystyle \frac{1}{L}}{\int }_{kT}^{(k+1)T}u\left(t\right)dt\hfill \end{array}$$

(13)

Next, the switching time sequence $\{t_1,t_2\dots ,t_k\dots \}$ is designed according to the following two cases. In Case 1, $t_k$ with $k=2m$ and $m=0,1,2,\dots$ is designed, while $t_k$ with $k=2m+1$ and $m=0,1,2,\dots$ is constructed in Case 2.

Case 1. $k=2m,m=0,1,2,\dots$. In this case, $u\left(t\right)$ in the time domain $[kT,(k+1\left)T\right]$ satisfies

$$u\left(t\right)=\left\{\begin{array}{cc}U,& t\in [kT,t_{k+1})\\ -U,& t\in [t_{k+1},(k+1)T)\end{array}\right.$$

(14)

Then,

$$\begin{array}{ccc}\hfill {\int }_{kT}^{(k+1)T}u\left(t\right)dt& =& {\int }_{kT}^{t_{k+1}}Udt-{\int }_{t_{k+1}}^{(k+1)T}Udt\hfill \\ & =& 2U{t}_{k+1}-(2k+1)UT\hfill \end{array}$$

(15)

This, together with (13), implies

$$\begin{array}{ccc}\hfill e\left[\right(k+1\left)T\right]& =& \left(1-{\displaystyle \frac{RT}{L}}\right)i\left(kT\right)-i_{\mathrm{ref}}\left[(k+1)T\right]\hfill \\ & & +{\displaystyle \frac{1}{L}}\left[2U{t}_{k+1}-(2k+1)UT\right]\hfill \end{array}$$

(16)

Choosing $t_{k+1}$ satisfying

$$\begin{array}{ccc}& & \left(1-{\displaystyle \frac{RT}{L}}\right)i\left(kT\right)-i_{\mathrm{ref}}\left[(k+1)T\right]\hfill \\ & & +{\displaystyle \frac{1}{L}}\left[2U{t}_{k+1}-(2k+1)UT\right]=\lambda e\left(kT\right)\hfill \end{array}$$

(17)

which results in

$$\begin{array}{c}\hfill e\left[\right(k+1\left)T\right]=\lambda e\left(kT\right)\end{array}$$

(18)

where $\lambda$ is the control parameter and $0\le \left|\lambda \right|<1$. It is easy to calculate from (17) that

$$\begin{array}{ccc}\hfill t_{k+1}& =& kT+{\displaystyle \frac{T}{2}}+{\displaystyle \frac{\lambda L+RT-L}{2U}}i\left(kT\right)\hfill \\ & & +{\displaystyle \frac{L{i}_{\mathrm{ref}}\left[(k+1)T\right]-\lambda L{i}_{\mathrm{ref}}\left(kT\right)}{2U}}\hfill \end{array}$$

(19)

Case 2. $k=2m+1, m=0,1,2,\dots$. In this case, $u\left(t\right)$ in the time domain $[kT,(k+1\left)T\right]$ satisfies

$$u\left(t\right)=\left\{\begin{array}{cc}-U,& t\in [kT,t_{k+1})\\ U,& t\in [t_{k+1},(k+1)T)\end{array}\right.$$

(20)

Thus,

$$\begin{array}{ccc}\hfill {\int }_{kT}^{(k+1)T}u\left(t\right)dt& =& {\int }_{kT}^{t_{k+1}}-Udt+{\int }_{t_{k+1}}^{(k+1)T}Udt\hfill \\ & =& -2U{t}_{2k+1}+(2k+1)UT\hfill \end{array}$$

(21)

Submitting (21) into (13) results in

$$\begin{array}{ccc}\hfill e\left[\right(k+1\left)T\right]& =& \left(1-{\displaystyle \frac{RT}{L}}\right)i\left(kT\right)-i_{\mathrm{ref}}\left[(k+1)T\right]\hfill \\ & & {\displaystyle \frac{1}{L}}\left[-2U{t}_{k+1}+(2k+1)UT\right]\hfill \end{array}$$

(22)

Choosing the switching time $t_{k+1}$ such that

$$\begin{array}{ccc}& & \left(1-{\displaystyle \frac{RT}{L}}\right)i\left(kT\right)-i_{\mathrm{ref}}\left[(k+1)T\right]\hfill \\ & & {\displaystyle \frac{1}{L}}\left[-2U{t}_{k+1}+(2k+1)UT\right]=\lambda e\left(kT\right)\hfill \end{array}$$

(23)

it can be observed that

$$e\left[\right(k+1\left)T\right]=\lambda e\left(kT\right)$$

(24)

By a simple calculation from (23), it is deduced that

$$\begin{array}{ccc}\hfill t_{k+1}& =& kT+{\displaystyle \frac{T}{2}}+{\displaystyle \frac{L-RT-\lambda L}{2U}}i\left(kT\right)\hfill \\ & & +{\displaystyle \frac{\lambda L{i}_{\mathrm{ref}}\left(kT\right)-L{i}_{\mathrm{ref}}\left[(k+1)T\right]}{2U}}\hfill \end{array}$$

(25)

Stability analysis. When the switching time sequence $t_{k+1}$ is chosen by Case 1 and Case 2, it yields from (18) and (24) that

$$e\left[\right(k+1\left)T\right]=\lambda e\left(kT\right)$$

(26)

For $k=0,1,\dots$, this yields Equation (27), which states that

$$e\left(kT\right)={\lambda }^{k}e\left(0\right)$$

(27)

With the above dSSC design and analysis, it the theorem follows:

Consider the discrete-time system (8) for the H-bridge converter. If the switching sequence controller is designed by Step 1–Step 3, and the switching time sequence $t_{k+1}$, $k=0,1,\dots$ is chosen by (19) and (25) according to the above Case 1 and Case 2, then

$$e\left(kT\right)={\lambda }^{k}e\left(0\right)$$

(28)

where $\lambda$ is the control parameter and $0\le \left|\lambda \right|<1$.

Equation (28) shows that the proposed method achieves zero steady-state errors. Also, it implies the relationship between the system dynamics and the control parameter $\lambda$. Applying $5\%$ as a criterion for the settling time $T_s$, it is selected $e\left(T_s\right)=0.05p.u.$ and $e\left(0\right)=1p.u.$ It has

$$e\left(T_s\right)={\lambda }^{{\displaystyle \frac{T_s}{T}}}e\left(0\right)={\lambda }^{{\displaystyle \frac{T_s}{T}}}=0.05p.u.$$

(29)

Hence,

$${\displaystyle T_s=Tlo{g}_{\lambda }0.05=\frac{3T}{ln(1/\lambda )}}$$

(30)

According to (30), the system dynamics are adjustable and the expected settling time $T_s$ is obtained by choosing the control parameter $\lambda$.

Remark 1.

It is observed from Step 3 that the power devices only switch once in a sampling period. However, the classic PWM requires the power devices to switch twice in a sampling period. This means the switching frequency for the dSSC (11) is only half of that for the PWM method.

4. A Special Case: dSSC with One-Sampling-Period Tracking

As a special case, selecting the control parameter $\lambda =0$ is discussed in this section. According to Equation (27), when $\lambda =0$, it is deduced that

$$e\left(T\right)={\lambda }^{k}e\left(0\right)=0^{k}e\left(0\right)=0$$

(31)

It implies the Equation (31), which states that

(1) This case has zero steady-state error tracking for any arbitrary current references;

(2) This case has significant fast dynamics and its dynamics process is about one sampling period.

In this case, together with (19), (25) and the control parameter $\lambda =0$, the switching time sequence $t_k$ is deduced as

$$t_{k+1}=\left\{\begin{array}{cc}{\displaystyle kT+\frac{T}{2}+\frac{L{i}_{\mathrm{ref}}\left[(k+1)T\right]}{2U}}& \\ {\displaystyle +\frac{RT-L}{2U}i\left(kT\right)}& \mathrm{if}k=2m\\ {\displaystyle kT+\frac{T}{2}-\frac{L{i}_{\mathrm{ref}}\left[(k+1)T\right]}{2U}}& \\ {\displaystyle +\frac{L-RT}{2U}i\left(kT\right)}& \mathrm{if}k=2m+1\end{array}\right.$$

(32)

According to (10), $t_{k+1}\in [kT,(k+1)T]$. To limit $t_{k+1}$ in such a region, a condition is expected to satisfy

$$\left|{\displaystyle \frac{RTi\left(kT\right)}{2U}}+{\displaystyle \frac{Li\left(kT\right)-L{i}_{\mathrm{ref}}\left[(k+1)T\right]}{2U}}\right|\le {\displaystyle \frac{T}{2}}$$

(33)

Hence, a conclusion is summarized as follows. Consider the discrete-time system (8) for the H-bridge converter. If the switching sequence controller is designed by Step 1–Step 3, the switching time sequence $t_{k+1}, k=0,1,\dots$ is chosen by (32) and the condition (33) is satisfied, the current $i\left(kT\right)$ will track the current references $i_{\mathrm{ref}}\left(kT\right)$ without steady-state errors and converge in a sampling period.

In practice, there are some applications where the condition (33) is unsatisfied. In the following, the controller (32) and Step 1–Step 3 with a saturation strategy are proposed to handle this issue.

When the condition (33) is unsatisfied and it results in $t_{k+1}>(k+1)T$ or $t_{k+1}<kT$, the switching time $t_{k+1}$ is designed by a saturation strategy as

$$t_{k+1}=\left\{\begin{array}{cc}(k+1)T& \mathrm{if}{t}_{k+1}>(k+1)T\hfill \\ kT& \mathrm{if}{t}_{k+1}<kT\hfill \end{array}\right.$$

(34)

With the saturation strategy (34), $u\left(t\right)$ is set as U or $-U$ in the time domain $[kT$, $(k+1)T]$, and the tracking errors reduce in the fastest way. Then, the condition (33) will be satisfied in a certain period, and the proposed method achieves zero steady-state error tracking.

5. Simulation Results

This section presents the simulation results for the proposed dSSC method. The simulation parameters are set as follows: $U=60$ V, $R=30\Omega$, $L=9$ mH, and $T=50$ μs. Figure 4, Figure 5 and Figure 6 are the simulation results of the proposed method.

In Figure 4, the simulation shows the tracking performances of the proposed dSSC, with different references. The control parameter $\lambda$ is selected as $0.4$. In Figure 4a, the current reference is set as a step-change signal. In Figure 4b, the current reference is a sinusoidal signal with its amplitude being $1A$. In Figure 4c, the reference is selected as a $0.5$ A sinusoidal signal with $0.5$ A third and $0.5$ A fifth harmonics. Observing In Figure 4b,c, the proposed method achieves zero steady-state-error tracking and it is suitable for different types of references, which is a part of the conclusion in Equation (27).

In Figure 5, the simulations provide the relationships between system dynamics and the control parameter $\lambda$. In Figure 5, the parameter $\lambda$ is chosen as $0.8$, $0.7$, and $0.4$, respectively. The simulation results show that the steady-state tracking errors are zero under different control parameters. However, their dynamics are different. It is observed from Figure 5, that a smaller $\gamma$ results in faster dynamics, which has been concluded in Equation (27).

Figure 6 shows the performance of the dSSC, with the control parameter $\lambda =0$. In Figure 6a, the current reference is a step-change from $0.7$ A to $0.8$ A and hence the condition (33) is satisfied. In this case, the current tracking has fast dynamics and its transient process is about one sampling period, which further confirms the results of Equation (31). In Figure 6b, the current reference is a step-change from $-1$ A to $1$ A and the condition (33) is unsatisfied. Observing Figure 6b, its dynamics are slower, being longer than one sampling period but it still converges to the current reference, with a short transient period.

6. Experiment Results

The proposed dSSC was implemented on a TMS320F28379D DSP-based platform. Gate signals were generated by a dedicated control PCB and used to drive the IGBTs forming the H-bridge inverter. Current waveforms were captured with an oscilloscope. The experimental parameters were $U=60\mathrm{V}$, $R=30\Omega$, $L=9\mathrm{mH}$, and $T=50$ μs. The experimental setup is shown in Figure 7.

Figure 8 shows the experimental tracking results for three reference signals: a step, a sinusoid, and a sinusoid with harmonics. Figure 8a illustrates that the proposed method exhibits a fast transient response to a step input. Figure 8b,c demonstrate that the controller achieves zero steady-state error when tracking a sinusoidal reference and a sinusoidal reference with harmonic content, respectively. Importantly, Figure 8c indicates that zero steady-state tracking error is preserved even in the presence of harmonics. These observations are consistent with Equation (27).

Figure 9 provides experiments of the dynamic performances, with different control parameters $\lambda$. Observing Figure 9, it is found that a smaller control parameter $\lambda$ leads to faster dynamics, which is also summarized in Equation (27).

Figure 10 is the experimental result of the dSSC, with the control parameter $\lambda =0$. In Figure 10a, the current reference is a step-change from $0.7$ A to $0.8$ A and the condition (33) is satisfied. Hence, a zero steady-state tracking error is achieved within one sampling period. It confirms the conclusion of Equation (31). In Figure 10b, the reference is a step-change from $-1$ A to $1$ A, which causes the condition (33) to be unsatisfied. Hence, the transient process is larger than a sampling period. However, it still achieves accurate tracking with satisfactory dynamics.

7. Conclusions

This paper proposes a dSSC for the H-bridge converters to track current references with zero steady-state errors. The proposed method is universal and it is suitable for arbitrary type references, such as steps, sinusoidal signals, and harmonics. In detail, the discrete model of the H-bridge converters is established, considering the switching characteristics of power devices. Then, the dSSC is provided in a step-by-step way to achieve accurate current tracking. The parameter tuning is also addressed to adjust the dynamic responses. In addition, choosing the control parameter as 0, a special case is discussed deeply. In this case, the system achieves zero steady-state errors within one-sampling-period dynamics, when the condition (33) is satisfied.

Furthermore, the average switching frequency of the proposed method is just half of that for the PWM methods. This reduction lowers switching losses in power devices and decreases overall power dissipation, which in turn reduces maintenance requirements and improves converter efficiency in wind-turbine applications. Simulation and experimental results validate the effectiveness of the proposed approach. However, the proposed dSSC method entails increased computational complexity, and its performance under more complex operating conditions has not yet been evaluated. Future work will therefore concentrate on lowering computational requirements and broadening the controller model to cover more practical scenarios.