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Open AccessArticle
A Source-to-Source Compiler to Enable Hybrid Scheduling for High-Level Synthesis
1
Department of Electrical Engineering, City University of Hong Kong, Hong Kong, China
2
Center for Intelligent Multidimensional Data Analysis, Hong Kong Science Park, Shatin, Hong Kong, China
*
Author to whom correspondence should be addressed.
Electronics 2025, 14(23), 4578; https://doi.org/10.3390/electronics14234578 (registering DOI)
Submission received: 20 October 2025
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Revised: 13 November 2025
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Accepted: 20 November 2025
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Published: 22 November 2025
Abstract
High-Level Synthesis (HLS) has gained considerable attention for its ability to quickly generate hardware descriptions from untimed specifications. Most state-of-the-art commercial HLS tools employ static scheduling, which excels in compute-intensive applications but struggles with control-dominant designs. While some open-source tools propose dynamic and hybrid scheduling techniques to synthesize dataflow-like architectures to improve speed, they lack well-established optimizations from static scheduling like datapath optimization and resource sharing, leading to frequency degradation and area overhead. Moreover, existing hybrid scheduling relies on extra dynamic synthesis support, either by dynamic or static HLS tools, and thereby loses generality. In this work, we propose another solution to achieve hybrid scheduling: a source-to-source compiler that exposes dynamism at the source code level, which reduces both frequency and area overhead while remaining fully compatible with modern static HLS tools without needing extra dynamic synthesis support. Experiments show significant improvements (1.26× speedup) on wall clock time (WCT) compared to VitisHLS and a better area–frequency–latency trade-off compared to dynamic (1.83× WCT speedup and 0.46× area) and hybrid (2.14× WCT speedup and 0.72× area) scheduling-based tools.
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MDPI and ACS Style
She, Y.; Huang, Y.; Liu, J.; Cheung, R.C.C.; Yan, H.
A Source-to-Source Compiler to Enable Hybrid Scheduling for High-Level Synthesis. Electronics 2025, 14, 4578.
https://doi.org/10.3390/electronics14234578
AMA Style
She Y, Huang Y, Liu J, Cheung RCC, Yan H.
A Source-to-Source Compiler to Enable Hybrid Scheduling for High-Level Synthesis. Electronics. 2025; 14(23):4578.
https://doi.org/10.3390/electronics14234578
Chicago/Turabian Style
She, Yuhan, Yanlong Huang, Jierui Liu, Ray C. C. Cheung, and Hong Yan.
2025. "A Source-to-Source Compiler to Enable Hybrid Scheduling for High-Level Synthesis" Electronics 14, no. 23: 4578.
https://doi.org/10.3390/electronics14234578
APA Style
She, Y., Huang, Y., Liu, J., Cheung, R. C. C., & Yan, H.
(2025). A Source-to-Source Compiler to Enable Hybrid Scheduling for High-Level Synthesis. Electronics, 14(23), 4578.
https://doi.org/10.3390/electronics14234578
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