Switching Frequency Figure of Merit for GaN FETs in Converter-on-Chip Power Conversion

Abstract

Power converters are increasingly pushing toward higher switching frequencies, with current designs typically operating between tens of kilohertz and a few megahertz. The commercialization of gallium nitride (GaN) power transistors has opened new possibilities, offering performance far beyond the limitations of conventional silicon devices. Despite this promise, the potential of GaN technology remains underutilized. This paper explores the feasibility of achieving sub-gigahertz switching frequencies using GaN-based switch-mode power converters, a regime currently inaccessible to silicon-based counterparts. To reach such operating speeds, it is essential to understand and quantify the intrinsic frequency limitations imposed by GaN device physics and associated parasitics. Existing power conversion topologies and control techniques are unsuitable at these frequencies due to excessive switching losses and inadequate drive capability. This work presents a detailed, systematic study of GaN transistor behavior at high frequencies, aiming to identify both fundamental and practical switching limits. A compact analytical model is developed to estimate the maximum soft-switching frequency, considering only intrinsic device parameters. Under idealized converter conditions, this upper bound is derived as a function of internal losses and the system’s target efficiency. From this, a soft-switching figure of merit is proposed to guide the design and layout of GaN field-effect transistors for highly integrated power systems. The key contribution of this study lies in its analytical insight into the performance boundaries of GaN transistors, highlighting the roles of parasitic elements and loss mechanisms. These findings provide a foundation for developing next-generation, high-frequency, chip-scale power converters.

1. Introduction

The switching frequency of power converters has traditionally ranged from tens of kilohertz to a few megahertz at most. Insulated gate bipolar transistors are typically employed in low-frequency, high-voltage, high-power applications, and MOSFET [1] are widely used in all other cases. The values of the output filter components (inductors and capacitors) in switch-mode power converters are inherently frequency-dependent: as the switching frequency increases, the required filter size decreases, leading to reductions in both the physical dimensions and cost of the overall converter system. However, higher frequencies also introduce increased switching losses, primarily due to the parasitic elements of the MOSFET, including gate resistance (r_G), gate–source capacitance (C_GS), output capacitance (C_OSS), and Miller capacitor (C_DG) [2]. Despite significant advancements in the performance of silicon (Si) switches by both academia and industry [3], the fundamental operational principles of power converters remain largely unchanged. This limitation stems from the intrinsic characteristics of Si-based transistors, such as their conduction losses, parasitic capacitances, limited breakdown voltage, and relatively low electron mobility.

In contrast, wide bandgap (WBG) semiconductors offer substantial advantages for power electronics applications. Their ability to sustain higher electric breakdown fields allows for a thinner drift region for the equivalent voltage rating, resulting in devices with reduced conduction losses. Additionally, their lower capacitance values and higher carrier saturation velocity enable faster-switching transitions [4]. Among WBG devices silicon carbide transistors have demonstrated superior breakdown voltage capabilities while maintaining a relatively lower on-state resistance. A secondary benefit is its high thermal conductivity, which enhances device reliability and thermal management [5]. Another promising WBG material is Vertical (bulk) Gallium Nitride (GaN) [6]. GaN devices exhibit inherently higher breakdown fields, enabling higher voltage operation in a narrower drift region. This makes them suitable for pushing the boundaries of power conversion efficiency beyond the limitations of Si-based technologies [7,8,9].

Although the material properties alone should enable superior device operation the full potential of GaN devices requires more than a simple substitution for conventional Si MOSFETs. Naïvely replacing a Si MOSFET with a GaN transistor in an existing converter design can lead to degraded performance or even device failure. The switching behavior of GaN devices is highly dependent on the gate driver circuitry, converter topology, and printed circuit board layout [10,11]. GaN has also been characterized for its reliability in high power and Microwave applications [12].

One of the primary challenges associated with GaN devices is the increased sensitivity to parasitic inductances arising from the packaging and PCB layout. Parasitic inductances in the drain (L_D), source (L_S), and gate (L_G) paths exacerbate voltage overshoots and ringing during switching transitions, thereby limiting performance and potentially causing malfunction [13,14,15]. The common source, in particular, couples high di/dt currents from the power loop into the low-voltage gate loop. The resulting voltage drops across L_S reduce the effective gate voltage during turn-on and increase it during turn-off, slowing transitions and increasing switching losses. This effect can be mitigated using Kelvin source connections [16] as demonstrated in [17,18]. To further reduce parasitics [19,20] in synchronous converter configurations, monolithic integration of high-side and low-side devices, along with optimized internal decoupling capacitors and interconnects, has proven effective [21]. Additional improvements can be achieved by integrating the gate driver directly into the power module as reported in [22]. Another critical concern in high-speed GaN-based converters is crosstalk—also known as cross conduction or Miller turn-on. This phenomenon occurs when a device is unintentionally turned on by the voltage transient (dv/dt) across its Miller capacitance, triggered by the switching of the complementary device in the same half-bridge leg. This unintended turned on leads to shoot-through currents across the DC bus, resulting in substantial switching losses [23].

Prior research has investigated key design considerations for gate driver circuits tailored to GaN high electron mobility transistors, with several works demonstrating multi-resonant, high-speed gate drivers capable of significantly reducing switching losses [22,24]. Comprehensive electrical models have also been proposed to facilitate accurate circuit level characterization and deeper understanding of GaN device behavior [25].

Another major limitation to high-frequency converter operation arises from magnetic core materials [26]. To address this, air-core inductors have been explored as a means to eliminate core-related losses. For instance, the work in [27] presented an air-core design that removes the magnetic material constraint, thereby enabling the realization of “core-less converters” or converter-on-chip (CoC) architectures.

Advancing power-converter operating frequencies also has implications for control bandwidth. While conventional dual loop controllers operating at several hundred kilohertz-are sufficient for most application with bandwidth requirements on the order of one kilohertz, emerging applications such as envelope tracking [28], RF power amplification [29] and light detection and ranging (LiDAR) systems [30] demand significantly higher bandwidth. To address this, both analog and digital control strategies have been proposed to enhance system robustness, including controllers capable of stabilizing multiple distinct plant configurations.

Although gigahertz-range power conversion remains largely impractical at present, pushing toward that regime highlights the importance of advanced circuit topologies and loss mitigation techniques. Conventional approaches such as zero-voltage switching (ZVS), zero current switching (ZCS), and resonant or quasi-resonant topologies continue to be employed. Additionally, recent efforts have focused on leveraging parasitic elements for efficient switching [31]. Prior work by authors introduced an analytical study of a GaN-based pulsed-width modulation (PWM) generator implemented using a ring oscillator (RO) topology, demonstrating its dual capability as both a controlled PWM source and a voltage-controlled oscillator [32].

This paper aims to provide design guidelines for GaN FET layout engineers from a power electronics perspective, with a focus on identifying suitable figure of merit (FOM) for device selection. To this end, we develop an analytical framework for evaluating high-speed GaN-based power converter and the corresponding limitations imposed by the device-level parasitics. We first present a simplified GaN FET model, following by an analysis of the relationship among key static and dynamic parameters. Subsequently, we quantified the required gate driving power and associated thermal losses as a function of the switching frequency. Through this model, we derive the maximum achievable switching frequency based on transistor parasitics. A case study is then conducted for buck and boost topologies operating in quasi-resonant mode, with an emphasis on evaluating drain current waveforms. Based on this analysis, a FOM was formulated to estimate the maximum switching frequency supported by commercial GaN FETs, such as those from (EPC) Efficient Power Conversion Corporation (See Appendix A). The principal contribution of this work is the establishment of the layout design rules that enable GaN FETs to operate at their maximum switching frequency, thereby facilitating the development of high-frequency CoC converters.

Throughout this paper, the term “GaN FET” refers specifically to enhancement-mode GaN high electron mobility transistors (HEMTs). This usage is consistent with prevailing industry nomenclature, wherein manufacturers such as EPC refer to their normally off GaN HEMTs as “GaN FETs” in data sheets and application nots. This convention is adopted here to align with practical terminology in converter design and device selection.

To clarify the structure of the paper, Section 2 lays the modeling foundation, whereas the core analytical contributions and design methodology are developed in Section 3, Section 4, Section 5 and Section 6.

2. GaN FET Electrical Model

To derive an analytical expression for the maximum switching frequency of GaN-based power converters, a comprehensive, frequency-dependent loss model for the switching device is essential. This section introduces a compact electrical model of a GaN FET that accounts for key loss mechanisms, including gate drive losses, output charge dissipation, conduction losses, and commutation losses. Each of these mechanisms is expressed as a function of the switching frequency, parasitic device parameters, and input operating conditions. This model forms the basis for the analytical Figure of Merit for Soft Switching (FOM_SS) proposed in Section 6, which characterizes the frequency limitations imposed by internal charge dynamics and associated power losses.

The selected GaN FET model shares similarities with conventional MOSFET model. A basic electrical representation of GaN FETs was previously introduced in [33]. At high frequencies, the internal wiring of the device introduces parasitic inductance, while the substrate layers act as parasitic capacitances. Although these parasitic inductances—typically ranging from a few hundred femtohenries to a few picohenries—are negligible at conventional switching frequencies (on the order of hundreds of kilohertz) [34] they become increasingly significant as the switching frequency approaches the hundreds of megahertz range. Consequently, these parasitics must be incorporated into the device model, as shown in [33] and illustrated in Figure 1, to accurately reflect the behavior of GaN transistors in high-frequency applications. The modeled device corresponds to a monolithic enhancement-mode GaN-on-Si HEMT, not a cascode configuration with a Si MOSFET.

The drain current (I_D) in a GaN FET is a nonlinear function of the drain, gate, and source voltages (V_D, V_G, V_S). Similarly, the gate-to-source (C_GS) and the gate-to-drain (C_DG) capacitance are voltage-dependent, influenced by V_D, V_G, V_S. The drain-to-source capacitance (C_DS) is also nonlinear function, primarily dependent on V_D, and V_S. In contrast, parasitic resistances at the gate and drain terminals (r_G, r_Ds) are assumed to be constant, determined by intrinsic device structure, packaging, and layout characteristics.

When the power converter is implemented on a PCB rather than as a monolithic converter on chip (CoC), the influence of parasitic elements becomes increasingly pronounced at higher switching frequencies. As the operating frequency approaches the sub-gigahertz regime, the impedance introduced by gate inductance is no longer negligible. This inductance contributes additional harmonics to the gate signal, inducing current fluctuations and potential instability within the device channel. The parasitic gate inductance effectively transforms the gate drive dynamics from a first-order RC system to a second-order RLC network, necessitating careful damping analysis to avoid undesirable oscillations. Although capacitor impedance ($X_C$) decreases with frequency, the energy required to charge the gate capacitance in each cycle becomes a dominant factor in switching losses. Despite this, due to the relatively small values of gate inductance (on the order of a few nanohenries [35]) and the typically low gate capacitance (a few picofarads), the capacitive reactance remains significantly higher than the inductive reactance $X_C⋙X_L$, holds across most of the operating frequency range. As illustrated in Figure 2, the active charge path (red) and the associated parasitic return loops (green) emphasize that capacitive charging dominates the gate dynamics. As a result, the power loss in the gate drive circuit remains strongly frequency-dependent, and is quantified by the expression provided in Equation (1).

$$P_{G,drv}\cong Q_{GS}·V_{GS}·f_{SW}$$

(1)

where $Q_{GS}$ is the gate to source charge, $V_{GS}$ is the gate drive voltage, and $f_{SW}$ is the switching frequency. This expression highlights the frequency-dependent nature of gate drive losses in high-speed switching applications. When the converter is implemented as a CoC, the interconnected traces are significantly shorter than those on a conventional PCB. In addition, there are no external package terminals, which substantially reduces parasitic inductance–often to negligible levels. However, even in a CoC architecture, fast voltage transients on the drain terminal ($dv/dt$) can couple through the Miller capacitance $C_{GD}$, disturbing the intended gate operation. This phenomenon is illustrated in Figure 3 and can lead to unintended switching events or increased switching losses. The dynamic output power loss, primarily associated with the charging and discharging of parasitic output and Miller capacitances, can be approximated by

$$P_{DYN}=P_{Q,OSS}\cong (Q_{DS}+Q_{GD})·V_{DS}·f_{SW}$$

(2)

where $Q_{DS}$ and $Q_{GD}$ are the drain-to-source and gate-to-drain charges, respectively, and $V_{DS}$ is the drain-to-source voltage. These losses represent a major component of the total switching loss, particularly in high-frequency GaN-based power converters.

The total channel losses in the GaN FET (i.e., across the drain to source path) consist of both static (conduction) and dynamic components. The static conduction losses can be approximated as

$$P_{STAT}\cong \left({{I_{L,avg}}^2+\left(I_{L,M}/\sqrt{3}\right)}^2\right)·t_{on}·f_{SW}·r_{DS}$$

(3)

where $I_{L,avg}$ is the average inductor current, $I_{L,M}$ is the amplitude of the triangle current waveform, $t_{on}$ is the ON-time of the transistor. based on standard GaN FET construction [33], the drain-to-gate surface distance is much longer than the source to the gate. Therefore, the ON-conduction resistance is $r_{DS}$ as presented in Figure 3.

One of the primary sources of thermal energy loss is the conduction current flowing through $r_{DS}$. A secondary, yet non-negligible, source—especially at high frequencies—is the static gate loss caused by the internal gate resistance $r_G$. While the loss is minor at conventional switching frequencies, it becomes increasingly relevant at sub-GHz frequencies. The gate current flows during the short intervals of gate charge and discharge, which follow an exponential profile.

Assuming the charging interval extends from $t=0$ to $t=5\tau$, where τ is the time constant of the gate RC circuit, the gate voltage reaches its full value. Discharge similarly occurs within the same time constant interval. The total time constant is defined as $\tau =C_g·r_{GT}$ where $C_g$ is the total gate capacitance and $r_{GT}=r_G+R_{drv}$ is the combined gate resistance, including the internal device resistance and the external gate driver resistance. Under these conditions, the RMS gate current is approximated by

$$I_{G,rms}\cong V_{drv}\sqrt{f_{sw}·C_G/r_{GT}}$$

(4)

where $V_{drv}$ is the gate drive voltage. This equation quantifies the increasing importance of gate resistance at high switching frequencies.

Following the RMS gate current derivation, the corresponding average gate dynamic power dissipation is expressed as

$$P_{G,DYN}\cong {V_{drv}}^2·f_{sw}·C_G$$

(5)

This power loss arises from the periodic charging and discharging of the gate capacitance through the gate driver resistance. Although small at lower frequencies, this term becomes increasingly relevant in high-frequency GaN-based switching environments.

Another critical component of loss is the commutation loss—dissipated during the brief intervals when both voltage and current overlap at the device terminals during turn-on and turn-off transitions. These transitions are typically characterized by a linear ramp of voltage and current, dividing the switching event into rise and fall times. The corresponding commutation loss can be estimated by

$$P_{COMM}=V_{DS}·I_D·\left(\left(Q_{GS}+Q_{GD}\right)/I_G\right)·f_{sw}$$

(6)

In specific converter topologies, such as resonant or soft-switching converters, these commutation losses can be significantly mitigated or entirely eliminated by enforcing ZVS and ZCS.

Additionally, external gate drive losses occur due to the resistive drop across resistors ($R_{drv}$) in the gate driver circuitry, as illustrated in Figure 3. The total power dissipation of a GaN transistor, considering all major mechanisms—gate drive, conduction, output charge, and commutation—is approximated by

$$P_{GaN}\cong P_{G,DYN}+P_{STAT}+P_{DYN}+P_{COMM}$$

(7)

These cumulative losses grow proportionally with switching frequency, directly impacting thermal performance and efficiency. Equations (2), (3), (5), and (6) collectively describe this frequency-dependent behavior.

3. Constraints on Switching Frequency

GaN FETs have demonstrated significant performance advantages over conventional Si transistors across a wide range of DC-DC power converters applications [36]. GaN devices not only offer reduced static (conduction), dynamic (switching), and commutation losses compared to their Si counterparts, but also enable operation at substantially higher switching frequencies—potentially in the sub-gigahertz range.

A critical factor limiting the maximum switching frequency is the interplay between the transistor’s parasitic parameters—particularly the gate resistance ($r_G$), gate-driver resistance ($R_{drv}$), and the intrinsic capacitances ($C_{GS}, C_{GD}, C_{DS}$). The physical layout of the transistor die fundamentally determines these parameters. For instance, increasing the die area can reduce the ON-state resistance ($r_{DS}$) and support higher current ratings, but it also increases intrinsic capacitances proportionally, which in turn increases the charge/discharge time. Since charge defined as $Q=C·V=I·t$, the time required to charge and discharge the gate capacitance is determined by the available current and resistance in the path. Thus, a trade-off exists between achieving low conduction losses and minimizing dynamic delay caused by capacitive effects.

3.1. Input and Output Capacitance Constraints

As illustrated in Figure 2, the charging and discharging path for the input capacitance (C_GS) involve the driver resistance ($R_{drv}$), gate resistance ($r_G$) channel resistance ($r_{DS}$), and gate/source parasitics (L_G, L_S). A Kirchhoff’s Voltage Law (KVL) analysis of the gate loop reveals a second-order differential equation governing the gate voltage. Under the assumption of CoC implementation, the parasitic inductance L_G can be considered negligible due to extremely short interconnect lengths (on the order of sub-picoHenries). In such scenarios, the gate current $i_G\left(t\right)$ becomes a third-order function of $R_{drv}$, $r_G$, and C_GS, which typically requires numerical methods for accurate time-domain solutions.

To evaluate the timing limitations introduced by capacitive networks, the Elmor delay (ED) model—a widely accepted technique for estimating signal propagation delays in RC ladder networks—can be employed [37]. The Elmore delay represents the first moment (center of gravity) of the voltage impulse response and is expressed as

$$ED\equiv {\int }_0^{\mathrm{\infty }}t·V\left(t\right)dt$$

(8)

For a cascaded RC ladder network, such as the gate drive circuit, the Elmore delay approximation simplifies to

$$ED=R_1\left(C_1+..+C_n\right)+R_2\left(C_2+..+C_n\right)+\dots +R_n{C}_n$$

(9)

This expression provides a closed-form estimate of the charging delay associated with layered resistance–capacitance structures and is instrumental in evaluating the upper switching frequency limit imposed by gate charge dynamics.

As shown in Figure 4, the ED model provides a compact and intuitive approximation of signal propagation delay within resistive-capacitive (RC) ladder networks. It should be noted that this RC-based analysis is strictly valid under CoC conditions where parasitic inductances remain negligible. In layouts with significant L_G or L_S, a full RLC treatment would be required. Originally formulated for small-signal timing in integrated circuits [30], the ED method is particularly appropriate in the context of converter-on-chip (CoC) designs, where the gate driver, GaN FET, and other passive elements are integrated monolithically. In such a scenario, parasitic inductances are minimized, and resistive-capacitive interactions dominate the switching dynamics. The equivalent charging time constant of the gate path is approximated by ${\tau }_c\cong R_{\mathrm{d}\mathrm{r}\mathrm{v}}\left(C_{\mathrm{d}\mathrm{r}\mathrm{v}}+C_{\mathrm{G}}\right){+r}_{\mathrm{G}}{C}_{\mathrm{G}}$. Assuming a first-order exponential behavior, the gate charging current becomes

$$i_{G-c}\left(t\right)=\left(V_{drv}/r_{GT}\right)·e^{-t/{\tau }_c}$$

(10)

where $r_{GT}=r_G+R_{drv}$ represents the total series resistance. A similar expression applies to the gate discharge path, which is governed by

$${\tau }_d\cong C_{drv}\left(r_G+R_{drv}\right)$$

(11)

and

$$i_{G-d}\left(t\right)=\left(V_{gs,max}/r_{GT}\right)·e^{-t/{\tau }_d}$$

(12)

Due to the typically larger gate capacitance $C_G$ and resistance $r_G$, the discharge time constant ${\tau }_d$ is significantly shorter than the charging time constant ${\tau }_c$. Gate threshold voltage ($V_{th}$) instability is a well-documented phenomenon [38], often influenced by device aging, temperature, and bias stress. For this analysis, we assume that

• $V_{drv}=V_{gs,max}=V_g$
• $V_{th}=0.5V_g$

Under this assumption, the average gate current during charging becomes

$$I_{G,avg}\cong 0.367·V_g/r_{GT}$$

(13)

Furthermore, using the root-mean-square formulation, the gate current is given by

$$I_{G,rms}\cong V_{DRV}\sqrt{f_{sw}·C_G/r_{GT}}$$

(14)

This result is consistent with the earlier expression in (4), thus validating the Elmore delay assumption.

By combining Equation (13) with the charge–time relationship, the maximum allowable switching frequency imposed by gate charge is

$$f_{SW{-Q}_G,max}\cong 0.367·V_g/\left(Q_G·r_{GT}\right)$$

(15)

The energy per switching event drawn from the gate driver is

$$E_{DRV}\cong 1.5·{V_{DRV}}^2·C_G$$

(16)

The discharging path of the output capacitance (C_DS) includes the drain inductance (L_D), on-state resistance (r_DS), and power inductor. Applying KVL and neglecting interconnect parasitics in the CoC case, the drain current during output capacitance charging path becomes

$$i_D\left(t\right)={\displaystyle \frac{V_S}{L}}\left(t+r_{ds}·C·e^{{\displaystyle \frac{-t}{r_{ds}·C}}}\right)+{\displaystyle \frac{V_S}{R}}{e}^{{\displaystyle \frac{-t}{r_{ds}·C}}}\left(0\le t\le T\right)$$

(17)

where $V_S$ is the supply voltage, L is the sum of relevant inductances and C is the effective drain-to-source capacitance. Assuming minimal r_DS, low $C_{OSS}$, and a 50% duty cycle, the average drain current simplifies to

$$I_{D.avg}\cong V_S/\left(8·L·f_{sw}\right)$$

(18)

From this, the maximum switching frequency constrained by the output charge $Q_{OSS}$ is approximated as

$$f_{SW{-Q}_{OSS},max}\cong \sqrt{V_S/\left(8·L·Q_{OSS}\right)}$$

(19)

However, practical GaN converter designs operating in the hundreds of MHz almost universally rely on soft-switching techniques such as ZVS and ZCS [39], which significantly mitigate output commutation losses. Thus, the limitation set by Equation (19) is unlikely to be the true bottleneck in CoC implementations. Literature evidence [40,41] suggests that typical device charge ratios are $Q_{OSS}\cong {5·Q}_G$, and with typical values of $r_{GT}\cong 0.5 \mathsf{\Omega }$ Equation (15) yields

$${\displaystyle \frac{0.367}{0.5}}>{\displaystyle \frac{1}{\sqrt{8}}}⟹f_{SW{-Q}_G}>f_{SW{-Q}_{OSS},max}$$

(20)

Given that $\sqrt{V_S}>V_{drv}$, both bounds are close. Therefore, the final frequency constraint, considering both gate and output charging limitations, is

$$f_{SW,max}=\min \left\{f_{SW{-Q}_G,max},f_{SW{-Q}_{OSS},max}\right\}$$

(21)

Nevertheless, in practical high-frequency GaN applications, hard switching becomes infeasible due to excessive loss, thermal constraints, and instability [42,43]. Therefore, assuming soft-switching operation, the gate charge $Q_G$ remains the most critical parameter to determining the maximum achievable switching frequency.

3.2. CoC Operation Mode Constraints

In hard switching mode, the transistor is toggled between on and off states while the inductor current is non-zero. During this process, the overlap of the drain to source voltage and current results in substantial switching losses. Additionally, high-frequency ringing is commonly observed due to parasitic interactions, particularly via the Miller (gate–drain) capacitance. This ringing can lead to gate voltage overshoot and false turn-on events, necessitating a reduction in switching speed via increased gate resistance. However, such a tradeoff imposes a limitation: hard-switching converters cannot simultaneously achieve both reduced switching losses and electromagnetic noise.

In contrast, soft switching techniques are widely adopted in PWM converters and are essential in CoC applications. The critical conduction mode (CRCM) is fundamental and effective strategy to realize ZVS during transistor turn-on. CRCM is prevalent in medium-low power designs due to its relative simplicity and the ability to suppress switching losses and noise through ZVS/ZCS transitions. Despite these advantages, CRCM increases the conduction losses due to elevated peak and the RMS current. Specifically, the inductor peak current twice the average inductor current in CRCM, resulting in a higher RMS drain current given by

$$I_{D,rms-CRCM}=2·\left(\sqrt{D/3}\right)·I_{D.avg}$$

(22)

where $D$ is the duty cycle of the converter, representing the fraction of the switching period during which the switch is on.

Consequently, conduction losses may increase by approximately 33.09% compared to continuous conduction mode (CCM), although switching losses are substantially reduced—often to near-zero—due to ZVS and ZCS in the synchronous rectifier. It should be emphasized that while ZVS and ZCS mitigate most switching-related losses, they do not eliminate all dissipation mechanisms. Residual losses remain from charging and discharging the output capacitance ($C_{OSS}$) and gate drive power. Therefore, CRCM is particularly effective in scenarios where switching losses dominate over conduction losses [36]. Although CRCM may not universally outperform CCM across all converter topologies, its use in high-frequency, on-chip GaN-based converters is justified. In such systems, switching losses are amplified by high frequencies and parasitics, which are effectively minimized using CRCM. This aligns with the objective of the proposed model—to identify the frequency-limiting parasitic mechanisms under soft-switching conditions compatible with CoC constraints.

When utilizing any soft-switching method—CRCM, quasi-resonant, or resonant—the energy associated with the output charge $Q_{OSS}$ is partially recycled through the input/output capacitors. Typically, this process is brief (on the order of picoseconds to nanoseconds) and does not interfere with the overall timing. However, as the switching frequency approaches the upper operating limit, the duration of output capacitance discharge can constitute over 30% of the switching period, thus becoming a significant design consideration in sub-gigahertz converter.

In conventional converter, the inductor current waveform forms a triangular shape composed of linear rising and falling segments with slopes $m_2$ (charging) and $m_1$ (discharging), as illustrated in Figure 5. The charging interval comprises the output capacitance discharge time of the main switch ($t_2$) followed by the inductor current ramp-up duration ($t_C=DT$). Conversely, the discharging interval includes the output capacitance discharge of the synchronous rectification ($t_1$) and the inductor current ramp-down ($t_D=D_{1}T$).

Applying the linear current equation $y=mx+b$ and integrating the current to obtain electric charge the output capacitance discharge times are derived as

$$t_1=-DT·m_2/m_1$$

(23)

$$t_2=-DT·\left(2I_{L,avg}-I_{L,max}\right)/I_{L,max}$$

(24)

These expressions quantify the timing burden imposed by $C_{OSS}$ discharge under realistic operating conditions. In high-frequency CoC systems, failure to account for these intervals can result in overlap between switching events, leading to incomplete soft-switching and undesirable power loss.

The upper switching frequency limit in CoC systems is governed not only by parasitic parameters such as gate and output capacitances but also by the inherent trade-off between efficiency, current ripple, and ZVS/ZCS timing constraints. One of the critical limiting factors is the time required to discharge the output capacitance $C_{OSS}$, which must complete before conduction begins in order to maintain soft switching.

The inductor ripple current $\Delta i_L$ is given by

$$\Delta i_L=\sqrt{3\left({I_{L,RMS}}^2-{I_{L,avg}}^2\right)}$$

(25)

This ripple determines the minimum and maximum inductor currents during the switching cycle:

$$I_{Lmin}=I_{L,avg}-\Delta i_L$$

(26)

$$I_{Lmax}=I_{L,avg}+\Delta i_L$$

(27)

When the converter operates under soft-switching conditions (ZVS/ZCS), the transistor power losses are primarily due to conduction losses $P_{COND}$ (as in Equation (3)) and the gate dynamic losses $P_{G,DYN}$ (as in Equation (6)). Assuming all other components in the converter are ideal, the total power dissipation is attributed to the transistor, and hence the overall efficiency $\eta$ is approximated by

$$\eta \approx P_o/\left(P_o+P_{COND}+P_{G,DYN}\right)$$

(28)

Here, $P_o$ is the output power delivered by the converter.

Using this relationship and incorporating the time constraints associated with discharging $Q_{OSS}$ (as derived from Equations (23) and (24), the maximum allowable switching frequency under soft-switching conditions is defined as

$$f_{SW}\le {\displaystyle \frac{1-\frac{P_o\left(\frac{1}{\eta }-1\right) }{{I_{RMS}}^2·r_{DS}}}{\left(\frac{2Q_{OSS}}{\left|I_{Lmin}\right|}\left(\frac{m_2}{m_1}·\frac{I_{Lmax}}{\left|I_{Lmin}\right|}+1\right)-\frac{V_{drv}·Q_G }{{I_{RMS}}^2·r_{DS}}\right)}}$$

(29)

where $I_{RMS}$ is the RMS current flowing through the transistor’s drain-source channel.

This equation defines the upper frequency boundary for CoC systems operating under idealized soft-switching conditions. It captures the balance between conduction losses, dynamic gate charge losses, and the required discharging time for $Q_{OSS}$, all of which are critical to maintaining ZVS and ZCS operation. The condition in (29) emphasizes the nonlinear interaction between transistor parameters (e.g., $Q_G, Q_{OSS}, r_{DS}$), circuit operating points (e.g., $I_{L,min}, I_{L,max}$), and converter efficiency. As switching frequency increases, even under ZVS/ZCS, parasitic delays and residual losses impose a hard boundary on system performance.

$$f_{SW,Buck}\le {\displaystyle \frac{ {I_{L,RMS}}^2·r_{DS}-P_S\left(\frac{1}{\eta }-1\right)}{\left(\frac{2Q_{OSS}· {I_{L,RMS}}^2·r_{DS}}{\left|I_o-\sqrt{3\left( {I_{L,RMS}}^2-{I_O}^2\right)}\right|}\left(\frac{V_s-V_o}{V_o}·\frac{I_o+\sqrt{3\left( {I_{L,RMS}}^2-{I_O}^2\right)}}{\left|I_o-\sqrt{3\left( {I_{L,RMS}}^2-{I_O}^2\right)}\right|}+1\right)-V_{drv}·Q_G\right)}}$$

(30)

$$f_{SW,Boost}\le {\displaystyle \frac{ {I_{L,RMS}}^2·r_{DS}-P_o\left(\frac{1}{\eta }-1\right)}{\left(\frac{2Q_{OSS}· {I_{L,RMS}}^2·r_{DS}}{\left|I_s-\sqrt{3\left( {I_{L,RMS}}^2-{I_s}^2\right)}\right|}\left(\frac{V_s}{V_s-V_o}·\frac{I_s+\sqrt{3\left( {I_{L,RMS}}^2-{I_s}^2\right)}}{\left|I_s-\sqrt{3\left( {I_{L,RMS}}^2-{I_s}^2\right)}\right|}+1\right)-V_{drv}·Q_G\right)}}$$

(31)

$$f_{SW,Buckboost}\le {\displaystyle \frac{ {I_{L,RMS}}^2·r_{DS}-P_o\left(\frac{1}{\eta }-1\right)}{\left(\frac{2Q_{OSS}· {I_{L,RMS}}^2·r_{DS}}{\left|I_o-\sqrt{3\left( {I_{L,RMS}}^2-{I_O}^2\right)}\right|}\left(\left|\frac{V_s}{V_o}\right| ·\frac{I_o+\sqrt{3\left( {I_{L,RMS}}^2-{I_O}^2\right)}}{\left|I_o-\sqrt{3\left( {I_{L,RMS}}^2-{I_O}^2\right)}\right|}+1\right)-V_{drv}·Q_G\right)}}$$

(32)

3.3. Buck CoC Constraints

The buck converter is the most widely use application due to its simplicity and compatibility with PWM control. A typical PWM buck converter requires a high-side driver, as the control circuit shares a common ground with power stage. In traditional implementations, the driver supply voltage is generated using a bootstrap mechanism due to its cost-effectiveness and compactness [31]. However, at switching frequencies in the tens of megahertz range, the repeated charging and discharging of the bootstrap capacitor introduce performance limitations, particularly in sustaining high-frequency operation. This poses a design challenge in high-frequency buck CoC circuits. For CCM, the minimum inductance required to prevent discontinuous operation is: $L_{min}=V_O(1-D)/\left(2·I_O·f_{SW}\right)$ where $V_O$ and $I_O$ are the output voltage and current, and D is the duty cycle. In discontinuous conduction mode (DCM) the output voltage is given by: $V_O=V_S·D/\left(D+D_1\right)$, where ${\mathrm{V}}_{\mathrm{S}}$ is the supply voltage, and ${\mathrm{D}}_1$ is the discharge duty cycle. The average inductor current is $I_{L,avg}={0.5·I}_{L,max}\left({D+D}_1\right)=I_O$. The current slopes in a buck are $m_1=-V_o/L$, and $m_2=\left(V_s-V_o\right)/L$.

Since the inductor average current equals the DC load current, the input RMS current is $I_{S,rms}=D·I_{L,RMS}$. By combining these parameters with Equations (25)–(29) and assuming the drain to source voltage of the GaN FET is 80% of the absolute maximum rating, the upper switching frequency constraint for the buck CoC is given by Equation (30).

In this derivation, the input power is expressed as $P_S= V_S·I_S$ for compactness, rather than directly in terms of the output power. Since $P_O=\eta ·P_S$, both forms are mathematically equivalent.

3.4. Boost CoC Constraints

The boost converter is a prevalent non-isolated topology, commonly employed in applications such as grid-connected rectifiers. While boost converters can operate in CCM with hard switching, CoC implementation requires operation in CRCM or DCM to ensure soft switch (ZVS, ZCS). For CCM, the minimum inductor value is defined by: $L_{min}=V_{O}D{(1-D)}^2/\left(2·I_O·f_{SW}\right)$. The DCM transfer function is $V_O=V_S\left(D+D_1\right)/D_1$. The average diode current is $I_{F,AVG}={0.5I}_{L,max}·D_1=I_O$. Solving for $D_1$: $D_1=(2{L·I}_O·f_{SW})/\left(V_{S}D\right)$. Current slopes are defined as $m_1=V_s-V_o/L$, $m_2=V_s/L$. The input source current, denoted as $I_S$, corresponds to the average current drawn from the supply. Under soft-switching operation in boost CoC converters, the converter’s input RMS current is $I_{S,RMS}=\left(D+D_1\right)·I_{L,RMS}$. Using these expressions with Equations (25)–(29), and again assuming a drain to source voltage of 80% of the maximum GaN FET rating, the upper switching frequency for the boost CoC is defined by Equation (31).

3.5. Formatting of Mathematical Components

The buck-boost converter is the third core topology evaluated for CoC implementation. Like the previous cases, soft-switching operation is mandatory for high-frequency performance. In this topology, the inductor average current equals the output load current: $I_O={0.5I}_{L,max}{D}_1=V_O/R$. The inductor current slopes are $m_1=-V_o/L$, $m_2=V_s/L$. The input RMS current is $I_{S,rms}=D{I}_{RMS}$. By applying the above parameters with the general constraints from Equations (25)–(29), and under the same voltage assumption as above, the maximum switching frequency for buck-boost CoC is expressed in Equation (32).

4. On-Chip Transistors Design Rules

To translate the switching frequency constraints derived in Section 3 into a practical design tool for GaN-based CoC systems, this section lays the groundwork for the FOM formulation, which is formally introduced in Section 5. This FOM is based on the dominant parasitic parameters of GaN transistors: gate charge ($Q_G$), output charge ($Q_{OSS}$), and on-state resistance ($r_{DS}$). These parameters, shown previously to limit the upper switching frequency, are now systematically analyzed to define design constraints across various topologies and GaN FET implementations, focusing on devices from EPC.

The actual upper-bound operating frequency of converter is affected by a range of parameters—some intrinsic to the transistor and others topology-dependent. Based on earlier analysis and practical design considerations, the following assumptions are made to standardize the model:

4.1. Assumptions and Design Constraints

(1)

GaN FET gate inductance

Regarding implementations, the interconnect length is extremely short and terminal pads are minimized, rendering gate inductance neglectable.

(2)

Switching timing

Charging and discharging durations are each assumed to span five-time constants (τ), making the total switching period ten τ.

(3)

Duty Cycle

A symmetric PWM operation is assumed, with a duty cycle of 50%.

(4)

Threshold Voltage

The gate threshold voltage is considered to be 50% of the gate drive voltage.

(5)

Charge Relationship

The output charge is assumed to be approximately five times the input charge: $Q_{OSS}\approx 5Q_G$

(6)

Switching Conditions

All converters are assumed to operate under ZVS/ZCS conditions.

(7)

Elmor Delay Model

Regarding implementations, the interconnect length is extremely short and terminal pads are minimized, rendering gate inductance neglectable.

(8)

On-State Resistance vs. Gate Resistance

The on-state resistance (r_DS(ON)) is assumed to be much lower than the internal gate resistance (r_G) and thus dominates conduction losses.

(9)

Operating Conditions

• Soft switching is maintained across all topologies.
• The drain to source voltage is set to 80% of the absolute maximum rating.
• The drain RMS current is defined as: $I_{D,RMS}=I_{max,cont}/\sqrt{2}$; where $I_{max,cont}$ is the manufacturer-specified maximum continuous current.
• The converter efficiency is fixed at 90%. Input and Output Charge Constraints on Switching Frequency.

As noted in earlier sections, the asymmetry in GaN transistor structure—where the gate area is considerably smaller than the drain—results in a smaller input gate charge ($Q_G$) compared to the output charge ($Q_{OSS}$). This distinction is pivotal when evaluating upper switching frequency limits, as each parasitic charge type imposes different constraints based on the converter’s operating conditions and topology.

The soft-switching boundary defined in (29) is derived based on nominal device parameters and idealized timing assumptions. While practical variations, such as threshold voltage shifts due to temperature or aging, $V_{DRV}$ tolerances, or duty-cycle asymmetry, can influence the maximum achievable $f_{SW}$, the dominant limiting mechanisms (gate-drive delay, output commutation time, and conduction losses) remain structurally valid. In practical designs, such non-idealities can be accommodated by applying conservative design margins to critical parameters, ensuring robustness without compromising the analytical usefulness of the proposed bound.

4.2. Output Charge Constraints (Q_OSS)

The maximum allowable switching frequency constrained by output charge ($Q_{OSS}$) has been analyzed across the entire EPC GaN FET catalog. These calculations, derived from (19), identify the lower frequency bounds imposed by parasitic output capacitance in soft-switched systems:

• For high-power transistors, such as the EPC2024 (40 V/90 A), the minimum upper bound is approximately 0.33 GHz.
• For low-power devices, such as the EPC2038 (100 V/0.5 A), the maximum switching frequency is around 9.66 GHz.

These results are summarized in Figure 6, which illustrates the upper switching frequency boundary as a function of $Q_{OSS}$.

To facilitate quick estimation, a two-term exponential fitting function relates the maximum frequency $f_{SW}$ in GHz to $Q_{OSS}$ in Coulombs:

$$Q_{OSS}={\displaystyle \frac{1231·e^{-2.05·f_{SW}}+5.583·e^{-0.039·f_{SW}}}{{10}^{10}}}$$

(33)

This empirical expression allows CoC designers to select devices that meet a specific frequency target by ensuring the transistor output charge remains within acceptable bounds.

4.3. Input Charge Constraints (Q_G)

While $Q_{OSS}$ constrains switching through output charge recycling, input charge $Q_G$ governs gate driving losses and delay, becoming the primary limit in ultra-high-frequency designs. Calculations based on (15) show

• The lowest upper bound limited by $Q_G$ is ~0.3 GHz, observed in high-power transistors like the EPC2053 (100 V/26 A).
• The highest operating frequency achieved is ~41 GHz, corresponding to the EPC8002 (40 V/0.5 A), a low-power high-speed transistor.

The correlation between $Q_G$ and maximum allowable $f_{SW}$ is captured in Figure 7, using a similar exponential fitting model:

$$Q_G={\displaystyle \frac{263.6·e^{-1.977·f_{SW}}+1.246·e^{-0.3692·f_{SW}}}{{10}^{10}}}$$

(34)

This formula provides a practical upper frequency constraint due to gate drive charge, enabling layout engineers to preemptively eliminate devices incompatible with high-speed gate requirements in CoC converters.

5. Design Implications and Frequency-Dependent Figures of Merit

As concluded from Section 4, the maximum switching frequency of a GaN FET in a CoC system is primarily constrained by the parasitic charges $Q_G$ and $Q_{OSS}$, and by the on-state resistance $r_{DS}$. These parameters collectively define the figure of merit for soft-switching (FOM_SS), serving as the basis for high-frequency power converter design. While Equation (21) defines the absolute upper switching frequency, it is insufficient to characterize the transistor’s power-handling capability. To bridge this gap, the maximum energy transferred per switching cycle was estimated for each EPC transistor, assuming nominal conditions as per the eight design rules outlined earlier. The result, illustrated in Figure 8, shows a power-law relationship between switching frequency and per-cycle energy transfer, given by

$$E_{per-cycle}=1.045·{10}^{-6}·{f_{SW}}^{-2.47}$$

(35)

This empirical model reveals a fundamental tradeoff between switching frequency and power throughput, highlighting the energy constraints of high-speed operation in CoC systems.

5.1. Topology-Specific Charge–Frequency Relationships

To generalize frequency limits across common converter topologies, transistor-level charge limits were modeled for buck, boost, and buck-boost converters. Each was analyzed under the same baseline assumptions, and Equations (30)–(32) were used for switching frequency constraints.

5.1.1. Buck Converter

• Input charge versus frequency (Figure 9):

$$Q_G=-1.24·{10}^{-9}·log\left(f_{SW}\right)+3.3007·{10}^{-8}$$

(36)

• Output charge versus frequency (Figure 10):

$$Q_{OSS}=-1.032·{10}^{-17}·f_{SW}+9.144·{10}^{-9} .$$

(37)

5.1.2. Boost Converter

• Input charge versus frequency (Figure 11):

$$Q_G=2.275·{10}^{-17}·f_{SW}-4.138·{10}^{-9}$$

(38)

• Output charge versus frequency (Figure 12):

$$Q_{OSS}={\displaystyle \frac{2.261}{{10}^{33}}}{f_{SW}}^3-{\displaystyle \frac{2.943}{{10}^{24}}}{f_{SW}}^2+{\displaystyle \frac{1.288}{{10}^{15}}}{f}_{SW}-1.661·{10}^{-7}$$

(39)

5.1.3. Buck-Boost Converter

• Input charge versus frequency (Figure 13):

$$Q_G=-9.1884·{10}^{-19}·f_{SW}+8.2628·{10}^{-9}$$

(40)

• Output charge versus frequency (Figure 14):

$$Q_{OSS}=-2.025·{10}^{-18}·f_{SW}+2.315·{10}^{-8}$$

(41)

5.2. Figure of Merit for Soft Switching (FOM_SS)

To unify the influence of gate and output charges with conduction loss, a generalized figure of merit is proposed, as presented in [44]:

$$FO{M}_{SS}=(Q_{OSS}+Q_G)·R_{DS}$$

(42)

This FOM quantifies the charge–resistance tradeoff critical to efficient soft-switching operation. Figure 15 presents FOM_SS vs. drain current I_D for six GaN transistor voltage classes, denoted as groups A–F.

Due to the inherent dependence of key GaN transistor parameters, such as $Q_G$, $Q_{OSS}$, and $R_{DS}$, on the rated $V_{DS}$, segmentation into discrete voltage classes allows for more consistent modeling of device behavior under soft-switching conditions. This classification reduces parameter variation within each group and avoids distortion of the FOM_SS metric by excluding devices with inherently different electrical characteristics.

While the structure of FOM_SS in (42) is based on [44], its plication in this work goes beyond comparative device evaluation. Here, FOM_SS is directly integrated into analytically derived switching frequency bounds (Equations (29)–(32)), allowing it to serve as a predictive design parameter for evaluating $R_{DS}$ under soft-switching conditions in CoC systems.

5.3. FOM_SS by Voltage Class

To standardize comparison, the Y-axis intercept of each linear fit (where the slope is at least three times smaller than the intercept) is taken as the characteristic FOM_SS for each group.

5.4. Scope and Methodological Consistency

All simulations and FOM_SS derivations utilize GaN FETs from EPC to maintain consistent data sourcing and modeling fidelity. While this excludes cross-manufacturer benchmarking, it ensures methodological rigor. EPC’s comprehensive datasheet information, consistent packaging, and diverse product range make it ideal for establishing generalized design guidelines.

Given the proprietary variations in layout, gate architecture, and manufacturing process among GaN vendors, extending this framework across brands would introduce variability incompatible with the controlled assumptions required for analytical clarity. As such, EPC serves not as a commercial benchmark but as a reference platform for scientifically grounded design rule extraction.

6. Case Study: Validation of FOM_SS

To validate the proposed FOM_SS methodology, five GaN FETs from EPC were intentionally selected as a device that was not included in the original dataset used to derive the FOM_SS voltage classes (Figure 15 and

Table 1. Figure of Merit for Soft-Switching GaN FET EPC Transistors.

Group	VDS	FOMSS
A	40 [V]	$1·{10}^{-10}$
B	60 [V]	$1.62·{10}^{-10}$
C	80 [V]	$1.95·{10}^{-10}$
D	100 [V]	$2.01·{10}^{-10}$
E	150 [V]	$3.45·{10}^{-10}$
F	200 [V]	$7.2·{10}^{-10}$

). The focus of the study is on EPC2205, which was employed in all experiments and simulations; however, the additional devices serve as independent validation cases across different voltage groups.

Table 2. Absolute maximum rating ⁽¹⁾ and parameters ⁽²⁾ of EPC devices.

Part Number	VDS (1)	ID (1)	VGS (1)	QG (2)	QOSS (2)	rDS,150° (2)
EPC2055	40 [V]	29 [A]	6 [V]	8.5 [nC]	13 [nC]	5 [mΩ]
EPC2102	60 [V]	30 [A]	6 [V]	8 [nC]	26 [nC]	4.9 [mΩ]
EPC2103	80 [V]	30 [A]	6 [V]	6.5 [nC]	30 [nC]	5.5 [mΩ]
EPC2044	100 [V]	29 [A]	6 [V]	4.3 [nC]	15 [nC]	10.5 [mΩ]
EPC2215	200 [V]	32 [A]	6 [V]	17.7 [nC]	104 [nC]	6 [mΩ]

summarizes the ratings and parameters of the selected devices, spanning voltage classes A, B, C, D, and F, thereby providing validation across a wide operating range. For each device, the characteristic FOM_SS value corresponding to its voltage class was used together with the manufacturer-specified Q_G and Q_OSS values in (42) to calculate the expected on-state resistance.

The derived values of R_DS are 5.1 mΩ (EPC2055, Group A), 4.76 mΩ (EPC2102, Group B), 5.34 mΩ (EPC2103, Group C), 10.41 mΩ (EPC2044, Group D), and 5.91 mΩ (EPC2215, Group F). These values show excellent agreement with the respective manufacturer datasheet specifications of 5.0, 4.9, 5.5, 10.5, and 6.0 mΩ.

The consistency across five independent devices and multiple voltage classes validates the analytical model.

6.1. Simulation-Based Frequency Verifications

Given the limitations of real-world components—such as gate drivers, ferrites, and packaging—the theoretical maximum frequency derived from the model requires practical validation through simulation. To this end, an LTSpice model was constructed using the EPC2055 GaN transistor model provided by the manufacturer, which includes dynamic characteristics ($Q_G, Q_{OSS}, R_{DS}$) consistent with datasheet values. The converter was implemented using a synchronous half-bridge buck topology, driven by ideal PULSE voltage sources for both the high-side and low-side switches. This setup intentionally omits gate drivers and other peripheral elements (e.g., level shifters) to isolate the intrinsic behavior of the GaN FET (

Table 3. Buck converter parameters.

${\mathit{V}}_{\mathit{S}}$	${\mathit{V}}_{\mathit{O}}$	${\mathit{V}}_{\mathit{D}\mathit{R}\mathit{V}}$	${\mathit{P}}_{\mathit{O}}$	$\mathit{\eta }$
32 [V]	16 [V]	5 [V]	100 [W]	90%

) and evaluate its theoretical switching frequency limit.

The converter operated under the nine design assumptions introduced earlier.

Applying these values to Equation (30), yields a theoretical maximum switching frequency of $f_{SW,Buck}\le 179.85 \left[\mathrm{M}\mathrm{H}\mathrm{z}\right]$.

The simulation results presented in Section 6.2 and Section 6.3 are based on this same LTSpice model (see Appendix B) and converter topology, operating under identical conditions and assumptions.

6.2. LT-Spice Simulation Results

Simulations were performed at three switching frequencies: 150 MHz (below), 175 MHz (near), and 190 MHz (above) the theoretical limit. Each test adjusted inductor and duty cycle values to maintain correct soft-switching and DCM behavior. Figure 16 illustrates the transient responses at each frequency. Efficiency exceeds 90% at 150 MHz and drops to 88.2% at 175 MHz, marking the onset of performance degradation. While this point falls slightly below the nominal 90% efficiency target, it remains consistent with the theoretical upper bound of $f_{SW,Buck}\le 179.85 \mathrm{M}\mathrm{H}\mathrm{z}$ under idealized assumptions. Simulation results are summarized in

Table 4. EPC2055 absolute maximum rating and parameters.

Parameter	Value #1	Value #2	Value #3	Units
Frequency	150	175	190	MHz
$\eta$	90.151	88.218	85.349	%
$V_{out}$	16.179	16.1948	16.1643	V
$P_{out}$	100.678	100.873	100.494	W
$P_{Q_1}$	5.637	5.8277	12.6052	W
$P_{Q_2}$	5.361	7.257	4.6446	W
$I_{out}$	6.222	6.228	6.217	A
$I_{RMS}$	21.349	22.436	23.472	A
${\mathrm{I}}_{\mathrm{L},max}$	38.381	40.034	40.979	A
${\mathrm{I}}_{\mathrm{L},min}$	−23.092	−24.112	−26.527	A
${\mathrm{m}}_2$	22.6808	28.4722	31.4227	×109
${\mathrm{m}}_1$	−23.189	−28.9721	−31.555	×109

. Practical non-idealities, such as parasitics, gate driver constraints, and ripple losses, shift the effective limit slightly lower, as confirmed in simulation.

6.3. Frequency-Domain Validation via FFT

To supplement the efficiency analysis, Fast Fourier Transform (FFT) was performed on time-domain simulation data from three key nodes: Switching node ($V_{SW}$), Output node ($V_{out}$), and Inductor current (${\mathrm{I}}_{\mathrm{L}}$). The frequency spectra at 50 MHz, 150 MHz, 175 MHz, and 190 MHz are plotted in Figure 17a–c using the following color scheme: Black: 50 MHz, Green: 150 MHz, Blue: 175 MHz, and Red: 190 MHz. Key observations include

• V_SW Spectrum (Figure 17a): At 190 MHz, harmonics above the fifth increase by ~4–6 dB, indicating heightened switching loss and parasitic excitation.
• V_out Spectrum (Figure 17b): Higher frequency noise rises by 3–5 dB at 175 MHz and 190 MHz, with emerging sidebands signaling electromagnetic interference (EMI) risks and potential instability.
• I_L Spectrum (Figure 17c): Higher frequency noise rises by 3–5 dB at 175 MHz and 190 MHz, with emerging sidebands signaling electromagnetic interference (EMI) risks and potential instability.

Figure 17. FFT spectra of buck converter nodes at 50–190 MHz: (a) $V_{SW}$, (b) $V_{out}$ and (c) ${\mathrm{I}}_{\mathrm{L}}$. The X-axis represents Frequency [Hz] and the Y-axis represents Amplitude [dB].

Figure 17. FFT spectra of buck converter nodes at 50–190 MHz: (a) $V_{SW}$, (b) $V_{out}$ and (c) ${\mathrm{I}}_{\mathrm{L}}$. The X-axis represents Frequency [Hz] and the Y-axis represents Amplitude [dB].

6.4. Conclusion of Case Study

The combination of efficiency metrics and spectral analysis confirms the analytically derived maximum switching frequency of ≈179.85 MHz for the EPC2055-based buck converter. While this value represents a theoretical upper bound, simulation results indicate the onset of performance degradation at 175 MHz. Operation at or above 190 MHz introduces excessive harmonic distortion, EMI, and reduced efficiency, thereby violating soft-switching conditions and underscoring the practical validity of the proposed FOM_SS-based approach.

7. Conclusions

This paper investigated the theoretical upper switching frequency boundary of GaN FET technology within the context of CoC integration. A comprehensive performance analysis was conducted on a wide family of EPC GaN devices, applying consistent assumptions to support the proposed theoretical framework. The study introduced a soft-switching figure of merit, which captures the trade-off between input and output charge and on-state resistance. A key contribution is the derivation of a compact expression—Equation (42)—linking maximum achievable switching frequency to basic device parameters such as gate charge and resistance. This relation enables prediction of the device’s high-frequency limits without reliance on empirical iteration or full-device modeling.

Time- and frequency-domain LTSpice simulations validated the theoretical results. These simulations showed that when operating near or beyond the calculated frequency limit, the converter exhibits notable spectral distortion, reduced efficiency, and increased power losses. The results confirm that dynamic switching losses, not static conduction losses, become the dominant limiting factor at high frequencies. Accordingly, achieving ZVS, and optionally ZCS, is essential to maintaining efficiency in high-frequency applications. The upper frequency boundary was shown to stem from the interplay between gate charge and on-state resistance. For the devices studied, theoretical switching limits were calculated to reach up to 2 GHz in buck configurations and 2.5 GHz in boost configurations, assuming idealized CoC conditions. These figures underscore that gate charge, rather than static losses, is the primary bottleneck in pushing frequency higher.

By linking switching limitations directly to internal device parameters—$Q_G$, $Q_{OSS}$, and $r_{DS\left(ON\right)}$—the proposed FOM_SS-based methodology enables targeted optimization of GaN device structures. This facilitates design strategies that move toward ultra-high-frequency CoC integration. The reported limits therefore represent the RC-dominant case of monolithic CoC integration. Extension of the framework to explicitly include RLC effects constitutes a natural direction for future investigation. A key design implication is that GaN FET manufacturers should prioritize optimization of the input charge distribution, especially gate charge, to unlock the upper-frequency potential of these devices. While this study centered on EPC devices, the core principles and modeling approach are broadly applicable to other GaN platforms.

Finally, while current gate drivers, passive components, and integration tools do not yet enable experimental validation at the predicted upper-frequency limits, the theoretical and simulation-based evidence strongly supports the validity of the FOM_SS approach. This work thus serves as a foundation for future advancements in high-speed GaN-based power conversion systems. In summary, while the proposed FOM_SS framework predicts theoretical GHz-range switching feasibility under idealized CoC assumptions, practical nonidealities in drivers, interconnects, and passives make it best regarded as a guiding design tool rather than a presently realizable operating limit.